Principles of Data Acquisition and Conversion
`
`Application Note
`
`October 1986
`
`AN002
`
`COMPUTER DATA BUS
`
`CONTROL
`
`CONVERTER
`
`A/D
`
`SAMPLE
`HOLD
`
`PROGRAMMER
`SEQUENCER
`
`ANALOG MULTIPLEXER
`
`TRANS-
`DUCER
`
`AMPLI-
`FIER
`
`ACTIVE
`FILTER
`
`PHYSICAL
`PARAMETER
`
`OTHER
`ANALOG
`CHANNELS
`
`FIGURE 1. DATA ACQUISITION SYSTEM
`
`The input to the system is a physical parameter such as
`temperature, pressure, flow, acceleration, and position,
`which are analog quantities. The parameter is first converted
`into an electrical signal by means of a transducer, once in
`electrical form, all further processing is done by electronic
`circuits.
`
`Next, an amplifier boosts the amplitude of the transducer
`output signal to a useful level for further processing.
`Transducer outputs may be microvolt or millivolt level signals
`which are then amplified to 1 to 10V levels. Furthermore, the
`transducer output may be a high impedance signal, a
`differential signal with common-mode noise, a current
`output, a signal superimposed on a high voltage, or a
`combination of these. The amplifier, in order to convert such
`signals into a high level voltage, may be one of several
`specialized types.
`
`The amplifier is frequently followed by a low pass active filter
`which reduces high frequency signal components, unwanted
`electrical interference noise, or electronic noise from the
`signal. The amplifier is sometimes also followed by a special
`nonlinear analog function circuit which performs a nonlinear
`operation on the high level signal. Such operations include
`squaring, multiplication, division, RMS conversion, log
`conversion, or linearization.
`
`The processed analog signal next goes to an analog
`multiplexer which sequentially switches between a number
`of different analog input channels. Each input is in turn
`connected to the output of the multiplexer for a specified
`period of time by the multiplexer switch. During this
`connection time a sample-hold circuit acquires the signal
`voltage and then holds its value while an analog-to-digital
`converter converts the value into digital form. The resultant
`digital word goes to a computer data bus or to the input of a
`digital circuit.
`
`Thus the analog multiplexer, together with the sample-hold,
`time shares the A/D converter with a number of analog input
`channels. The timing and control of the complete data
`acquisition system is done by a digital circuit called a
`programmer-sequencer, which in turn is under control of the
`
`Data Acquistion Systems
`Introduction
`Data acquisition and conversion systems interface between
`the real world of physical parameters, which are analog, and
`the artificial world of digital computation and control. With
`current emphasis on digital systems, the interfacing function
`has become an important one; digital systems are used
`widely because complex circuits are low cost, accurate, and
`relatively simple to implement. In addition, there is rapid
`growth in use of minicomputers and microcomputers to
`perform difficult digital control and measurement functions.
`
`Computerized feedback control systems are used in many
`different industries today in order to achieve greater
`productivity in our modern industrial society. Industries which
`presently employ such automatic systems include steel
`making, food processing, paper production, oil refining,
`chemical manufacturing, textile production, and cement
`manufacturing.
`
`The devices which perform the interfacing function between
`analog and digital worlds are analog-to-digital (A/D) and
`digital-to-analog (D/A) converters, which together are known
`as data converters. Some of the specific applications in
`which data converters are used include data telemetry
`systems, pulse code modulated communications, automatic
`test systems, computer display systems, video signal
`processing systems, data logging systems, and sampled
`data control systems. In addition, every laboratory digital
`multimeter or digital panel meter contains an A/D converter.
`
`Besides A/D and D/A converters, data acquisition and
`distribution systems may employ one or more of the
`following circuit functions:
`
`Basic Data Distribution Systems
`• Transducers
`
`• Amplifiers
`
`• Filters
`
`• Nonlinear Analog Functions
`
`• Analog Multiplexers
`
`• Sample-Holds
`
`The interconnection of these components is shown in the
`diagram of the data acquisition portion of a computerized
`feedback control system in Figure 1.
`
`1
`
`CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
`1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1986
`
`Apple 1022
`IPR of U.S. Pat. No. 6,470,399
`
`Apple 1022
`U.S. Pat. 9,189,437
`
`

`
`Application Note 002
`
`of discrete output states. Coding is the process of assigning
`a digital code word to each of the output states. Some of the
`early A/D converters were appropriately called quantizing
`encoders.
`
`Quantizer Transfer Function
`The nonlinear transfer function shown in Figure 3 is that of
`an ideal quantizer with 8 output states; with output code
`words assigned, it is also that of a 3-bit A/D converter. The 8
`output states are assigned the sequence of binary numbers
`from 000 through 111. The analog input range for this
`quantizer is 0 to +10V.
`
`There are several important points concerning the transfer
`function of Figure 3. First, the resolution of the quantizer is
`defined as the number of output states expressed in bits; in
`this case it is a 3-bit quantizer. The number of output states
`for a binary coded quantizer is 2n, where n is the number of
`bits. Thus, an 8-bit quantizer has 256 output states and a
`12-bit quantizer has 4096 output states.
`As shown in the diagram, there are 2n-1 analog decision
`points (or threshold levels) in the transfer function. These
`points are at voltages of +0.625, +1.875, +3.125, +4.375,
`+5.625, +6.875, and +8.125. The decision points must be
`precisely set in a quantizer in order to divide the analog
`voltage range into the correct quantized values.
`
`The voltages +1.25, +2.50, +3.75, +5.00, +6.25, +7.50, and
`+8.75 are the center points of each output code word. The
`analog decision point voltages are precisely halfway
`between the code word center points. The quantizer
`staircase function is the best approximation which can be
`made to a straight line drawn through the origin and full
`scale point; notice that the line passes through all of the
`code word center points.
`
`Q
`
`+1.25 2.50 3.75 5.00 6.25 7.50 8.7510.00
`INPUT VOLTAGE (+)
`
`Q
`
`111
`
`110
`
`101
`
`100
`
`011
`
`010
`
`001
`
`000
`
`OUTPUT CODE
`
`8 7 6 5 4 3 2 1
`
`OUTPUT STATES
`
`QUANTIZER
`ERROR
`
`+Q/2
`0
`-Q/2
`
`FIGURE 3. TRANSFER FUNCTION OF IDEAL 3-BIT QUANTIZER
`
`computer. In some cases the computer itself may control the
`entire data acquisition system.
`
`While this is perhaps the most commonly used data
`acquisition system configuration, there are alternative ones.
`Instead of multiplexing high-level signals, low-level
`multiplexing is sometimes used with the amplifier following
`the multiplexer. In such cases just one amplifier is required,
`but its gain may have to be changed from one channel to the
`next during multiplexing. Another method is to amplify and
`convert the signal into digital form at the transducer location
`and send the digital information in serial form to the
`computer. Here the digital data must be converted to parallel
`form and then multiplexed onto the computer data bus.
`
`Basic Data Acquisition System
`The data distribution portion of a feedback control system,
`illustrated in Figure 2, is the reverse of the data acquisition
`system. The computer, based on the inputs of the data
`acquisition system, must close the loop on a process and
`control it by means of output control functions. These control
`outputs are in digital form and must therefore be converted
`into analog form in order to drive the process. The
`conversion is accomplished by a series of digital-to-analog
`converters as shown. Each D/A converter is coupled to the
`computer data bus by means of a register which stores the
`digital word until the next update. The registers are activated
`sequentially by a decoder and control circuit which is under
`computer control.
`
`REGISTER
`
`D/A
`CONVERTER
`
`ACTUATOR
`
`PROCESS
`PARAMETER
`
`REGISTER
`
`D/A
`CONVERTER
`
`ACTUATOR
`
`PROCESS
`PARAMETER
`
`DECODER
`AND
`CONTROL
`
`COMPUTER DATA BUS
`
`CONTROL
`
`FIGURE 2. DATA DISTRIBUTION SYSTEM
`
`The D/A converter outputs then drive actuators which
`directly control the various process parameters such as
`temperature, pressure, and flow. Thus the loop is closed on
`the process and the result is a complete automatic process
`control system under computer control.
`
`Quantizing Theory
`Introduction
`Analog-to-digital conversion in its basic conceptual form is a
`two-step process: quantizing and coding. Quantizing is the
`process of transforming a continuous analog signal into a set
`
`2
`
`

`
`Application Note 002
`
`window) in making a measurement and results in an
`amplitude uncertainty (or error) in the measurement if the
`signal is changing during this time.
`
`V(t)
`
`∆V
`
`∆V
`
`=
`
`dV t( )
`×
`-------------- TA
`dt
`
`TA
`
`TA = APERTURE TIME
`∆V = AMPLITUDE UNCERTAINTY
`
`FIGURE 4. APETURE TIME AND AMPLITUDE UNCERTAINTY
`
`As shown in Figure 4, the input signal to the A/D converter
`changes by ∆V during the aperture time TA in which the
`conversion is performed. The error can be considered an
`amplitude error or a time error, the two are related as follows:
`dV t( )
`--------------
`dt
`
`∆V TA
`=
`
`(EQ. 3)
`
`where dV(t)/dt is the rate of change with time of the input
`signal.
`It should be noted that ∆V represents the maximum error
`due to signal change, since the actual error depends on how
`the conversion is done. At some point in time within TA, the
`signal amplitude corresponds exactly with the output code
`word produced.
`
`For the specific case of a sinusoidal input signal, the
`maximum rate of change occurs at the zero crossing of the
`waveform, and the amplitude error is
`
`)t
`
`=
`
`0
`
`=
`
`TAAω
`
`(EQ. 4)
`
`dd
`
`----- Asinωt(
`
`
`t
`
`∆V TA
`=
`
`Quantizer Resolution and Error
`At any part of the input range of the quantizer, there is a
`small range of analog values within which the same output
`code word is produced. This small range is the voltage
`difference between any two adjacent decision points and is
`known as the analog quantization size, or quantum, Q. In
`Figure 3, the quantum is 1.25V and is found in general by
`dividing the full scale analog range by the number of output
`states. Thus
`
`Q
`
`=
`
`FSR
`------------
`2n
`
`(EQ. 1)
`
`where FSR is the full scale range, or 10V in this case. Q is
`the smallest analog difference which can be resolved, or
`distinguished, by the quantizer. In the case of a 12-bit
`quantizer, the quantum is much smaller and is found to be
`
`Q
`
`=
`
`FSR
`------------
`2n
`
`=
`
`10V
`-------------
`4096
`
`=
`
`2.44mV
`
`(EQ. 2)
`
`If the quantizer input is moved through its entire range of
`analog values and the difference between output and input is
`taken, a sawtooth error function results, as shown in Figure
`3. This function is called the quantizing error and is the
`irreducible error which results from the quantizing process. It
`can be reduced only by increasing the number of output
`states (or the resolution) of the quantizer, thereby making
`the quantization finer.
`
`For a given analog input value to the quantizer, the output
`error will vary anywhere from 0 to ±Q/2; the error is zero only
`at analog values corresponding to the code center points.
`This error is also frequently called quantization uncertainty
`or quantization noise.
`
`The quantizer output can be thought of as the analog input
`with quantization noise added to it. The noise has a peak-to-
`peak value of Q but, as with other types of noise, the
`average value is zero. Its RMS value, however, is useful in
`analysis and can be computed from the triangular
`waveshape to be Q/2√3.
`
`Sampling Theory
`Introduction
`An analog-to-digital converter requires a small, but
`significant, amount of time to perform the quantizing and
`coding operations. The time required to make the conversion
`depends on several factors; the converter resolution, the
`conversion technique, and the speed of the components
`employed in the converter. The conversion speed required
`for a particular application depends on the time variation of
`the signal to be converted and on the accuracy desired.
`
`Aperture Time
`Conversion time is frequently referred to as aperture time. In
`general, aperture time refers to the time uncertainty (or time
`
`3
`
`The resultant error as a fraction of the peak to peak full scale
`value is
`∆V
`--------
`2A
`
`(EQ. 5)
`
`ε
`
`=
`
`=
`
`πfTA
`
`From this result the aperture time required to digitize a 1kHz
`signal to 10 bits resolution can be found. The resolution
`required is one part in 210 or 0.001.
`
`(EQ. 6)
`
`320 10 9–
`×
`
`=
`
`0.001
`---------------------------
`3.14 103
`×
`
`=
`
`επ
`
`-----
`f
`
`TA
`
`=
`
`The result is a required aperture time of just 320ns!
`
`One should appreciate the fact that 1kHz is not a particularly
`fast signal, yet it is difficult to find a 10-bit A/D converter to
`perform this conversion at any price! Fortunately, there is a
`relatively simple and inexpensive way around this dilemma
`by using a sample-hold circuit.
`
`

`
`Application Note 002
`
`4 BITS
`6 BITS
`8 BITS
`10 BITS
`12 BITS
`13 BITS
`14 BITS
`15 BITS
`16 BITS
`
`(A)
`SIGNAL
`
`(B)
`SAMPLING
`PULSES
`
`(C)
`SAMPLED
`SIGNAL
`
`(D)
`SAMPLED AND
`HELD SIGNAL
`
`1ms
`
`100µs
`
`10µs
`
`1µs
`
`APERTURE TIME (TA)
`
`100ns
`
`10ns
`
`1ns
`
`1
`
`10
`
`10K
`1K
`100
`SINUSOIDAL FREQUENCY (Hz)
`
`100K
`
`FIGURE 5. GRAPH FOR APERTURE ERROR FOR
`SINUSOIDAL SIGNALS
`
`Sample-Holds and Aperture Error
`A sample-hold circuit samples the signal voltage and then
`stores it on a capacitor for the time required to perform the
`A/D conversion. The aperture time of the A/D converter is
`therefore greatly reduced by the much shorter aperture time
`of the sample-hold circuit. In turn, the aperture time of the
`sample-hold is a function of its bandwidth and switching
`time.
`
`Figure 5 is a useful graph of Equation 5. It gives the aperture
`time required for converting sinusoidal signals to a maximum
`error less than one part in 2n where n is the resolution of the
`converter in bits. The peak to peak value of the sinusoid is
`assumed to be the full scale range of the A/D converter. The
`graph is most useful in selecting a sample-hold by aperture
`time or an A/D converter by conversion time.
`
`Sampled-Data Systems and the Sampling Theo-
`rem
`In data acquisition and distribution systems, and other
`sampled-data systems, analog signals are sampled on a
`periodic basis as illustrated in Figure 6. The train of sampling
`pulses in Figure 6B represents a fast-acting switch which
`connects to the analog signal for a very short time and then
`disconnects for the remainder of the sampling period.
`
`4
`
`FIGURE 6. SIGNAL SAMPLING
`
`The result of the fast-acting sampler is identical with
`multiplying the analog signal by a train of sampling pulses of
`unity amplitude, giving the modulated pulse train of Figure
`6C. The amplitude of the original signal is preserved in the
`modulation envelope of the pulses. If the switch type
`sampler is replaced by a switch and capacitor (a sample-
`hold circuit), then the amplitude of each sample is stored
`between samples and a reasonable reconstruction of the
`original analog signal results, as shown in Figure 6D.
`
`The purpose of sampling is the efficient use of data
`processing equipment and data transmission facilities. A
`single data transmission link, for example, can be used to
`transmit many different analog channels on a sampled basis,
`where-as it would be uneconomical to devote a complete
`transmission link to the continuous transmission of a single
`signal.
`
`Likewise, a data acquisition and distribution system is used
`to measure and control the many parameters of a process
`control system by sampling the parameters and updating the
`control inputs periodically. In data conversion systems it is
`common to use a single, expensive A/D converter of high
`speed and precision and then multiplex a number of analog
`inputs into it.
`
`An important fundamental question to answer about sample-
`data systems is this: “How often must I sample an analog
`signal in order not to lose information from it?” It is obvious
`that all useful information can be extracted if a slowly varying
`signal is sampled at a rate such that little or no change takes
`place between samples. Equally obvious is the fact that
`information is being lost if there is a significant change in
`signal amplitude between samples.
`
`The answer to the question is contained in the well known
`Sampling Theorem which may be stated as follows: If a
`continuous bandwidth-limited signal contains no frequency
`components higher than fC, then the original signal can be
`recovered without distortion if it is sampled at a rate of at
`least 2 fC samples per second.
`
`

`
`Application Note 002
`
`Frequency Folding and Aliasing
`The Sampling Theorem can be demonstrated by the
`frequency spectra illustrated in Figure 7. Figure 7A shows
`the frequency spectrum of a continuous bandwidth-limited
`analog signal with frequency components out to fC. When
`this signal is sampled at a rate fS, the modulation process
`shifts the original spectrum out of fS, 2fS, 3fS, etc. in addition
`to the one at the origin. A portion of this resultant spectrum
`is shown in Figure 7B.
`
`frequency can be significantly different from the original
`frequency. From the figure it is easy to see that if the
`sinusoid is sampled at least twice per cycle, as required by
`the Sampling Theorem, the original frequency is preserved.
`
`SIGNAL
`
`V
`
`0
`
`V
`
`(A)
`CONTINUOUS
`SIGNAL
`SPECTRUM
`
`(B)
`SAMPLED
`SIGNAL
`SPECTRUM
`
`fC
`
`f
`
`FREQUENCY FOLDING
`
`0
`
`fS - fC
`
`fC
`fS/2
`FIGURE 7. FREQUENCY SPECTRA DEMONSTRATING THE
`SAMPLING THEOREM
`
`fS
`
`fS + fC
`
`SAMPLING
`PULSES
`
`ALIAS
`FREQUENCY
`
`FIGURE 8. ALIAS FREQUENCY CAUSED BY INADEQUATE
`SAMPLING RATE
`
`Coding for Data Converters
`Natural Binary Code
`A/D and D/A converters interface with digital systems by
`means of an appropriate digital code. While there are many
`possible codes to select, a few standard ones are almost
`exclusively used with data converters. The most popular
`code is natural binary, or straight binary, which is used in its
`fractional form to represent a number
`a12 1–
`a22 2–
`a32 3– … an2 n–
`+
`+
`
`N
`
`=
`
`+
`
`+
`
`(EQ. 7)
`
`If the sampling frequency fS is not high enough, part of the
`spectrum centered about fS will fold over into the original
`signal spectrum. This undesirable effect is called frequency
`folding. In the process of recovering the original signal, the
`folded part of the spectrum causes distortion in the
`recovered signal which cannot be eliminated by filtering the
`recovered signal.
`
`From the figure, if the sampling rate is increased such that
`fS - fC > fC, then the two spectra are separated and the
`original signal can be recovered without distortion. This
`demonstrates the result of the Sampling Theorem that fS >
`2fC. Frequency folding can be eliminated in two ways: first
`by using a high enough sampling rate, and second by
`filtering the signal before sampling to limit its bandwidth to
`fS/2.
`One must appreciate the fact that in practice there is always
`some frequency folding present due to high frequency signal
`components, noise and non-ideal pre-sample filtering. The
`effect must be reduced to negligible amounts for the
`particular application by using a sufficiently high sampling
`rate. The required rate, in fact, may be much higher than the
`minimum indicated by the Sampling Theorem.
`
`The effect of an inadequate sampling rate on a sinusoid is
`illustrated in Figure 8; an alias frequency in the recovered
`signal results. In this case, sampling at a rate slightly less
`than twice per cycle gives the low frequency sinusoid shown
`by the dotted line in the recovered signal. This alias
`
`5
`
`where each coefficient “a” assumes a value of zero or one. N
`has a value between zero and one.
`
`A binary fraction is normally written as 0.110101, but with
`data converter codes the decimal point is omitted and the
`code word is written 110101. This code word represents a
`fraction of the full scale value of the converter and has no
`other numerical significance.
`
`The binary code word 110101 therefore represents the
`decimal fraction (1x0.5)+(1x0.25)+(1x0.125)+(1x0.0625)+
`(0x0.03125)+(1x0.015625)=0.828125 or 82.8125% of full
`scale for the converter. If full scale is +10V, then the code
`word represents +8.28125V. The natural binary code
`belongs to a class of codes known as positive weighted
`codes since each coefficient has a specific weight, none of
`which is negative.
`
`The leftmost bit has the most weight, 0.5 of full scale, and is
`called the most significant bit, or MSB; the rightmost bit has
`the least weight, 2-n of full scale, and is therefore called the
`least significant bit, or LSB. The bits in a code word are
`numbered from left to right from 1 to n.
`
`The LSB has the same analog equivalent value as Q
`discussed previously, namely
`
`LSB (Analog Value)
`
`=
`
`FSR
`------------
`2n
`
`(EQ. 8)
`
`

`
`Application Note 002
`
`Table 1 is a useful summary of the resolution, number of
`states, LSB weights, and dynamic range for data converters
`from one to twenty bits resolution.
`
`other words, the maximum analog value of the converter,
`corresponding to all one’s in the code, never quite reaches
`the point defined as analog full scale.
`
`TABLE 1. RESOLUTION NUMBER OF STATES, LSB WEIGHT,
`AND DYNAMIC RANGE FOR DATA CONVERTERS
`
`RESOLU-
`TION
`BITS (n)
`
`NUMBER
`OF
`STATES
`(2n)
`
`LSB WEIGHT
`(2-n)
`
`DYNAMIC
`RANGE
`(dB)
`
`0
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`1 1
`
`2 0.5
`
`4 0.25
`
`8 0.125
`
`16 0.0625
`
`32 0.03125
`
`64 0.015625
`
`128 0.0078125
`
`256 0.00390625
`
`512 0.001953125
`
`1024 0.0009765625
`
`2048 0.00048828125
`
`4096 0.000244140625
`
`0
`
`6
`
`12
`
`18.1
`
`24.1
`
`30.1
`
`36.1
`
`42.1
`
`48.2
`
`54.2
`
`60.2
`
`66.2
`
`72.2
`
`Other Binary Codes
`Several other binary codes are used with A/D and D/A
`converters in addition to straight binary. These codes are
`offset binary, two’s complement, binary coded decimal
`(BCD), and their complemented versions. Each code has a
`specific advantage in certain applications. BCD coding for
`example is used where digital displays must be interfaced
`such as in digital panel meters and digital multimeters. Two’s
`complement coding is used for computer arithmetic logic
`operations, and offset binary coding is used with bipolar
`analog measurements.
`
`Not only are the digital codes standardized with data
`converters, but so are the analog voltage ranges. Most
`converters use unipolar voltage ranges of 0 to +5V and 0 to
`+10V although some devices use the negative ranges 0 to
`-5V and 0 to -10V. The standard bipolar voltage ranges are
`±2.5V, ±5V and ±10V. Many converters today are pin-
`programmable between these various ranges.
`
`TABLE 2. BINARY CODING FOR 8-BIT UNIPOLAR CONVERTERS
`
`STRAIGHT
`BINARY
`
`COMPLE-
`MENTARY
`BINARY
`
`1111 1111
`
`0000 0000
`
`+ 10V fS
`+9.961
`
`FRACTION
`OF fS
`+fS-1 LSB
`+3/4fS
`+1/2fS
`+1/4fS
`+1/8fS
`+1 LSB
`
`0
`
`+7.500
`
`+5.000
`
`+2.500
`
`+1.250
`
`+0.039
`
`0.000
`
`1100 0000
`
`0011 1111
`
`1000 0000
`
`0111 1111
`
`0100 0000
`
`1011 1111
`
`0010 0000
`
`1101 1111
`
`0000 0001
`
`1111 1110
`
`0000 0000
`
`1111 1111
`
`Table 2 shows straight binary and complementary binary
`codes for unipolar 8-bit converter with a 0 to +10V analog fS
`range. The maximum analog value of the converter is
`+9.961V, or one LSB less than +10V. Note that the LSB size
`is 0.039V as shown near the bottom of the table. The
`complementary binary coding used in some converters is
`simply the logic complement of straight binary.
`
`When A/D and D/A converters are used in bipolar operation,
`the analog range is offset by half scale, or by the MSB value.
`The result is an analog shift of the converter transfer function
`as shown in Figure 9. Notice for this 3-bit A/D converter
`transfer function that the code 000 corresponds with -5V, 100
`with 0V, and 111 with +3.75V. Since the output coding is the
`same as before the analog shift, it is now appropriately
`called offset binary coding.
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`8192 0.0001220703125
`
`16384 0.00006103515625
`
`32768 0.000030517578125
`
`65536 0.0000152587890625
`
`131072 0.00000762939453125
`
`262144 0.000003814697265625
`
`78.3
`
`84.3
`
`90.3
`
`96.3
`
`102.3
`
`108.4
`
`524288 0.0000019073486328125
`
`114.4
`
`1048576 0.00000095367431640625 120.4
`
`The dynamic range of a data converter in dB is found as
`follows:
`DR dB(
`
`log
`2
`6.02n
`
`(EQ. 9)
`
`)
`
`2n
`log
`20n
`20
`=
`(
`)
`20n 0.301
`=
`
`=
`=
`
`where DR is a dynamic range, n is the number of bits, and 2n
`the number of states of the converter. Since 6.02dB
`corresponds to a factor of two, it is simply necessary to
`multiply the resolution of a converter in bits by 6.02. A 12-bit
`converter, for example, has a dynamic range of 72.2dB.
`
`An important point to notice is that the maximum value of the
`digital code, namely all 1’s does not correspond with analog
`full scale, but rather with one LSB less than full scale, or fS
`(1-2-n). Therefore a 12-bit converter with a 0 to 10V analog
`range has a maximum code of 1111 1111 1111 and a
`maximum analog value of +10V (1-2-12) = +9.99756V. In
`
`6
`
`

`
`Application Note 002
`
`OFFSET BINARY
`
`COMP OFF BINARY
`
`TWO’S
`COMPLEMENT
`
`SIGN-MAG BINARY
`
`FRACTION OF fS
`+fS-1 LSB
`+1/4fS
`+1/2fS
`+3/4fS
`0
`
`±5V fS
`+4.9976
`
`+3.7500
`
`+2.5000
`
`+1.2500
`
`0.0000
`
`-1.2500
`
`-2.5000
`
`-3.7500
`
`-4.9976
`
`-5.0000
`
`-1/4fS
`-1/2fS
`-3/4fS
`-fS+1 LSB
`-fS
`NOTE: Sign Magnitude Binary has two code words for zero as shown here.
`
`1111 1111
`
`1110 0000
`
`1100 0000
`
`1010 0000
`
`1000 0000
`
`0110 0000
`
`0100 0000
`
`0010 0000
`
`0000 0001
`
`0000 0000
`
`0000 0000
`
`0001 1111
`
`0011 1111
`
`0101 1111
`
`0111 1111
`
`1001 1111
`
`1011 1111
`
`1101 1111
`
`1111 1110
`
`1111 1111
`
`0111 1111
`
`0110 0000
`
`0100 0000
`
`0010 0000
`
`0000 0000
`
`1110 0000
`
`1100 0000
`
`1010 0000
`
`1000 0001
`
`1000 0000
`
`1111 1111
`
`1110 0000
`
`1100 0000
`
`1010 0000
`
`1000 0000
`
`0010 0000
`
`0100 0000
`
`0110 0000
`
`0111 1111
`
`--
`
`complementing of the MSB. In bipolar coding, the MSB
`becomes the sign bit.
`
`The sign-magnitude binary code, infrequently used, has
`identical code words for equal magnitude analog values
`except that the sign bit is different. As shown in Table 3 this
`code has two possible code words for zero: 1000 0000 or
`0000 0000. The two are usually distinguished as 0+ and 0-,
`respectively. Because of this characteristic, the code has
`maximum analog values of ± (fS-1 LSB) and reaches neither
`analog +fS or -fS.
`BCD Codes
`Table 4 shows BCD and complementary BCD coding for a 3
`decimal digit data converter. These are the codes used with
`integrating type A/D converters employed in digital panel
`meters, digital multimeters, and other decimal display
`applications. Here four bits are used to represent each
`decimal digit. BCD is a positive weighted code but is
`relatively inefficient since in each group of four bits, only 10
`out of a possible 16 states are utilized.
`
`TABLE 4. BCD AND COMPLEMENTARY BCD CODING
`
`FRACTION
`OF fS
`+fS-1 LSB
`+3/4fS
`+1/2fS
`+1/4fS
`+1/8fS
`+1 LSB
`
`+10V
`fS
`+9.99
`
`+7.50
`
`+5.00
`
`+2.50
`
`+1.25
`
`+0.01
`
`BINARY CODED
`DECIMAL
`
`COMPLEMENTARY
`BCD
`
`1001 1001 1001
`
`0110 0110 0110
`
`0111 0101 0000
`
`1000 1010 1111
`
`0101 0000 0000
`
`1010 1111 1111
`
`0010 0101 0000
`
`1101 1010 1111
`
`0001 0010 0101
`
`1110 1101 1010
`
`0000 0000 0001
`
`1111 1111 1110
`
`0
`
`0.00
`
`0000 0000 0000
`
`1111 1111 1111
`
`The LSB analog value (or quantum, Q) for BCD is
`
`LSB (Analog Value)
`
`=
`
`Q
`
`=
`
`FSR
`------------
`10d
`
`(EQ. 10)
`
`111
`
`110
`
`101
`
`OUTPUT CODE
`
`100
`
`Q
`
`011
`
`010
`
`001
`000
`
`-5.00
`
`-3.75
`
`-2.50
`
`0
`+1.25
`-1.25
`INPUT VOLTAGE
`
`+2.50 +3.75 +5.00
`
`FIGURE 9. TRANSFER FUNCTION FOR BIPOLAR 3-BIT A/D
`CONVERTER
`
`Table 3 shows the offset binary code together with
`complementary offset binary, two’s complement, and sign-
`magnitude binary codes. These are the most popular codes
`employed in bipolar data converters.
`
`TABLE 3. POPULAR BIPOLAR CODES USED WITH DATA
`CONVERTERS
`
`0+
`
`0
`
`SIGN-MAG BINARY
`
`1000 0000 0000
`
`0000 0000 0000
`
`The two’s complement code has the characteristic that the
`sum of the positive and negative codes for the same analog
`magnitude always produces all zero’s and a carry. This
`characteristic makes the two’s complement code useful in
`arithmetic computations. Notice that the only difference
`between two’s complement and offset binary is the
`
`7
`
`

`
`Application Note 002
`
`where FSR is the full scale range and d is the number of
`decimal digits. For example if there are 3 digits and the full
`scale range is 10V, the LSB value is
`
`LSB (Analog Value)
`
`=
`
`10V
`-----------
`103
`
`=
`
`0.01V 10mV
`=
`
`(EQ. 11)
`
`BCD coding is frequently used with an additional overrange
`bit which has a weight equal to full scale and produces a
`100% increase in range for the A/D converter. Thus for a
`converter with a decimal full scale of 999, an overrange bit
`provides a new full scale of 1999, twice that of the previous
`one. In this case, the maximum output code is 1 1001 1001
`1001. The additional range is commonly referred to as 1/2
`digit, and the resolution of the A/D converter in this case is
`31/2 digits.
`Likewise, if this range is again expanded by 100%, a new full
`scale of 3999 results and is called 33/4 digits resolution.
`Here two overrange bits have been added and the full scale
`output code is 11 1001 1001 1001. When BCD coding is
`used for bipolar measurements another bit, a sign bit, is
`added to the code and result is sign-magnitude BCD coding.
`
`Amplifiers and Filters
`Operational and Instrumentation Amplifiers
`The front end of a data acquisition system extracts the desired
`analog signal from a physical parameter by means of a
`transducer and then amplifies and filters it. An amplifier and
`filter are critical components in this initial signal processing.
`
`The amplifier must perform one or more of the following
`functions: boost the signal amplitude, buffer the signal,
`convert a signal current into a voltage, or extract a
`differential signal from common mode noise.
`
`To accomplish these functions requires a variety of different
`amplifier types. The most popular type of amplifier is an
`operational amplifier which is a general purpose gain block
`with differential inputs. The op amp may be connected in
`many different closed loop configurations, of which a few are
`shown in Figure 10. The gain and bandwidth of the circuits
`shown depend on the external resistors connected around
`the amplifier. An operational amplifier is a good choice in
`general where a single-ended signal is to be amplified,
`buffered, or converted from current to voltage.
`
`8
`
`I
`
`E1
`
`R
`
`+-
`
`E = -IR
`
`CURRENT TO VOLTAGE
`CONVERSION
`
`R1
`
`E1
`
`R2
`
`+-
`
`R2–
`-----------E1
`R1
`INVERTING VOLTAGE GAIN
`
`=
`
`E2
`
`+-
`
`R2
`
`=
`
`E2
`
`
`
`
`
`1
`
`+
`
`R2
`
`
`-------
`R1
`
`
`E1
`
`R1
`
`NON-INVERTING VOLTAGE GAIN
`
`E
`
`+-
`
`E2 = E1
`UNITY GAIN BUFFER
`
`FIGURE 10. OPERATIONAL AMPLIFIER CONFIGURATIONS
`
`+VS
`
`RG
`
`R0
`
`+-
`
`RO
`
`G
`
`=
`
`E0
`--------
`∆E
`
`=
`
`2R0
`-----------
`RG
`
`E0
`
`I1
`
`I1
`
`∆E
`
`I1
`
`I1
`
`-VS
`FIGURE 11. SIMPLIFIED INSTRUMENTATION AMPLIFIER
`CIRCUIT
`
`In the case of differential signal processing, the
`instrumentation amplifier is a better choice since it maintains
`high impedance at both of its differential inputs and the gain
`is set by a resistor located elsewhere in the amplifier circuit.
`One type of instrumentation amplifier circuit is shown in
`Figure 11. Notice that no gain-setting resistors are
`connected to either of the input terminals. Instrumentation
`amplifiers have the following important characteristics.
`
`1. High impedance differential inputs
`2. Low input offset voltage drift
`3. Low input bias currents
`4. Gain easily set by means of one or two external resistors
`5. High common-mode rejection ratio
`
`Common Mode Rejection
`Common-mode rejection ratio is an important parameter of
`differential amplifiers. An ideal differential input amplifier
`responds only to the voltage difference between its input
`terminals and does not respond at all to any voltage that is
`common to both input terminals (common-mode voltage). In
`nonideal amplifiers, however, the common-mode input signal
`
`

`
`Application Note 002
`
`-3dB
`
`4-POLE
`BESSEL
`
`4-POLE
`BUTTERWORTH
`
`4-POLE
`CHEBYCHEV
`
`0.2
`
`0.3 0.4 0.5 0.6 0.8 1
`NORMALIZED FREQUENCY
`
`2
`
`3
`
`4
`
`5
`
`0
`
`5
`
`10
`
`15
`
`20
`
`ATTENUATION (dB)
`
`25
`0.1
`
`FIGURE 12. SOME PRACTICAL LOW PASS FILTER
`CHARACTERISTICS
`
`No filter does a perfect job of eliminating noise or other
`undesirable frequency components, and therefore the choice
`of a filter is always a compromise. Ideal filters, frequently
`used an analysis examples, have flat passband response
`with infinite attenuation at the cutoff frequency, but are
`mathematical filters only and not physically realizable.
`
`In practice, the systems engineer has a choice of cutoff
`frequency and attenuation rate. The attenuation rate and
`resultant phase response depend on the particular filter
`characteristic and the number of poles in the filter function.
`Some of the more popular filter characteristics include
`Butterworth, Chebychev, Bessel, and elliptic. In making this
`choice, the effect of overshoot and nonuniform phase delay
`must be carefully considered. Figure 12 illustrates some
`practical low pass filter response characteristics.
`
`Passive RLC filters are seldom used in signal proces