United States Patent
`Birkner et al.
`
`[19]
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,727,512
`Feb. 23, 1988
`
`[54]
`
`INTERFACE ADAPTOR EMULATING
`MAGNETIC TAPE DRIVE
`
`Primary E.xam:'ner—Raulfe B. Zache
`Assilrranl Examr'r:er—-Michael J. Ure
`
`[75]
`
`[56]
`
`Inventors‘ David A Birlmer Wellesley- Mark
`A. Sankey, Lexington, both or Mass.
`[73] Assignee: Computer Design & Applications,
`Inc., Waltham, Mess.
`mo
`rzu
`Di’-1-5 5. 1934
`[23] Filed!
`[SI]
`Int. Cl.‘ ................................................ GIMF 3/I14
`[53]
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`____________________________ __ 354/gm
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`354/200_ 9“), 200 MS pi]e_
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`References Cm":
`US. PATENT DOCUMENTS
`3.290.554 12/195:. Rcttig at al.
`4,t'.lJ4.2?7
`I/I93‘? Garvil
`4,5 I 1,963 4/ I935 Kantner ..............
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`3”“
`A E RACT
`[57]
`A magnetic tape drive emulator provides interface corn-
`
`acquisition processing system. The emulator receives
`sigmls ma‘ are nonmlly appned ‘° 3 “"“3“°‘i" mp‘:
`drive system and converts them into datasignals which
`are formatted for general agjfss by the image acquisi-
`ticm processing system. In
`moo, the magnetic tape
`drive emulator converts signals generated by the pc-
`ripheral processing system into data signals which are
`formatted for access by the computer system through
`""3 5"“'d‘"‘‘ "P9 d'i"'° i“‘°1'f3°=-
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`4 China, 3 Drawing Figures
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`MAG TAPE BUS
`\\
`
`DIGITAL DATA PATH
`T0/FROM PROCESSING
`SYSTEM II
`
`I4
`
`PERIPH ERAL BUS
`
`(9 SOMEHMES PHYSICALLY LOCATED on TAPE "DRIVE". SOMETIMES PART or
`TAPE “COUPLER”
`
`@ MA‘! as MORE THAN om-: "DRIVE" omsv cnamso
`
`@ mousrm STANDARD EIUS
`
`
`
`Apple 1009
`
`Apple 1009
`U.S. Pat. 9,189,437
`
`

`
`U.S. Patent
`
`Feb. 23, 1988
`
`Sheet 1 or 2
`
`4,727,512
`
`24
`
`READ DATA
`
`23
`
`30
`
`INDUSTRY STANDARD
`MAG TAPE Dus
`
`BUFFER
`WRITE DATA MEMORY
`
`DATA
`INTERFACE
`
`D|G'TN- DATA
`PATH TWFROM
`PROCESSING
`SYSTEM II
`
`LOGIC
`
`2
`
`INDUSTRY STANDARD
`MAG TAPE BUS \ @
`
`MAG TAPE
`EMULATOR
`
`DTGITAL DATA PATH
`TO/FROM PROCESSING
`SYSTEM I I
`
`EXISTING
`COMPUTER
`
`/4
`
`PERIPHERAL BUS
`
`(D SOMETIMES PHYSICALLY LOCATED ON TAPE "DRIVE". SOMETIMES PART OF
`TAPE "COUPLER"
`
`@ MAY BE MORE THAN ONE "DRTVE" DAns~r DHAINED
`
`@) INDUSTRY STANDARD BUS
`
`FIG I
`
`

`
`U.S. Patent
`
`Feb. 23, 1988
`
`4|MS
`
`2.m1..-
`
`4,727,512
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`]
`
`4,727,512
`
`INTERFACE ADAPTOR EMULATING MAGNETIC
`TAPE DRIVE
`
`BACKGROUND OF THE INVENTION
`l. Field of the Invention:
`The present
`invention relates to interface devices
`and, more particularly,
`is directed toward a device
`which provides modality interface compatibility be-
`tween a computer system having an industry standard
`magnetic tape drive interface and peripheral
`image
`acquisition processing system.
`2. Description of the Prior Art:
`Generally. manufacturers of computer systems pro-
`vide interface units which are specifically designed to
`operate with their system. However, virtually every
`digital
`imaging modality and film digitizer available
`today has a vendor supplied magnetic tape drive as an
`existing peripheral unit, or as an available option, and
`standard software to transfer images and patient data to
`and from the tape drive. Although there is an industry
`standard tape drive interface, there is no industry stan-
`dard interface through which data is made available for
`general access by peripheral processing systems.
`SUMMARY OF THE INVENTION
`
`It is an object of the present invention to provide a
`universal
`interface device which converts magnetic
`tape drive signals into suitably formatted data that is
`available for general access by peripheral processing
`systems using existing industry standard interfaces.
`It is a further object of the present invention to pro-
`vide a magnetic tape drive emulator which intercon-
`nects with an industry standard magnetic tape drive
`interface bus of a computer system and a host bus of a
`peripheral processing system for receiving and trans-
`mitting data signals. The emulator converts magnetic
`tape drive signals generated by the computer system
`and applied to the magnetic tape drive interface bus via
`the magnetic tape drive interface into data signals. The
`emulator formats the data signals in such a way that
`they are available for general access by the peripheral
`processing system. The emulator also converts signals
`generated by the processing system into data signals
`which are formatted for access by the computer system
`through the standard tape drive interface.
`The magnetic tape drive emulator includes a buffer
`memory, a data interface and control logic. Data signals
`are converted to the appropriate format and transfered
`between an industry standard magnetic tape interface
`bus which is accessible by the computer system and a
`host interface bus which is accessible by the processing
`system via the tape emulator. Transfer of digital data to
`and from a databus is provided by the data interface
`which is connected to the buffer memory. A control
`logic which receives signals from the magnetic tape bus
`and the data bus via the data interface controls the
`operation of the magnetic tape drive emulator.
`Other objects of the present invention will in part be
`obvious and will in part appear hereinafter.
`The invention accordingly comprises the device,
`together with its parts, elements and interrelationships,
`that are exemplified in the following disclosure.
`the
`scope of which will be indicated in the appended claims.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A fuller understanding of the nature and objects of
`the present invention will become apparent upon con-
`
`35
`
`60
`
`65
`
`2
`sideration of the following detailed description taken in
`connection with the accompanying drawings, wherein:
`FIG. 1 is a block and schematic diagram ofa com-
`puter system with a magnetic tape drive bus and a mag-
`netic tape drive emulator embodying the present inven-
`tion;
`FIG. 2 is simplified block and schematic diagram of
`the magnetic tape drive emulator of FIG. 1; and
`FIG. 3 is a detailed block and schematic diagram of
`the magnetic tape drive emulator of FIG. 1.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Referring now to the drawings. particularly FIG. 1,
`there is shown a block diagram of a computer system 10
`which is provided with a magnetic tape drive emulator
`24 embodying the present
`invention. Magnetic tape
`drive emulator 24 is an imaging interface between com-
`puter system Ill and a peripheral image processing sys-
`tem 11, for example. a picture archival and communica-
`tions system. Computer system 10 has a computer 12
`which is connected to a peripheral bus 14. A tape cou-
`pler 16 couples signals between the peripheral bus I4
`and a tape formatter 18.
`An industry standard magnetic tape drive interface
`bus 20 carries data between the tape formatter 18 and a
`tape drive system 22 which is a single magnetic tape
`drive unit or multiple magnetic tape drives which are
`daisy chained togehter. Manufacturers of computer
`systems provide a standard interface for interconnec-
`tion with magnetic tape transport devices. This is evi-
`denced by the fact that magnetic tape transport device
`manufactures, for example. Pertec Peripheral Equip-
`ment, Cipher, Kennedy, Fujitsu, CDC. IBM and Wang
`have conforming specifications with regard to signals
`passing between the tape formatter and the magnetic
`tape transport.
`The magnetic tape drive emulator 24 embodying the
`present
`invention is connected to the magnetic tape
`drive interface bus 2|]. The magnetic tape drive emula-
`tor 24 receives the magnetic tape data and controls
`signals at the magnetic tape drive interface bus 20 and
`converts them into digital data and control signals. The
`digital data and control signals are sent to a data bus 26
`where they are available for general access. That is,
`magnetic tape drive emulator 2-I emulates the operation
`of tape drive 22 and interface bus 20, and converts the
`tape drive signals into a suitable fonnat that is accessible
`by the peripheral image acquisition processing system
`11. Also. data and control signals generated by the
`peripheral processing system II are converted in the
`magnetic tape drive emulator 24 into data and control
`signals which are fonnatted for access by the computer
`system ll].
`As shown in FIG. 2, magnetic tape drive emulator
`drive 24 includes a buffer memory 28 to which write
`data from magnetic tape interface bus 20 is applied and
`from which read data is fed to the magnetic tape inter-
`face bus. Read and write data are fed between the buffer
`memory 28 and a data interface 30 which is connected
`to the data bus 26. Buffer memory 28 is provided to
`smooth the flow of data between the magnetic tape
`interface bus 20 and the data bus 26. A control logic 32,
`which receives signals from the magnetic tape interface
`bus 20 and the digital data bus 26 via data interface 30,
`controls the operation of magnetic tape drive emulator
`24.
`
`

`
`4-.727,5 I2
`
`3
`In the detailed schematic and block diagram of FIG.
`3, control signals are denoted by the open arrow heads
`and data signals are denoted by the closed arrow heads.
`Data and control signals from magnetic tape interface
`bus 20 are applied respectively to a write data register
`3-4 and a drive control register 36 via receivers and
`terminators 38. Control signals from drive control regis-
`ter 36 are fed to a test multiplexer 4-0 which receives
`input signals from the peripheral image processing sys-
`tem ll via. a host bus interface 42 and an arithmetic
`logic unit 44. Test multiplexer 40 output signals and a
`feedback signal from a control store unit 4-6 are applied
`to a micro sequencer 48, the output signals generated by
`the micro sequencer being fed to the control store unit
`4-6. Control signals generated by the control store unit
`4-6 are applied to the host bus interface 42. In addition.
`the control store unit 46 output control signals are fed to
`the arithmetic logic unit -14 as well as the units which
`receive data signals. Test multiplexer 40, micro se-
`quencer 48, control store unit 4-6 and arithmetic logic
`unit 44 define a processing unit.
`As previously indicated, write data signals from re-
`ceivers and terminators 38 are sent to the write data
`register 34. The write data signals are stored in a regis-
`ter file 49 and fed to the host bus interface 42 via a data
`buffer 50. The write data signals are converted in arith-
`metic logic unit 44 into a. predetenriined format which is
`suitable for access by the peripheral processing system
`11 via the host bus interface 42.
`Read signals from the peripheral processing system
`II are applied to magnetic tape drive emulator 21 via
`the host bus interface 42. The read signals are sent to a
`read data register 52 and a drive status register 54 via
`data buffer 50 and register tile 49. Read data register 52,
`in response to control signals from control store «It! and
`clock signals from a read clock generator 56 processes
`the received read data signals. The processed read data
`signals are encoded in a read data encoder 58 and ap-
`plied to the magnetic tape interface bus 20 via drivers
`60. The drive status register 54 controls the application
`of the encoded read data signals to the magnetic tape
`interface bus 20 as a function of the status of the signals
`on the bus.
`Since certain changes may be made in the foregoing
`disclosure without departing from the scope of the
`invention herein involved, it is intended that all matter
`contained in the above description and depicted in the
`accompanying drawings be construed in an illustrative
`and not a limiting sense.
`What is claimed is:
`I. A magnetic tape drive emulator for use with a
`computer system having industry standard tape drive
`interface and peripheral image processing system, said
`magnetic tape drive emulator comprising:
`(A) receivers and terminators for receiving data sig-
`nals and control signals present on an industry
`standard tape drive interface:
`(B) a write data register connected to said receivers
`and tenninators for receiving said data signals;
`(C) a drive control register connected to said receiv-
`ers and terminators for receiving said control sig-
`nals; and
`(D) a processing unit connected to said write data
`register and said drive control register for convert-
`ing said data signals into an image processing sys-
`tem signal format,
`wherein said processing unit includes:
`
`4
`(a) a test multiplexer connected to said drive control
`register for receiving signals at the output thereof;
`(b) a micro sequencer connected to said test multi-
`plexer for receiving signals at the Dutpttt thereof;
`(c) a control store connected to said micro sequencer,
`a feedback signal generated by said control store
`applied to said micro sequencer; and
`{d) an arithmetic logic unit connected to said control
`store and said test multiplexer, write data signals
`generated by said write data register being applied
`to said arithmetic logic unit, said write data signals
`converted in said arithmetic logic unit
`into an
`image processing system format.
`2. The magnetic tape drive emulator as claimed in
`claim 1 including-.
`(a) a register file and data buffer for receiving said
`image processing system format data signals;
`(b) said arithmetic logic unit also converting image
`processing system data signals and control signals
`into computer system fonnat;
`(c) a read data register for receiving said signals con-
`verted into said computer system format;
`(d) a read data encoder connected to said read data
`register for encoding data signals generated by said
`read data register; and
`(e) driver means connected to said read data encoder
`and for presenting said computer system format
`data signals to the standard tape drive interface.
`3. The magnetic tape drive emulator as claimed in
`claim 2 including a drive status register for receiving
`signals representing the status of the computer system
`and controlling said driver means as a function of said
`status.
`4. A magnetic tape drive emulator for use with a
`computer system having an industry standard tape drive
`interface and peripheral image processing system. said
`magnetic tape drive emulator comprising:
`(a) receivers and terminators for receiving data and
`control signals presented on an industry standard
`tape drive interface;
`(b) a write data register connected to said receivers
`and tenninators for receiving said data signals;
`(c) a drive control register connected to said receiv-
`ers and tenninators for receiving said control sig-
`nals;
`(cl) a test multiplexer connected to said drive control
`register for receiving signals at the output thereof;
`(e) a micro sequencer connected to said test multi-
`plexer for receiving signals at the output thereof;
`(0 a control store connected to said micro sequencer.
`tt feedback signal generated by said control store
`applied to said micro sequencer;
`(g) an arithmetic logic unit connected to said control
`store and said test multiplexer. write data signals
`generated by said write data register being applied
`to said arithmetic logic unit, said write data signals
`converted in said arithmetic logic unit
`into an
`image processing system format;
`fit) a register file and data buffer for receiving said
`image procmsing system format data signals:
`(i) said arithmetic logic unit also converting image
`processing system data signals and control signals
`into computer system fonrtat;
`(j) a read data register for receiving said signals con-
`verted into said computer system format;
`(It) a read clock generator connected to said read data
`register for controlling the operation thereof;
`
`

`
`4,727,512
`
`5
`(I) a read data encoder connected to said read data
`register and read clock generator for encoding data
`signals generated by said read data register;
`(in) a drive status register for receiving signals repre-
`senting the status of the computer system; and
`(11) driver means connected to said read data encoder
`
`6
`and said drive status register for presenting said
`computer system format data signals to the stan-
`dard tape drive interface when said computer sys-
`tem is available to receive said computer system
`format data signals.
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