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`Paper No.
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________________
`
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`CISCO SYSTEMS, INC.,
`Petitioner
`
`v.
`
`TQ DELTA LLC,
`Patent Owner
`
`_____________________
`
`
`Case IPR2016-01760
`Patent No. 9,094,268
`_____________________
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`PETITIONER’S REPLY
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`1
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`TABLE OF CONTENTS
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`I. 
`
`II. 
`
`Introduction ...................................................................................................... 5 
`
`Claim Construction .......................................................................................... 5 
`
`A. 
`
`B. 
`
`“maintaining synchronization with a second transceiver” .................... 5 
`
`the full power mode
`“parameters associated with
`operation” .............................................................................................. 7 
`
`III.  Bowie And Yamano Render The Claims Obvious ......................................... 8 
`
`A. 
`
`B. 
`
`Bowie and Yamano render obvious “a transmitter portion
`of the transceiver does not transmit data… and a receiver
`portion of the transceiver receives data….” .......................................... 8 
`
`The combination of Bowie and Yamano renders obvious
`“maintaining synchronization with a second transceiver
`during the low power mode.” .............................................................. 12 
`
`1. 
`
`2. 
`
`Yamano’s poll or other timing signal maintains
`synchronization between the transceivers during
`low power mode. ....................................................................... 12 
`
`Yamano’s poll or other timing signal is provided
`when the receiver is receiving data and in full
`power mode. .............................................................................. 14 
`
`C. 
`
`Bowie teaches “storing, during the low power mode, at
`least one parameter associated with a full power mode.” ................... 16 
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`IV.  A POSITA Would Have Been Motivated To Combine Bowie
`And Yamano .................................................................................................. 19 
`
`A. 
`
`B. 
`
`C. 
`
`The teachings of Bowie and Yamano are compatible. ........................ 19 
`
`The obviousness analysis is based on the prior art
`teachings—not hindsight. .................................................................... 21 
`
`Bowie and Yamano render obvious that the transmitter
`enters low power mode. ...................................................................... 22 
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`2
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`D. 
`
`E. 
`
`F. 
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Bowie in combination with Yamano renders obvious
`transmitting or receiving internet and video data while in
`low power mode. ................................................................................. 23 
`
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`
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`Dr. Kiaei’s deposition testimony is consistent with his
`declaration. .......................................................................................... 25 
`
`Yamano’s synchronization teachings are applicable to
`Bowie. .................................................................................................. 27 
`
`teachings do not render
`G.  Yamano’s synchronization
`Bowie inoperable for its intended use. ................................................ 28 
`
`V. 
`
`Patent Owner’s Attack on Dr. Kiaei Has No Merit ....................................... 30 
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`VI.  Conclusion ..................................................................................................... 31 
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`VII.  Certificate of Word Count ............................................................................. 32 
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`3
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`

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`
`
`Ex.1001
`Ex.1002
`Ex.1003
`Ex.1004
`Ex.1005
`Ex.1006
`Ex.1007
`Ex.1008
`Ex.1009
`Ex.1010
`Ex.1011
`Ex.1012
`Ex.1013
`Ex.1014
`Ex.1015
`Ex.1016
`Ex.1017
`Ex.1018
`Ex.1019
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`PETITIONER’S UPDATED EXHIBIT LIST
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`
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`August 23, 2017
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`U.S. Patent No. 8,611,404 to Greszczuk et al.
`Prosecution File History of U.S. Patent No. 8,611,404
`Declaration of Sayfe Kiaei under 37 C.F.R. § 1.68
`Curriculum Vitae of Dr. Sayfe Kiaei
`U.S. Patent No. 5,956,323 to Bowie
`U.S. Patent No. 6,075,814 to Yamano et al.
`Reserved
`Reserved
`U.S. Patent No. 6,084,881 to Fosmark et al.
`Declaration of Dr. Chrissan in IPR2016-01160
`Deposition Transcript of Dr. Chrissan
`Second Declaration of Sayfe Kiaei under 37 C.F.R. § 1.68
`Reserved
`Deposition Transcript of Dr. Chrissan in IPR2016-01006
`Reserved
`U.S. Patent No. 5,909,463
`Reserved
`Reserved
`District Court Claim Construction Order
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`4
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`

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`
`
`Introduction
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`I.
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Patent Owner attempts to distinguish the challenged claims of U.S.
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`9,094,268 (“the ‘268 patent”) on four bases: (1) that the combination of Bowie and
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`Yamano does not teach “a transmitter portion of the transceiver does not transmit
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`data during the low power mode and a receiver portion of the transceiver receives
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`data during the low power mode;” (2) that the combination of Bowie and Yamano
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`does not teach “maintaining synchronization with a second transceiver;” (3) that
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`the combination of Bowie and Yamano does not teach “parameters associated with
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`the full power mode operation;” and (4) that there is no motivation to combine
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`Bowie and Yamano. Each of these arguments is incorrect.
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`Patent Owner’s attempt to distinguish the prior art relies on improper claim
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`constructions and mischaracterizes the disclosures of both Bowie and Yamano.
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`For at least these reasons, Patent Owner’s arguments fail to refute the obviousness
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`of the challenged claims.
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`II. Claim Construction
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`A.
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`“maintaining synchronization with a second transceiver”
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`Patent Owner and its expert previously asserted that the term
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`“synchronization” refers to a “timing relationship between two transceivers.”
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`IPR2016-01160, Paper 16, p.24; Ex.1010, ¶55; see also Ex.1019, 4 (district court
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`construction of “synchronization signal”). Patent Owner now asserts that this term
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`5
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`means “maintaining a timing relationship between two transceivers by correcting
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`
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`errors or differences in the timing of the timing reference of the transceiver and the
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`timing reference of a second transceiver.” Response, 19-22. As evidenced by
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`Patent Owner’s change of position, this new proposal is not the broadest
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`reasonable construction.
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`The specification never discloses—much less requires— “correcting errors
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`or differences in [] timing” to maintain synchronization. In fact, Patent Owner’s
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`expert, Dr. Chrissan, admitted that he added this language to his earlier
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`construction in response to Dr. Kiaei’s analysis of the prior art. Ex.1011, 86:3-9
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`(“Q. So you added this extra language...in response to the prior art discussed by Dr.
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`Kiaei?” “A. In -- in part I added that clarification language.”) Dr. Chrissan further
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`explained that his new language is based on one embodiment in the ’268
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`specification that uses phase lock loops. Ex. 1011, 88:20-89:5.
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`While the ’268 specification discloses maintaining synchronization via
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`phase lock loops, it also states that “[o]ther forms of timing signal may, of
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`course, be used.” Ex.1001, 5:47-50. As Dr. Kiaei explains, “[s]ince the
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`specification encompasses other forms of timing signals for synchronization and
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`not just a pure tone, a POSITA would have understood that the claims are not
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`limited to correcting errors or differences in the timing references of the transmitter
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`and receiver.” Ex.1012, ¶5.
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`6
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Because claims should be construed in light of the specification—not the
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`
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`
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`prior art—the Board should adopt the broadest reasonable construction for
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`“maintaining synchronization with a second transceiver” to include “maintaining a
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`timing relationship between transceivers.” Ex.1012, ¶6.
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`B.
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`“parameters associated with the full power mode operation”
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`Patent Owner asserts that this term means a “parameter associated with the
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`transmission and/or reception of data during normal operation.” Response, 22-23.
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`This construction improperly excludes embodiments described in the ’268
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`specification.
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`The specification discloses that during full power mode, operational
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`parameters, such as signal-to-noise ratio (“SNR”), are measured. Ex.1001, 2:17-22.
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`From these measured parameters, transmission/reception parameters are derived.
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`Id., 2:23-24. Dr. Chrissan confirmed this relationship among these parameters. See
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`Ex.2005, ¶30 (“Signal to noise ratio (‘SNR’) is a function of, inter alia, loop
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`characteristics (e.g., line noise levels and line attenuation), and is used to
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`determine transmission parameters that are used for transmission of data.”). The
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`ANSI T1.413 standard confirms that parameters such as SNR and attenuation are
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`measured during full power mode (i.e., “at any other time following the execution
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`of initialization and training sequence of the ADSL system”) and used for
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`determining transmission parameters (e.g., bits per subchannel). Ex.2008, 82, 108.
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`7
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`According to Dr. Kiaei, “a POSITA would have understood that in the context of
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`
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`
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`the patents at issue, the parameters associated with full power mode not only
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`include parameters used for transmission and reception of data (e.g., bits, gains,
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`and equalizer values) but also include parameters from which the transmission and
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`reception parameters are derived (e.g., attenuation, SNR).” Ex.1012, ¶9.
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`Since Patent Owner limits the claim term to parameters associated with the
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`“transmission and/or reception of data,” rather than to parameters associated with
`
`full power mode operation (as the plain language requires), the proposed
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`interpretation is improperly narrow. Ex.1012, ¶¶8-9; See, e.g., Oatey Co. v. IPS
`
`Corp., 514 F.3d 1271, 1277 (Fed. Cir. Jan. 30, 2008) (“where claims can
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`reasonably [be] interpreted to include a specific embodiment, it is incorrect to
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`construe the claims to exclude that embodiment, absent probative evidence on the
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`contrary.”)
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`Therefore, Patent Owner’s construction should not be adopted and the plain
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`and ordinary meaning for this term should be applied. Ex.1012, ¶10.
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`III. Bowie And Yamano Render The Claims Obvious
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`A. Bowie and Yamano render obvious “a transmitter portion of the
`transceiver does not transmit data… and a receiver portion of the
`transceiver receives data….”
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`Patent Owner argues that Bowie and Yamano do not render obvious “a
`
`transceiver in a low power mode that receives data in the low power mode and
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`8
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`does not transmit data in the low power mode.” Response, 27. In support of this
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`
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`argument, Patent Owner asserts—incorrectly—that the Petition relied “on the
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`concept of inherency” to show a transmitter portion in low power mode. Id. 28.
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`As explained in the Petition and in Dr. Kiaei’s declaration, Bowie teaches
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`entering a low power mode since it discloses that “upon receipt of the shut-down
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`signal,” the ADSL unit “may then enter low-power mode by shutting off the now
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`unnecessary sections of signal processing 111, transmitting 112, and receiving 113
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`circuitry.” Ex.1005, 5:17-28; Ex.1003, pp.39-40; Petition, 27. Further, as
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`explained, a transmit portion of the transceiver does not transmit data since
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`Bowie’s low power mode provides for “shutting off the now unnecessary sections
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`of...transmitting...circuitry.” Ex.1005, 5:25-28; Ex.1003, p.40; Petition, 27.
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`Therefore Bowie teaches entering low power mode and shutting off unnecessary
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`portions of the transmitter circuitry. Ex.1012, ¶¶11-12.
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`The Petition also explained that Yamano’s transmitter enters low power
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`mode while in burst mode since “[t]he transmitter circuit only sends information
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`when there is meaningful packet data available to be sent” and otherwise “the
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`transmitter circuit does not transmit any signals on the communication channel.”
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`Ex.1006, 13:56-65; Ex.1003, p.43; Petition, 29-30. Yamano’s transmitter in burst
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`mode reduces processing power since it only transmits data when there is
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`meaningful data available. Ex.1012, ¶13. Indeed, Patent Owner’s expert, Dr.
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`9
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Chrissan, acknowledged that the “burst mode protocol described in
`
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`
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`Yamano…conserve[s] power.” Ex.2005, ¶116.
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`Further, as explained in the Petition, Yamano’s “echo canceler 309 can be
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`disabled when the local transmitter circuit is not transmitting.” Ex.1006, 16:2-5;
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`Ex.1003, p.43; Petition, 29-30. As Dr. Kiaei explains, “the echo canceler in
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`Yamano’s transceiver, which is interposed between both the transmitter and
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`receiver, is part of both circuits.” Ex.1012, ¶14; Ex.1006, FIGs. 1-4. This
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`understanding is also evidenced by numerous contemporaneous references. See
`
`e.g., Ex.1016, FIG. 1 (item 16).1 Accordingly, as Dr. Kiaei explains, “disabling of
`
`the echo canceller (which is part of both the receiver and transmitter circuit) further
`
`demonstrates what Yamano already teaches—that Yamano’s transmitter operates
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`in a reduced power mode when not transmitting.” Ex.1012, ¶14.
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`As additionally explained in the Petition, Yamano’s receiver is in full power
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`mode and receives data since Yamano teaches that “[u]pon detecting the easily
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`detected signal, non-idle detector 401 enables the full processing mode of
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`receiver circuit 400, thereby causing receiver circuit 400 to perform full
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`demodulation on the incoming RECEIVE signal.” Ex.1006, 14:20-29; Petition, 30-
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`1 Petitioner’s evidence introduced in this Reply is responsive to arguments raised
`by Patent Owner and therefore proper. See 37 C.F.R. § 42.23(b); Rules of Practice
`for Trials before the Patent Trial and Appeal Board, 77 Fed.Reg. 48,612, 48,620
`(Aug. 14, 2014); Genzyme Therapeutic Prods. Ltd. v BioMarin Pharm. Inc., 825
`F.3d 1360 (Fed. Cir. 2016).
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`10
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`31. Notably, Yamano enables full processing mode of only the receiver, not the
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`
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`transmitter. Id. Accordingly, even if Yamano’s transmitter is not transmitting and
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`thus is in low power mode, the receiver can receive signals in full power mode
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`(with the transmitter turned off, the transceiver as a whole is in a “low power
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`mode.”)
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`Lastly, as explained by Dr. Kiaei, “[a] POSITA would understand...that
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`Yamano improves upon Bowie’s shut-down of both the transmit and receive
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`circuitry by only disabling the circuit not in use (i.e., disabling the transmitter
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`when not transmitting and disabling the receiver when not receiving).” Ex.1003,
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`p.45; Petition, 31. This is consistent with Bowie’s desire of “shutting off the now
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`unnecessary sections.” Ex.1005, 5:17-28.
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`As shown by Dr. Kiaei, Yamano’s teachings allow Bowie’s CPE modem’s
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`transmitter to operate in low power mode while the receiver is receiving data in
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`full power mode.
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`Ex.1003, p.31.
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`11
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Therefore, the combination of Bowie and Yamano renders obvious a
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`
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`transceiver in low power mode, where the transmitter is in a low power mode and
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`not transmitting data and the receiver receiving data.
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`B.
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`The combination of Bowie and Yamano renders obvious
`“maintaining synchronization with a second transceiver during
`the low power mode.”
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`Patent Owner argues that “maintaining synchronization with a second
`
`transceiver during the low power mode” is not taught for a number of reasons.
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`These arguments lack merit.
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`1.
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`Yamano’s poll or other timing signal maintains
`synchronization between the transceivers during low power
`mode.
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`Patent Owner argues that “Yamano does not suggest...that the poll is used to
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`maintain a timing relationship between two transceivers by correcting errors or
`
`differences in the timing of the timing reference of the transceiver and the timing
`
`reference of a second transceiver.” Response, 31. This argument applies an
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`incorrect construction and mischaracterizes the prior art. Ex.1012, ¶15.
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`First, as discussed above, the term “maintaining synchronization with a
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`second transceiver” under the proper construction means “maintaining a timing
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`relationship between transceivers.” Yamano teaches the claim limitation because it
`
`uses a “poll or other timing signal” “to maintain synchronization of these time
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`intervals between receiver circuit 400 and the remote transmitter circuit.” Ex.1006,
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`12
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`

`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`15:29-32; Ex.1003, pp.48-49. Patent Owner does not dispute that Yamano’s poll or
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`
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`other timing signal is used to maintain a timing relationship. Therefore, under the
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`correct construction, it is undisputed that Yamano teaches this limitation. Ex.1012,
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`¶16.
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`Second, Yamano’s “poll or other timing signal” teaches this claim term even
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`under Patent Owner’s newly proposed meaning of “maintaining a timing
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`relationship between two transceivers by correcting errors or differences in the
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`timing of the timing reference of the transceiver and the timing reference of a
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`second transceiver.” Response, 19-22. Again, Yamano’s “poll or other timing
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`signal” is “used to maintain synchronization of these time intervals between
`
`receiver circuit 400 and the remote transmitter circuit.” Ex.1006, 15:29-32. As Dr.
`
`Kiaei explains, “a POSITA knew that a purpose of maintaining synchronization is
`
`to correct errors or differences that may periodically exist between transceivers.”
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`Ex.1012, ¶17; see also id., ¶¶18-19. Dr. Chrissan confirms this understanding.
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`Ex.1011, 67:8-10 (“If you don't correct for errors, you're not going to stay locked
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`and you're not going to be in synchronism.”)
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`Patent Owner also argues that “Yamano teaches that its transceiver
`
`establishes synchronization with the far end transceiver only at the start of the
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`reception of the data packet, and this occurs only when the transceiver is already in
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`full processing mode, i.e., full power mode.” Response, 32. Patent Owner then
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`13
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`

`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
`
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`concludes that “Yamano’s teaching that synchronization is established in full
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`
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`power mode necessarily teaches that synchronization is not maintained in the low
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`power mode.” Response, 33. This argument has no merit. Yamano’s “poll or other
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`timing signal” is taught to “maintain synchronization…between receiver
`
`circuit…[and] transmitter circuit” when operating in a reduced processing state.
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`Ex.1006, 15:29-32. The fact that Yamano also synchronizes in full power mode, in
`
`addition to synchronizing in low power mode, is of no moment and is consistent
`
`with how the ’268 patent synchronizes in both full power mode and low power
`
`mode. See Ex.1001, 5:5-20, 7:14-20.
`
`Therefore, even under Patent Owner’s construction, Yamano teaches
`
`“maintaining synchronization with a second transceiver.” Ex.1012, ¶17.
`
`2.
`
`Yamano’s poll or other timing signal is provided when the
`receiver is receiving data and in full power mode.
`
`Patent Owner also argues that “Yamano’s poll is neither sent nor received
`
`when the receiver is receiving data or in a full power mode.” Response, 33. This is
`
`wrong.
`
`The Petition explained that in the combination, Yamano’s “poll or other
`
`timing signal” is provided when the receiver is receiving data, but the transceiver is
`
`in a low power mode. To illustrate, take the example where the transmitter of the
`
`CPE modem (which corresponds to the transceiver in claim 1) is in low power
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`14
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`

`

`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
`
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`mode and its receiver is in full power mode and receiving data. See Ex.1003, p.31.
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`
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`
`
`In this example, when the CPE modem’s receiver (which is in full power
`
`mode) receives data, it will receive full power mode synchronization, as Patent
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`Owner acknowledges. See Response, 33 (“Yamano’s teaching that synchronization
`
`is established in the full power mode.”). Additionally, the CPE modem’s
`
`transmitter (which is in low power mode) will transmit a “poll or other timing
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`signal” to the COT modem’s receiver (which is also in low power mode) in order
`
`to maintain synchronization between the respective transmitting and receiving
`
`circuits. See Ex.1006, 15:64-16:5 (“the local transmitter circuit is not transmitting
`
`local transmit data” and “echo canceler 309 can be disabled when the local
`
`transmitter circuit is not transmitting packet information”); id. 15:29-32 (“poll or
`
`some other timing signal would be used to maintain synchronization of these time
`
`intervals between receiver circuit 400 and the remote transmitter circuit.”).
`
`Accordingly, when the CPE modem’s receiver is in full power mode and receiving
`
`data, its transmitter may be in low power mode and transmitting a “poll or other
`
`timing signal” to the COT modem’s receiver to maintain synchronization. The
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`CPE modem (“transceiver”) as a whole, is in a low power mode.
`
`Therefore, the combination of Bowie and Yamano renders obvious
`
`“maintaining synchronization with a second transceiver during the low power
`
`mode.”
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`15
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`

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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
`
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`C. Bowie teaches “storing, during the low power mode, at least one
`parameter associated with a full power mode.”
`
`
`
`Patent Owner argues that Bowie does not teach storing a “parameter
`
`associated with a/the full power mode,” because, allegedly, Bowie’s loop
`
`characteristics are not associated with transmitting data. Response, 35. This
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`argument fails for numerous reasons.
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`First, as discussed above, the term “parameter associated with the full power
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`mode” should be given its plain and ordinary meaning. Patent Owner
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`acknowledges that Bowie teaches storing loop characteristics, such as
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`“attenuation,” which “must be determined and exchanged” during “handshaking”
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`and used in full power mode operation. Response, 9 (citing Ex.1005, 4:64-5:3).
`
`Parameters such as attenuation and SNR are used in full power mode for various
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`operations. See Ex.2008, 82 (obtaining SNR and attenuation parameters “at any
`
`other time following the execution of initialization and training sequence of the
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`ADSL system.”). Thus, under the plain and ordinary meaning, it is undisputed that
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`Bowie teaches storing “parameters” (e.g., attenuation) “associated with the full
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`power mode operation.”
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`Second, Bowie teaches this term even under Patent Owner’s construction of
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`a “parameter associated with the transmission and/or reception of data during
`
`normal operation.” Response, 23. Patent Owner argues that Bowie’s “loop
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`16
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
`
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`characteristics” “are ‘associated’ with physical attributes of the loop [and]...are
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`
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`independent of...transmission of data.” Response, 35. This argument is baseless
`
`and contradicts Bowie’s express teachings.
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`Patent Owner ignores the fact that Bowie stores “loop transmission
`
`characteristics.” Ex.1005, 5:62-66. These “loop transmission characteristics” are
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`“retrieved from memory [] and used to enable data transmission to resume
`
`quickly,” when returning to full power mode. Ex.1005, 5:60-66; see also, id. 5:23-
`
`25 (“Storing loop characteristics enables rapid resumption of user data
`
`transmission when the units are returned to full power mode.”); Petition, 35-36.
`
`Patent Owner never addresses Bowie’s disclosure which makes clear that the
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`stored loop characteristics are associated with “transmission” of user data in full
`
`power mode.
`
`Further, as explained in the Petition and Dr. Kiaei’s declaration, Bowie
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`determines the loop transmission characteristics by exchanging information.
`
`Petition, 3. According to Bowie, “[t]his exchange of information is often referred
`
`to as handshaking. Once handshaking is completed, transmission of user data
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`may begin.” Ex.1005, 4:64-5:5. Bowie then stores this exchanged information
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`(e.g.., loop transmission characteristics) during low power mode. Id., 5:17-19.
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`Since after handshaking data transmission may begin, Bowie’s handshaking is part
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`of initialization and includes the exchange of transmission and reception data. This
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`is evidenced by the ‘268 patent, which recognizes that “it is necessary to initialize
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`prior to the transmission and reception of data. This initialization
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`includes...calculating the bit-allocation tables ...and exchanging these tables.”
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`Ex.1001, 3:12-25; see also, Ex.2008, 87 (“During the exchange process each
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`receiver shares with its corresponding far-end transmitter certain transmission
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`settings that it expects to see. Specifically, each receiver communicates to its far-
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`end transmitter the number of bits.”) Therefore, Bowie’s loop transmission
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`characteristics exchanged during handshaking/initialization include parameters
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`used for transmission of user data.
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`Indeed, if Bowie’s loop transmission characteristics were not associated with
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`transmission, then before transmitting user data, the modem would have to
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`initialize/re-initialize (which takes significant amount of time). See, e.g., Ex.1001,
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`3:29-34 (“the time required to initialize or re-initialize the system after a
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`suspension of operation in connection with power conservation is generally
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`unacceptable”). But no initialization/re-initialization occurs since Bowie states
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`that “data transmission…resume[s] quickly” and there is a “rapid resumption of
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`user data transmission.” Ex.1005, 5: 23-25, 60-66. Accordingly, Bowie’s loop
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`transmission characteristics are in fact used for transmission—hence the usage of
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`the term “transmission” in the phrase “loop transmission characteristics.” Ex.1005,
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`5:60-66.
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Therefore, even under Patent Owner’s construction, Bowie’s loop
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`transmission characteristics that enable user data transmission to resume quickly,
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`teach “parameters associated with the full power mode operation.”
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`IV. A POSITA Would Have Been Motivated To Combine Bowie And
`Yamano
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`Patent Owner argues that a POSITA would not have combined the teachings
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`of Bowie and Yamano in the manner set forth in the Petition for a number of
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`reasons. See Response, 37-55. Each meritless argument is addressed below.
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`A. The teachings of Bowie and Yamano are compatible.
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`Patent Owner argues that “an ADSL-based system, like the one disclosed in
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`Bowie, is not compatible with the burst mode protocol of Yamano.” Response, 37.
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`According to Patent Owner, “Bowie’s ADSL-based system was intended to
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`comply with the 1995 ADSL Standard” and “Yamano’s burst mode protocol...does
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`not comply with the superframe structure required by the 1995 ADSL Standard.”
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`Id., 37-39. This argument mischaracterizes the art and lacks merit.
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`Patent Owner’s argument that Bowie “intended” to constantly transmit
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`superframes (even in low power mode) is baseless. Bowie never mentions—much
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`less requires—continuous transmission of superframes. To the contrary, Bowie
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`“shut[s] off…sections of signal processing 111, transmitting 112, and receiving
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`113 circuitry” and places the loop “in an inactive state,” which means that
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`superframes are not sent during Bowie’s low power mode. Ex.1005, 5:26-28.
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`Accordingly, Patent Owner’s argument that Bowie “intended” to transmit
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`superframe idle data during low power is unsupported.
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`Further, while Yamano does not specifically use the term “superframes,”
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`Yamano does in fact teach that during full power, its modem processes “an analog
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`signal in accordance with a conventional modem protocol, such as xDSL.”
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`Ex.1006, 7:18-20. The ADSL standard is a variant of a conventional xDSL
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`protocol contemplated in Yamano. Ex.1003, pp. 32-33; Ex.1001, 1:47-50.
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`Accordingly, Yamano is capable of processing superframes per the ADSL
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`standard. Ex.1012, ¶22.
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`Further still, Patent Owner makes no showing that the ADSL Standard,
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`which provides the minimal requirements for full power mode operation, somehow
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`restricts implementation of proprietary improvements in low power mode. Patent
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`Owner cannot, because the ADSL Standard expressly allows for improvements
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`(e.g., low power mode as in Bowie and Yamano), recognizing that “[e]quipment
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`may be implemented with additional functions and procedures.” Ex.2008, 2. As
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`Dr. Kiaei explains, “a POSITA would understand Yamano’s burst mode to be
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`compatible with the ANSI standard because low power mode operation is just an
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`additional function that the standard permits.” Ex.1012, ¶23.
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`Therefore, Patent Owner fails to make a showing that Yamano and Bowie
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`are incompatible. In re Ratti, 270 F.2d 810, 813, 123 USPQ 349, 352 (CCPA
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`1959).
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`B.
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`The obviousness analysis is based on the prior art teachings—not
`hindsight.
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`Patent Owner argues that the Petition relied on hindsight because allegedly,
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`Yamano “does not comply with the 1995 ADSL standard” and Bowie requires
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`compliance. Response, 41. As discussed above, the ADSL standard does not
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`prohibit low power modes like those described in Bowie and Yamano.
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`Nevertheless, Yamano’s modem processes “an analog signal in accordance with a
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`conventional modem protocol, such as xDSL,” which includes the ADSL standard.
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`Ex.1006, 7:18-20; Ex. 1003, pp.32-33; Ex.1001, 1:47-50. Therefore, the teachings
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`are compatible and the Petition did not rely on hindsight.
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`Patent Owner also argues that “combining Bowie’s shut-down signal with
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`Yamano… would be superfluous and, in fact, would add unnecessary complexity.”
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`Response, 43. Patent Owner appears confused since Petitioner is not adding
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`Bowie’s shut-down signal to Yamano; instead, Bowie is modified in view of
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`Yamano’s teachings. And, as explained by Dr. Kiaei, the teachings would have
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`been combined since “both Bowie and Yamano teach reducing power consumption
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`of a DSL modem when data is not being transmitted or received.” Ex.1003, p.33.
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`Dr. Kiaei also explained that “[g]iven that Yamano teaches activating only the
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`portion of the modem needed for communication, rather than the entire modem as
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`in Bowie, a POSITA would have understood that power saving could be further
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`gained by applying Yamano’s teachings into Bowie’s system, thereby resulting in
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`more refined power saving potential across thousands of transmit and receive
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`circuits supporting thousands of data connections.” Id., p.34.
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`Therefore, Petitioner relied on the teachings of the references to show that a
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`POSITA would have combined Yamano with Bowie to improve the reduction in
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`power consumption, which both references recognize as desirable. Ex.1005,
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`Abstract (“conserving power in terminal”); Ex.1006, 10:58-59 (“reduce power
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`consumption of the processing element”).
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`C. Bowie and Yamano render obvious that the transmitter enters
`low power mode.
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`Patent Owner argues that the Petition “hinges on an incorrect and
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`unsupported understanding of Yamano’s transmitter.” Response, 41. According to
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`Patent Owner, nothing “describes reducing the processing power of the
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`transmitter” and the “only thing described in Yamano as going into a reduced
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`processing mode is the receiver circuit.” Id., 42. This is incorrect.
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`First, as discussed above, Bowie teaches that the transmitter enters low
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`power mode based on a shut-down signal. See Section III.A. Patent Owner cannot
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`show nonobviousness by attacking the references individually where the rejections
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`are based on combinations of references. In re Keller, 642 F.2d 413, 426 (Fed. Cir.
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`Petitioner’s Reply
`IPR2016-01760 (Patent No. 9,094,268)
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`1981); In re Merck & Co., Inc., 800 F.2d 1091 (Fed. Cir. 1986).
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`Second, Yamano teaches that burst mode provides low power since “[t]he
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`transmitter circuit only sends information when there is meaningful packet data
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`ava