IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`A PHY is not required to meet the RX_CLK and TX_CLK signal functional requirements when either bit
`0.11 or bit 0.10 is set to a logic one. A PHY shall meet the RX_CLK and TX_CLK signal functional require-
`ments defined in 22.2.2 within 0.5 s after both bit 0.11 and 0.10 are cleared to zero.
`
`The default value of bit 0.11 is zero.
`
`22.2.4.1 .6 Isolate
`
`The PHY may be forced to electrically isolate its data paths from the M11 by setting bit 0.10 to a logic one.
`Clearing bit 0.10 allows normal operation. When the PHY is isolated from the M11 it shall not respond to the
`TXD<3:0>, TX_EN, and TX_ER inputs, and it shall present a high impedance on its TX_CLK, RX_CLK,
`RX_DV, RX_ER, RXD<3:0>, COL, and CRS outputs. When the PHY is isolated from the M11 it shall
`respond to management transactions.
`
`A PHY that is connected to the M11 via the mechanical interface defined in 22.6 shall have a default value of
`
`one for bit 0.10 so as to avoid the possibility of having multiple MII output drivers actively driving the same
`signal path simultaneously.
`
`NOTE—This clause neither requires nor assumes any specific behavior at the MDI resulting from setting bit 0.10 to a
`logic one.
`
`22.2.4.1.7 Restart Auto-Negotiation
`
`If a PHY reports via bit 1.3 that it lacks the ability to perform Auto-Negotiation, or if Auto-Negotiation is
`disabled, the PHY shall return a value of zero in bit 0.9. If a PHY reports via bit 1.3 that it lacks the ability to
`perform Auto-Negotiation, or if Auto-Negotiation is disabled, bit 0.9 should always be written as zero, and
`any attempt to write a one to bit 0.9 shall be ignored.
`
`Otherwise, the Auto-Negotiation process shall be restarted by setting bit 0.9 to a logic one. This bit is self-
`clearing, and a PHY shall retum a value of one in bit 0.9 until the Auto-Negotiation process has been initi-
`ated. The Auto-Negotiation process shall not be affected by writing a zero to bit 0.9.
`
`The default value of bit 0.9 is zero.
`
`22.2.4.1 .8 Duplex mode
`
`The duplex mode can be selected via either the Auto-Negotiation process, or manual duplex selection. Man-
`ual duplex selection is allowed when Auto-Negotiation is disabled by clearing bit 0.12 to zero. When Auto-
`Negotiation is disabled, setting bit 0.8 to a logic one configures the PHY for f11ll-duplex operation, and clear-
`ing bit 0.8 to a logic zero configures the PHY for half-duplex operation. When Auto-Negotiation is enabled,
`bit 0.8 can be read or written, but the state of bit 0.8 has no effect on the link configuration. If a PHY reports
`via bits 1.15:1 1 that it is able to operate in only one duplex mode, the value of bit 0.8 shall correspond to the
`mode in which the PHY can operate, and any attempt to change the setting of bit 0.8 shall be ignored.
`
`When a PHY is placed in the loopback mode of operation via bit 0.14, the behavior of the PHY shall not be
`affected by the state of bit 0.8.
`
`The default Value of bit 0.8 is zero, unless a PHY reports Via bits 1.l5:1l that it is able to operate only in
`f11ll-duplex mode, in which case the default value of bit 0.8 is one.
`
`22.2.4.1.9 Collision test
`
`The COL signal at the MII may be tested by setting bit 0.7 to a logic one. When bit 0.7 is set to one, the PHY
`shall assert the COL signal within 512 BT in response to the assertion of TX_EN. While bit 0.7 is set to one,
`
`This is an54\rchive IEEE Standard.
`
`It has been superseded byogplaggrg/g§§iggEg(..tI{gs,s;agagard.
`
`
`
`Aerohive - Exhibit 1025
`
`0070
`
`

`

`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`the PHY shall de—assert the COL signal within 4 BT in response to the de-assertion of TX_EN. Clearing bit
`0.7 to zero allows normal operation.
`
`The default value of bit 0.7 is zero.
`
`NOTE—It is recommended that the Collision Test fimction be used only in conjunction with the loopback mode of oper-
`ation defined in 22.2.4.l.2.
`
`22.2.4.1.10 Reserved bits
`
`Bits 0.620 are reserved for future standardization. They shall be written as zero and shall be ignored when
`read; however, a PHY shall return the value zero in these bits.
`
`22.2.4.2 Status register (register 1)
`
`The assignment of bits in the Status register is shown in table 22-8 below. All of the bits in the Status register
`are read only, a write to the Status register shall have no effect.
`
`Table 8—Status register bit definitions
`
`l00BASE-T4
`
`l = PHY able to perform l00BASE-T4
`0 = PHY not able to perform l00BASE-T4
`
`Description
`
`l00BASE-X Full Duplexl
`
`l00BASE-X Half Duplex
`
`10 Mb/s Full Duplexb
`
`10 Mb/s Half Duplex
`
`Reserved
`MF Preamble Suppression
`
`Auto-Negotiation
`Complete
`Remote Fault
`
`Auto-Negotiation Ability
`
`Link Status
`
`Jabber Detect
`
`Extended Capability
`
`l = PHY able to perform full-duplex l00BASE-X
`0 = PHY not able to perform fiill-duplex l00BASE-X
`1 = PHY able to perform half-duplex l00BASE-X
`0 = PHY not able to perform half-duplex l00BASE-X
`l = PHY able to operate at 10 Mb/s in full-duplex mode
`0 = PHY not able to operate at 10 Mb/s in full-duplex mode
`1 = PHY able to operate at 10 Mb/s in half-duplex mode
`0 = PHY not able to operate at 10 Mb/s in half-duplex mode
`ignore when read
`l = PHY will accept management flames with preamble
`suppressed.
`0 = PHY will not accept management frames with preamble
`suppressed.
`1 = Auto-Negotiation process completed
`0 = Auto-Negotiation process not completed
`l = remote fault condition detected
`0 = no remote fault condition detected
`
`l = PHY is able to perform Auto-Negotiation
`0 = PHY is not able to perform Auto-Negotiation
`1 = link is up
`0 = link is down
`
`l = jabber condition detected
`0 = no jabber condition detected
`= extended register capabilities
`0 = basic register set capabilities only
`
`*R0 = Read Only, LL = Latching Low, LH = Latching High
`lspecifications for full-duplex mode operation are plarmed for future work.
`
`This is arbelgfigii/@1EfiEE§tanggrg,e,lL@as been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1025
`
`0071
`
`Aerohive - Exhibit 1025
`
`0071
`
`

`

`IEEE
`Std 802.3, 1998 Edition
`
`22.2.4.2.1 100BASE-T4 ability
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`When read as a logic one, bit 1.15 indicates that the PHY has the ability to perform link transmission and
`reception using the IOOBASE-T4 signaling specification. When read as a logic zero, bit 1.15 indicates that
`the PHY lacks the ability to perform link transmission and reception using the 100BASE-T4 signaling spec-
`ification.
`
`22.2.4.2.2 100BASE-X full-duplex ability
`
`When read as a logic one, bit 1.14 indicates that the PHY has the ability to perform firll-duplex link trans-
`mission and reception using the 100BASE-X signaling specification. When read as a logic zero, bit 1.14
`indicates that the PHY lacks the ability to perform full-duplex link transmission and reception using the
`100BASE-X signaling specification.
`
`NOTE—Specifications for fi1ll-duplex mode operation are planned for future work.
`
`22.2.4.2.3 100BASE-X half-duplex ability
`
`When read as a logic one, bit 1.13 indicates that the PHY has the ability to perform half-duplex link trans-
`mission and reception using the 100BASE-X signaling specification. When read as a logic zero, bit 1.13
`indicates that the PHY lacks the ability to perform half-duplex link transmission and reception using the
`100BASE-X signaling specification.
`
`22.2.4.2.4 10 Mbls full-duplex ability
`
`When read as a logic one, bit 1.12 indicates that the PHY has the ability to perform full duplex link transmis-
`sion and reception while operating at 10 Mb/s. When read as a logic zero, bit 1.12 indicates that the PHY
`lacks the ability to perform full duplex link transmission and reception while operating at 10 Mb/s.
`
`NOTE—Specifications for fi111-duplex mode operation are planned for fiiture work.
`
`22.2.4.2.5 10 Mbls half-duplex ability
`
`When read as a logic one, bit 1.11 indicates that the PHY has the ability to perform half-duplex link trans-
`mission and reception while operating at 10 Mb/s. When read as a logic zero, bit 1.11 indicates that the PHY
`lacks the ability to perform half-duplex link transmission and reception while operating at 10 Mb/s.
`
`22.2.4.2.6 Reserved bits
`
`Bits 1.10:7 are reserved for future standardization and shall be ignored when read; however, a PHY shall
`return the value zero in these bits. Bits 1.10:8 are specifically reserved for future PHY capabilities that will
`be reflected in the Auto—Negotiation base link code word Technology Ability field, as defined in 28.2.1.2.
`
`22.2.4.2.7 MF preamble suppression ability
`
`When read as a logic one, bit 1.6 indicates that the PHY is able to accept management frames regardless of
`whether they are or are not preceded by the preamble pattern described in 22.2.4.4.2. When read as a logic
`zero, bit 1.6 indicates that the PHY is not able to accept management fiames unless they are preceded by the
`preamble pattern described in 22.2.4.4.2.
`
`22.2.4.2.8 Auto-Negotiation complete
`
`When read as a logic one, bit 1.5 indicates that the Auto—Negotiation process has been completed, and that
`the contents of registers 4, 5, 6, and 7 are valid. When read as a logic zero, bit 1.5 indicates that the Auto-
`
`This is an5gtrchive IEEE Standard.
`
`It has been superseded byogplaggrg/g§§iggEg(..tl{gsss;agag@rd.
`
`0072
`
`it 1025
`
`Aerohive - Exhibit 1025
`
`0072
`
`

`

`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`Negotiation process has not been completed, and that the contents of registers 4, 5, 6, and 7 are meaningless.
`A PHY shall return a value of zero in bit 1.5 if Auto-Negotiation is disabled by clearing bit 0.12. A PHY
`shall also return a value of zero in bit 1.5 if it lacks the ability to perform Auto-Negotiation.
`
`22.2.4.2.9 Remote fault
`
`When read as a logic one, bit 1.4 indicates that a remote fault condition has been detected. The type of fault
`as well as the criteria and method of fault detection is PHY specific. The Remote Fault bit shall be imple-
`mented with a latching function, such that the occurrence of a remote fault will cause the Remote Fault bit to
`become set and remain set until it is cleared. The Remote Fault bit shall be cleared each time register 1 is
`read via the management interface, and shall also be cleared by a PHY reset.
`
`If a PHY has no provision for remote fault detection, it shall maintain bit 1.4 in a cleared state. Further infor-
`mation regarding the remote fault indication can be found in 28.2.1.2, and in 24.3.2.1.
`
`22.2.4.2.10 Auto-Negotiation ability
`
`When read as a logic one, bit 1.3 indicates that the PHY has the ability to perform Auto-Negotiation. When
`read as a logic zero, bit 1.3 indicates that the PHY lacks the ability to perform Auto-Negotiation.
`
`22.2.4.2.11 Link Status
`
`When read as a logic one, bit 1.2 indicates that the PHY has determined that a valid link has been estab-
`lished. When read as a logic zero, bit 1.2 indicates that the link is not valid. The criteria for determining link
`validity is PHY specific. The Link Status bit shall be implemented with a latching function, such that the
`occurrence of a link failure condition will cause the Link Status bit to become cleared and remain cleared
`
`until it is read via the management interface. This status indication is intended to support the management
`attribute defined in 30.5. 1 . l .4, aMediaAvailable.
`
`22.2.4.2.12 Jabber detect
`
`When read as a logic one, bit 1.1 indicates that a jabber condition has been detected. This status indication is
`intended to support the management attribute defined in 30.5 . 1.1.6, aJabber, and the MAU notification
`defined in 30.5. 1 .3.1, nJabber. The criteria for the detection of a jabber condition is PHY specific. The Jabber
`Detect bit shall be implemented with a latching function, such that the occurrence of a jabber condition will
`cause the Jabber Detect bit to become set and remain set until it is cleared. The Jabber Detect bit shall be
`
`cleared each time register 1 is read via the management interface, and shall also be cleared by a PHY reset.
`
`PHYs specified for 100 Mb/s operation (IOOBASE-X and l00BASE-T4) do not incorporate a Jabber Detect
`fimction, as this function is defined to be performed in the repeater unit in 100 Mb/s systems. Therefore,
`l00BASE-X and l00BASE-T4 PHYs shall always return a value of zero in bit 1.1.
`
`22.2.4.2.13 Extended capability
`
`When read as a logic one, bit 1.0 indicates that the PHY provides an extended set of capabilities which may
`be accessed through the extended register set. When read as a logic zero, bit 1.0 indicates that the PHY pro-
`vides only the basic register set.
`
`22.2.4.3 Extended capability registers
`
`In addition to the basic register set defined in 22.2.4.1 and 22.2.4.2, PHYs may provide an extended set of
`capabilities that may be accessed and controlled via the MH management interface. Six registers have been
`defined within the extended address space for the purpose of providing a PHY-specific identifier to layer
`management, and to provide control and monitoring for the Auto-Negotiation process.
`
`This is arbeigfigii/@1EfiEE§tanggr,d,e,lt,has been superseded by a later version of this standard.
`
`0073
`
`it 1025
`
`Aerohive - Exhibit 1025
`
`0073
`
`

`

`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`If an attempt is made to perform a read transaction to a register in the extended register set, and the PHY
`being read does not implement the addressed register, the PHY shall not drive the MDIO line in response to
`the read 1ransaction. If an attempt is made to perform a write transaction to a register in the extended register
`set, and the PHY being written does not implement the addressed register, the write transaction shall be
`ignored by the PHY.
`
`22.2.4.3.1 PHY Identifier (registers 2 and 3)
`
`Registers 2 and 3 provide a 32-bit value, which shall constitute a unique identifier for a particular type of
`PHY. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier.
`
`Bit 2.15 shall be the MSB of the PHY Identifier, and bit 3.0 shall be the LSB of the PHY Identifier.
`
`The PHY Identifier shall be composed of the third through 24th bits of the Organizationally Unique Identi-
`fier (OUI) assigned to the PHY manufacturer by the IEEE,28 plus a six-bit manufacturer’s model number,
`plus a four—bit manufacturer’s revision number. The PHY Identifier is intended to provide sufficient informa-
`tion to support the oResourceTypeID object as required in 30.1.2.
`
`The third bit of the OUI is assigned to bit 2.15, the fourth bit of the OUI is assigned to bit 2.14, and so on. Bit
`2.0 contains the eighteenth bit of the OUI. Bit 3.15 contains the nineteenth bit of the OUI, and bit 3.10 con-
`tains the twenty-fourth bit of the OUI. Bit 3.9 contains the MSB of the manufacturer’s model number. Bit 3.4
`contains the LSB of the manufacturer’s model number. Bit 3.3 contains the MSB of the manufacturer’s revi-
`
`sion number, and bit 3.0 contains the LSB of the manufacturer’s revision number.
`
`Figure 22-12 depicts the mapping of this information to the bits of Registers 2 and 3. Additional detail
`describing the format of OUIs can be found in IEEE Std 802-1990.
`
`
`
`22.2.4.3.2 Auto-Negotiation advertisement (register 4)
`
`Register 4 provides 16 bits that are used by the Auto-Negotiation process. See 28.2.4.1.
`
`28Interested applicants should contact the IEEE Standards Department, Institute of Electrical and Electronics Engineers, 445 Hoes
`Lane, PO. Box 1331, Piscataway, NJ 08855-1331, USA.
`
`This is an5Archive IEEE Standard.
`
`It has been superseded byogpigggrg/g§§iggEg(..ti;is,s;agag@rd.
`
`0074
`
`1025
`
`Aerohive - Exhibit 1025
`
`0074
`
`

`

`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`22.2.4.3.3 Auto-Negotiation link partner ability (register 5)
`
`Register 5 provides 16 bits that are used by the Auto-Negotiation process. See 28.2.4.1.
`
`22.2.4.3.4 Auto-Negotiation expansion (register 6)
`
`Register 6 provides 16 bits that are used by the Auto-Negotiation process. See 28.2.4.1.
`
`22.2.4.3.5 Auto-Negotiation next page (register 7)
`
`Register 7 provides 16 bits that are used by the Auto-Negotiation process. See 28.2.4.1.
`
`22.2.4.3.6 PHY specific registers
`
`A particular PHY may provide additional registers beyond those defined above. Register addresses 16
`through 31 (decimal) may be used to provide vendor-specific functions or abilities. Register addresses 8
`through 15 (decimal) are reserved for assignment within future editions of this standard.
`
`22.2.4.4 Management frame structure
`
`Frames transmitted on the MII Management Interface shall have the fi'arne structure shown in table 22-9.
`The order of bit transmission shall be fi'om lefl to right.
`
`Table 9—Management frame format
`
`
`
`22.2.4.4.1 IDLE (IDLE condition)
`
`The IDLE condition on MDIO is a high-impedance state. All three state drivers shall be disabled and the
`PHY’s pull-up resistor will pull the MDIO line to a logic one.
`
`22.2.4.4.2 PRE (preamble)
`
`At the beginning of each transaction, the station management entity shall send a sequence of 32 contiguous
`logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can
`use to establish synchronization. A PHY shall observe a sequence of 32 contiguous one bits on MDIO with
`32 corresponding cycles on MDC before it responds to any transaction.
`
`If the STA determines that every PHY that is connected to the MDIO signal is able to accept management
`flames that are not preceded by the preamble pattern, then the STA may suppress the generation of the pre-
`amble pattern, and may initiate management frames with the ST (Start of Frame) pattern.
`
`22.2.4.4.3 ST (start of frame)
`
`The start of frame is indicated by a <0l> pattern. This pattern assures transitions from the default logic one
`line state to zero and back to one.
`
`This is arbe()§fiE|()I@1Efi&§Ifin§igr,d,e,lLj]aS been superseded by a later version of this stancggrd.
`
`
`
`
`it 1025
`
`0075
`
`Aerohive - Exhibit 1025
`
`0075
`
`

`

`IEEE
`Std 802.3, 1993 Edition
`
`22 2.4.4.4 OP {operation code}
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`The operation code for a read transaction is <l03>, while the ope1'ation code for a write transaction is <01?-.
`
`22.2.4.4.5 PHYAD {PHY Address}
`
`The PHY Address is five bits, allowing 32 unique PHY addresses. The first PHY address bit transmitted and
`received is the MSB of the address. A PHY that is connected to the station management entity via the
`mechanical interface defined in 22.6 shall always respond to transactions addressed to PHY Address zero
`<00000>. A station management entity that is attached to multiple PHYS must have a priori knowledge of
`the appropriate PHY Address for each PHY.
`
`22.2.4.4.6 REGAD (Register Address}
`
`The Register Address is five bits. allowing 32 individual registers to be addressed within each PHY. The first
`Register Address bit transmitted and received is the MSB of the address. The register‘ accessed at Register
`Address zero <00000> shall be the control register defined in 22.2.4.1, and the register accessed at Register
`Address one <00001> shall be the status register defined in 22.2.4.2.
`
`22.2.4.4} TA {turnaround}
`
`The turnaround time is a 2 bit time spacing between the Register Address field and the Data field of a man-
`agement frame to avoid contention during a read transaction. For a read transaction, both the STA and the
`PHY shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shall drive a
`zero bit during the second bit time of the turnaround of a read transaction. During a write transaction. the
`STA shall drive a one bit for the first bit time of the turnaround and a zero bit for the second bit time of the
`
`turnaround. Figure 22-13 shows the behavior of the Ix/[D10 signal during the turnaround field of a read trans-
`action.
`
`Figure 22-13—Behavior of MDIO during TA field of a read transaction
`
`22.2.4.4.8 DATA {data}
`
`The data field is 16 bits. The first data bit transmitted and received shall be bit 15 of the register being
`addressed.
`
`22.3 Signal timing characteristics
`
`All signal timing characteristics shall be measured using the techniques specified in armex 22C. The signal
`
`threshold potentials Vihcmm) and Vmmax} are defined in 22.4.4.1.
`
`This is arwirchive IEEE Standard.
`
`It has been superseded by0ap{a§er@»g§§iQgEq{..t.h_,i.§s$;§adard.
`
`Aerohive - Exhib
`
`Aerohive - Exhibit 1025
`
`0076
`
`

`

`CSMNCD
`
`IEEE
`Std 302.3, 1993 Edition
`
`The HIGH time of an M11 signal is defined as the length of time that the potential of the sig:nal is greater than
`
`or equal to Vihwn-n)_ The LOW time of an MII signal is defined as the length of time that the potential of the
`signal is less than or equal to Vmmu).
`
`The setup time of an M11 signal relative to an MII clock edge is defined as the length of time between when
`the signal exits and remains out of the switching region and when the clock enters the switching region. The
`hold time of an MII signal relative to an M11 clock edge is defined as the length of time between when the
`clock exits the switching region and when the signal enters the switching region.
`
`The propagation delay from an Ml] clock edge to a valid MII signal is defined as the length of time between
`when the clock exits the switching region and when the signal exits and remains out of the switching region.
`
`22.3.1 Signals that are synchronous to TX_CLK
`
`Figure 22-14 shows the timing relationship for the sigials associated with the transmit data path at the MII
`connector. The clock to output delay shall be a minimum of 0 ns and a maximum of 25 ns.
`
`T)(_CLK
`
`v v v V V r
`
`TXD<3IU>, TX_EN, TX_ER
`
`'lIJ;'IA'A\ K
`J.Q.§.§.C.§.
`
`v
`
`C K
`
`V:h(min]
`
`V*'(W)
`
`_
`
`Vflmax)
`
`Figure 22-14—Transmit signal timing relationships at the MII
`
`22.3.1.1 TX_EN
`
`TX_EN is transitioned by the Reconciliation sublayer synchronously with respect to the TX_CLK rising
`edge with the timing as shown in figure 22-I4.
`
`22.3.1.2 TXD<3:0>
`
`TXD<3:0> is transitioned by the Reconciliation sublayer synchronously with respect to the TX_CLK rising
`edge with the timing as depicted in figure 22-14.
`
`22.3.1.3 TX_ER
`
`TX_ER is transitioned synchronously with respect to the rising edge of TX_CLK as shown in figure 22-14.
`
`22.3.2 Signals that are synchronous to RX_CLK
`
`Figure 22-15 shows the timing relationship for the sigials associated with the receive data path at the MII
`connector. The timing is referenced to the rising edge of the RX_CLK. The input setup time shall be a mini-
`mum of 10 ns and the input hold time shall be a minimum of 10 us.
`
`This is arbep§qQi}.@1tE§fi§tan§grQ5eA,t,j]as been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1
`
`Aerohive - Exhibit 1025
`
`0077
`
`

`

`IEEE
`Std 802.3, 1993 Edilion
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`RX_CLK
`
`RXD<3Ii]>, RX_DV, RX_ER
`
`Vih(min)
`vihmx}
`
`Vih(min]
`Vimmax)
`
`Figure 22-15—Receive signal timing relationships at the Mll
`
`22.3.2.1 RX_DV
`
`RX_DV is sampled by the Reconciliation sublayer synchronously with respect to the rising edge of
`RX_CLK with the timing shown in figure 22-15.
`
`22.3.2.2 RXD<3:0>
`
`RXD<3:0> is sampled by the Reconciliation sublayer synchronously with respect to the rising edge of
`RX_CLK as shown in figure 22-1 5. The RXD<3:0> timing requirements must be met at all rising edges of
`RX_CLK.
`
`22.3.2.3 RX_ER
`
`RX_ER is sampled by the Reconciliation sublayer synchronously with respect to the rising edge of
`RX_CLK as shovm in figure 22-15. The RX_ER timing requirements must be met at all rising edges of
`RX CLK.
`
`22.3.3 Signals that have no required clock relationship
`
`22.3.3.1 CRS
`
`CRS is driven by the PHY'. Transitions on CR8 have no required relationship to either of the clock signals
`provided at the M11.
`
`22.3.3.2 COL
`
`COL is driven by the PHY. Transitions on COL have no required relationship to either of the clock signals
`provided at the M11.
`
`22.3.4 MDIO timing relationship to MDC
`
`MDIO (Management Data Input/Output) is a bidirectional signal that can be sourced by the Station Manage-
`ment Entity (STA) or the PHY. When the STA sources the MDIO signal, the STA shall provide a minimum
`of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of MDC. as shown
`in figure 22-16, measured at the M11 connector.
`
`When the MDIO signal is sourced by the PHY, it is sampled by the STA synchronously with respect to the
`rising edge of MDC. The clock to output delay from the PHY. as measured at the M11 connector. shall be a
`minimum ofO ns, and a maximum of 300 115, as shown i.n figure 22-17.
`
`This is angfiirchive IEEE Standard.
`
`It has been superseded by0gpla§a[@»g§§iQgEqt..t.h_,i§S$;§agard.
`
`Aerohive - Exhibit 10
`
`00
`
`Aerohive - Exhibit 1025
`
`0078
`
`

`

`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`MDC
`
`MDIO
`
`MDC
`
`MDIO
`
`
`
`V'9'9‘9‘9'.'
`Vih(min)
`K\\Y6Y6Y6YIl’7
`Dlofoioiofoii
`
`rl:.v.v.v.v.\ l
`1.;
`Vi|(max)
`
`
`
`
`
`Figure 22-17—MDlO sourced by PHY
`
`22.4 Electrical characteristics
`
`The electrical characteristics of the M11 are specified such that the three application environments described
`in 22.1 are accommodated. The electrical specifications are optimized for the integrated circuit to integrated
`circuit application environment, but integrated circuit drivers and receivers that are implemented in compli-
`ance with the specification will also support the mother board to daughter board and short cable application
`environments, provided those environments are constrained to the limits specified in this clause.
`
`NOTE—The specifications for the driver and receiver characteristics can be met with TTL compatible input and output
`buffers implemented in a digital CMOS ASIC process.
`
`22.4.1 Signal levels
`
`The MII uses TTL signal levels, which are compatible with devices operating at a nominal supply voltage of
`either 5.0 or 3.3 V.
`
`NOTE—Care should be taken to ensure that all MII receivers can tolerate dc input potentials from 0.00 V to 5.50 V, refer-
`enced to the COMMON signal, and transient input potentials as high as 7.3 V, or as low as -1.8 V, referenced to the COM-
`MON signal, which can occur when IVHI signals change state. The transient duration will not exceed 15 ns. The dc source
`impedance will be no less than Roh(m]-H). The transient source impedance will be no less than (68 X 0.85 =) 57.8 $2.
`
`This is arbetgfigiii/@1fifiEE§tan§i,grg,e,lt,§]as been superseded by a later version of this standgrd.
`
`
`
`Aerohive - Exhibit 1025
`
`0079
`
`

`

`IEEE
`Std 802.3, 1998 Edition
`
`22.4.2 Signal paths
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`MII signals can be divided into two groups: signals that go between the STA and the PHY, and signals that
`go between the Reconciliation sublayer and the PHY.
`
`Signals between the STA and the PHY may connect to one or more PHYs. When a signal goes between the
`STA and a single PHY, the signal’s path is a point—to—point transmission path. When a signal goes between
`the STA and multiple PHYS, the signal’s transmission path has drivers and receivers attached in any order
`along the length of the path and is not considered a point-to-point transmission path.
`
`Signals between the Reconciliation sublayer and the PHY may also connect to one or more PHYS. However,
`the transmission path of each of these signals shall be either a point-to-point transmission path or a sequence
`of point-to-point transmission paths connected in series.
`
`All connections to a point—to—point transmission path are at the path ends. The simplest point-to-point trans-
`mission path has a driver at one end and a receiver at the other. Point-to-point transmission paths can also
`have more than one driver and more than one receiver if the drivers and receivers are lumped at the ends of
`the path, and if the maximum propagation delay between the drivers and receivers at a given end of the path
`is a very small fraction of the 10%—90% rise/fall time for signals driven onto the path.
`
`The MII shall use unbalanced signal transmission paths. The characteristic impedance Z0 of transmission
`paths is not specified for electrically short paths where transmission line reflections can be safely ignored.
`
`The characteristic impedance Z0 of electrically long transmission paths or path segments shall be 68 Q :|: 15%.
`
`The output impedance of the driver shall be used to control transmission line reflections on all electrically
`long point-to-point signal paths.
`
`NOTE—In the context of this clause, a transmission path whose round-trip propagation delay is less than half of the
`l0%—90% rise/fall time of signals driven onto the path is considered an electrically short transmission path.
`
`22.4.3 Driver characteristics
`
`The driver characteristics defined in this clause apply to all MII signal drivers. The driver characteristics are
`specified in terms of both their ac and dc characteristics.
`
`NOTE—Rail-to-rail drivers that comply with the driver output V-I diagrams in annex 22B will meet the following ac and
`dc characteristics.
`
`22.4.3.1 DC characteristics
`
`The high (one) logic level output potential Voh shall be no less than 2.40 V at an output current 1011 of -4.0 mA.
`The low (zero) logic level output potential V01 shall not be greater than 0.40V at an output current 101 of
`4.0 mA.
`
`22.4.3.2 AC characteristics
`
`Drivers must also meet certain ac specifications in order to ensure adequate signal quality for electrically
`long point—to—point transmission paths. The ac specifications shall guarantee the following performance
`requirements.
`
`The initial incident potential change arriving at the receiving end of a point-to-point MII signal path plus its
`reflection from the receiving end of the path must switch the receiver input potential monotonically fi'om a
`
`valid high (one) level to Vil S Vmmax) — 200 mV, or from a valid low (zero) level to Vih Z Vimmin) + 200 mV,
`
`This is an54\rchive IEEE Standard.
`
`It has been superseded byogpigggrg/g§§iggEg(..ti;isss;agagard.
`
`0080
`
`1025
`
`Aerohive - Exhibit 1025
`
`0080
`
`

`

`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`Subsequent incident potential changes arriving at the receiving end of a point—to—point MII signal path plus
`their reflections from the receiving end of the path must not cause the receiver input potential to reenter the
`
`range Vimiiax) — 200 mV < Vi < Vimmin) + 200 mV except when switching from one valid logic level to the
`other. Such subsequent incident potential changes result from a mismatch between the characteristic imped-
`ance of the signal path and the driver output impedance.
`
`22.4.4 Receiver characteristics
`
`The receiver characteristics are specified in terms of the threshold levels for the logical high (one) and logi-
`cal low (zero) states. In addition, receivers must meet the input current and capacitance limits.
`
`22.4.4.1 Voltage thresholds
`
`An input potential Vi of 2.00 V or greater shall be interpreted by the receiver as a logical high (one). Thus,
`Vih(miii) = 2.00 V. An input potential Vi of 0.80 V or less shall be interpreted by the receiver as a logical low
`(zero). Thus, Vii(ma,i) = 0.80 V. The switching region is defined as signal potentials greater than Vii(max) and
`less than Viii(miii). When the input signal potential is in the switching region, the receiver output is undefined.
`
`22.4.4.2 Input current
`
`The input current requirements shall be measured at the MII connector and shall be referenced to the +5 V
`supply and COMMON pins of the connector. The input current requirements shall be met across the full
`range of supply voltage specified in 22.5.].
`
`The bidirectional signal MDIO has two sets of input current requirements. The MDIO drivers must be dis-
`abled when the input current measurement is made.
`
`The input current characteristics for all MII signals shall fall within the limits specified in table 22-10.
`
`Table 10—lnput current limits
`
`Parameter
`
`Condition
`
`Signal(s)
`
`Input High Current
`
`Input Low Current
`
`All except COL,
`VIDC, MD1o*
`
`coLi
`
`VIDCI
`
`\/IDIO§
`**
`
`\/IDIO
`
`All except COL,
`VIDC, MDIO“
`
`COLb
`
`‘VIDCC
`
`MDIO‘!
`
`MDlOe
`
`This is arbeigfigii/@1EfiEE§tanggrg,e,li.,,has been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1025
`
`0081
`
`Aerohive - Exhibit 1025
`
`0081
`
`

`

`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`Table 10—lnput current limits (Continued)
`
`
`
`‘Measured at input of Reconciliation sublayer for CRS, RXD<3:0>, RX_CLK, RX_DV, RX_ER, and TX_CLK. Mea-
`sured at inputs of PHY for TXD<3:0>, TX_EN, and TX_ER.
`lMeasured at input of Reconciliation sublayer.
`iMeasured at input of PHY.
`§l*\/leasured at input of STA.
`Measured at input of PHY, which can be attached via the mechanical interface specified in 22.6.
`
`NOTE—These limits for dc input current allow the use of weak resistive pull-ups or pull-downs on the input of each MH
`signal. They allow the use of weak resistive pull-downs on the signals other than COL, MDC, and MDIO. They allow the
`use of a weak resistive pull-up on the signal COL. They allow the use of a resistive pull-down of 2 k9 i 5% on the MDIO
`signal in the STA. The