IEEE
`Std 802.3, 1993 Edition
`
`22.1.1 Summary of major concepts
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`a)
`
`b)
`
`Each direction of data transfer is serviced with seven (making a total of 14) signals: Data (a four-bit
`bundle), Delimiter, Error, and Clock.
`
`Two media status signals are provided. One indicates the presence of carrier, and the other indicates
`the occurrence of a collision.
`
`c) A management interface comprised of two signals provides access to management parameters and
`services.
`
`d)
`
`The Reconciliation sublayer maps the signal set provided at the M11 to the PLS service definition
`specified in clause 6.
`
`2.1.2 Application
`
`This clause applies to the interface between MAC sublayer and PHYS, and between PHYs and Station Man-
`agement entities. The implementation of the interface may assume any of the following three forms:
`
`a) A chip-to-chip (integrated circuit to integrated circuit) interface implemented with traces on a
`printed circuit board.
`
`b) A motherboard to daughterboard interface between two or more printed circuit boards.
`
`c)
`
`An interface between two printed circuit assemblies that a.1'e attached with a length of cable and an
`appropriate connector.
`
`Figure 22-2 provides an example of the third application environment listed above. All M11 conformance
`tests are performed at the mating surfaces of the M11 connector, identified by the line A-A.
`
`Mll Connector
`
`Figure 22-2—Examp|e application showing location of conformance test
`
`This interface is used to provide media independence for various forms of unshielded twisted-pair wiring,
`shielded twisted-pair wiring, fiber optic cabling, and potentially other media, so that identical media access
`controllers may be used with airy of these media.
`
`To allow for the possibility that multiple PHYs may be controlled by a single Station Ivianagement entity. the
`Mll management interface has provisions to accommodate up to 32 PHYS, with the restriction that a maxi-
`mum of one PHY may be attached to a management interface via the mechanical interface defined in 22.6.
`
`This is angetrchive IEEE Standard.
`
`It has been superseded byoaptagergrggatgpggtutkhigstgyradard.
`
`Aerohive - Exhibit
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`Aerohive - Exhibit 1025
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`0054
`
`

`
`CSMA/CD
`
`22.1.3 Rates of operation
`
`IEEE
`Std 802.3, 1998 Edition
`
`The MII can support two specific data rates, 10 Mb/s and 100 Mb/s. The functionality is identical at both
`data rates, as are the signal timing relationships. The only difference between 10 Mb/s and 100 Mb/s opera-
`tion is the nominal clock frequency.
`
`PHYs that provide an lVlII are not required to support both data rates, and may support either one or both.
`PHYS must report the rates they are capable of operating at via the management interface, as described in
`22.2.4.
`
`22.1.4 Allocation of functions
`
`The allocation of flll1Cl2l01'1S at the MII is such that it readily lends itself to implementation in both PHYS and
`MAC sublayer entities. The division of functions balances the need for media independence with the need
`for a simple and cost-effective interface.
`
`While the Attachment Unit Interface (AUI) was defined to exist between the Physical Signaling (PLS) and
`Physical Media Attachment (PMA) sublayers for 10 Mb/s DTEs, the MH maximizes media independence by
`cleanly separating the Data Link and Physical Layers of the ISO (IEEE) seven-layer reference model. This
`allocation also recognizes that implementations can benefit from a close coupling of the PLS or PCS sub-
`layer and the PMA sublayer.
`
`22.2 Functional specifications
`
`The M11 is designed to make the differences among the various media absolutely transparent to the MAC
`sublayer. The selection of logical control signals and the functional procedures are all designed to this end.
`Additionally, the MII is designed to be easily implemented at minimal cost using conventional design tech-
`niques and manufacturing processes.
`
`22.2.1 Mapping of MII signals to PLS service primitives and Station Management
`
`The Reconciliation sublayer maps the signals provided at the MII to the PLS service primitives defined in
`clause 6. The PLS service primitives provided by the Reconciliation sublayer behave in exactly the same
`manner as defined in clause 6. The MII signals are defined in detail in 22.2.2 below.
`
`Figure 22-3 depicts a schematic view of the Reconciliation sublayer inputs and outputs, and demonstrates
`that the MH management interface is controlled by the Station Management entity (STA).
`
`22.2.1.1 Mapping of PLS_DATA.request
`
`22.2.1.1.1 Function
`
`Map the primitive PLS_DATA request to the MII signals T}G)<3:0>, TX_EN and TX_CLK.
`
`22.2.1.1.2 Semantics of the service primitive
`
`PLS_DATA request (OUTPUT_UNIT)
`
`The OUTPUT_UNIT parameter can take one of three values: ONE, ZERO, or DATA_COMPLETE. It repre-
`sents a single data bit. The values ONE and ZERO are conveyed by the signals TXD<3>, TXD<2>,
`TXD<l> and TXD<0>, each of which conveys one bit of data while TX_EN is asserted. The value
`DATA_COMPLETE is conveyed by the de—assertion of TX_EN. Synchronization between the Reconcilia-
`tion sublayer and the PHY is achieved by way of the TX_CLK signal.
`
`This is arbetgfigii/@1bEfiEE§tanggr,d,e,lt.,,has been superseded by a later version of this standard.
`
`0055
`
`1025
`
`Aerohive - Exhibit 1025
`
`0055
`
`

`
`IEEE
`Std 802.3, 1993 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`PLS Service Primitives
`
`..
`
`.
`
`PLS_DATA.reque5t
`
`PLS_StGNALindicate
`
`PLS_DATA.indicate
`
`PLS_CARR|ER.indicate
`
`Station Management
`
`Mil Signals
`
`TX_ER
`T)(D<3:l]>
`
`“LE”
`T)(_Ct_K
`
`COL
`RXD<3:D>
`
`RX_ER
`Rx_cu<
`
`§’F§§D“'
`
`MDIO
`
`Figure 22-3—Reconciliation Sublayer (RS) inputs and outputs
`and STA connections to MII
`
`22.2.1.1.3 When generated
`
`The TX_C‘LK signal is generated by the PHY. The TXD<3:0> and TX_EN sigials are generated by the Rec-
`onciliation sublayer after every group of four PLS_DATA request transactions from the MAC sublayer to
`request the trasnsmission of four data bits on the physical medium or to stop transmission.
`
`22.2.1.2 Mapping of PLS_DATA.indicate
`
`22.2.1 .2.1 Function
`
`Map the primitive PLS_DATA.ir1dicate to the M11 signals RXD<3:0>_. RX_DV, RX_ER, and RX_CLK.
`
`22.2.1.2.2 Semantics of the service primitive
`
`PLS_DATA.indicate (]INPUT_UN1T)
`
`The ]NPUT_UNIT parameter can take one of two values: ONE or ZERO. It represents a single data bit. The
`values ONE and ZERO are derived from the signals RXD<3>, RXD<2>, RXD<t>, and RXD<0>_. each of
`which represents one bit of data while RX_DV is asserted.
`
`The value of the data transferred to the MAC is controlled by the RX_ER signal, see 22.2.1.5, Response to
`RX_ER indication from MIL
`
`Synchronization between the PHY and the Reconciliation sublayer is achieved by way of the RX_CLK
`signal.
`
`22.2.1.2.3 When generated
`
`This primitive is generated to all MAC sublayer entities in the network after a PLS_DATA.request is issued.
`Each nibble of data transferred on RXD<3 20> will result in the generation of four PLS_DATA.ir1dicate t1'ans-
`actions.
`
`This is amfiirchive IEEE Standard.
`
`it has been superseded by0ap{a§er@;g§§iQgEq{..ti;;_,i%$;9gadard.
`
`Aerohive - Exhibit 1025
`
`0056
`
`

`
`CSMA/CD
`
`22.2.1.3 Mapping of PLS_CARRIER.indicate
`
`22.2.1 .3.1 Function
`
`IEEE
`Std 802.3, 1998 Edition
`
`Map the primitive PLS_CARRIER.indicate to the MH signals CRS and RX_DV.
`
`22.2.1.3.2 Semantics of the service primitive
`
`PLS_CARRIER.indicate (CARRIER_STATUS)
`
`The CARRIER_STATUS parameter can take one of two values: CARRIER_ON or CARRIER_OFF. The
`values CARRIER_ON and CARRIER_OFF are derived from the MII signals CRS and RX_DV.
`
`22.2.1.3.3 When generated
`
`The PLS_CARRIER.indicate service primitive is generated by the Reconciliation sublayer whenever the
`CARRIER_STATUS parameter changes from CARRIER_ON to CARRIER_OFF or vice versa.
`
`While the RX_DV signal is de-asserted, any transition of the CRS signal from de-asserted to asserted must
`cause a transition of CARRIER_STATUS from the CARRIER_OFF to the CARRIER_ON value, and any
`transition of the CRS signal from asserted to de-asserted must cause a transition of CARRIER_STATUS
`from the CARRIER_ON to the CARRIER_OFF value. At any time after CRS and RX_DV are both asserted,
`de-assertion of RX_DV must cause CARRIER_STATUS to transition to the CARRIER_OFF value. This
`transition of CARRIER_STATUS from the CARRIER_ON to the CARRIER_OFF value must be recog-
`nized by the MAC sublayer, even if the CRS signal is still asserted at the time.
`
`NOTE—The behavior of the CRS signal is specified within this clause so that it can be mapped directly (with the appro-
`priate implementation-specific synchronization) to the carriersense variable in the MAC process Deference, which is
`described in 4.2.8. The behavior of the RX_DV signal is specified within this clause so that it can be mapped directly to
`the carriersense variable in the MAC process BitReceiver, which is described in 4.2.9, provided that the MAC process
`BitReceiver is implemented to receive a nibble of data on each cycle through the inner loop.
`
`22.2.1.4 Mapping of PLS_SIGNAL.indicate
`
`22.2.1.4.1 Function
`
`Map the primitive PLS_SIGNAL.indicate to the M11 signal COL.
`
`22.2.1.4.2 Semantics of the service primitive
`
`PLS_SIGNAL.indicate (SIGNAL_STATUS)
`
`SIGNAL_ERROR or
`values:
`two
`of
`one
`take
`can
`parameter
`SIGNAL_STATUS
`The
`NO_SIGNAL_ERROR. SIGNAL_STATUS assumes the value SIGNAL_ERROR when the MII signal COL
`is asserted, and assumes the value NO_SIGNAL_ERROR when COL is de-asserted.
`
`22.2.1.4.3 When generated
`
`The PLS_SIGNAL.indicate service primitive is generated whenever SIGNAL_STATUS makes a transition
`from SIGNAL_ERROR to NO_SIGNAL_ERROR or vice versa.
`
`22.2.1.5 Response to RX_ER indication from Mll
`
`If, during frame reception, both RX_DV and RX_ER are asserted, the Reconciliation sublayer shall ensure
`that the MAC will detect a FrameCheckError in that frame.
`
`This is arbegfigii/@1bEfiEE§tanggrg,e,l1.,.has been superseded by a later version of this standard.
`
`
`
`Aerohive - Exhibit 1025
`
`0057
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`This requirement may be met by incorporating a function in the Reconciliation sublayer that produces a
`result that is guaranteed to be not equal to the CRC result, as specified by the algorithm in 3.2.8, of the
`sequence of nibbles comprising the received flame as delivered to the MAC sublayer. The Reconciliation
`sublayer must then ensure that the result of this function is delivered to the MAC sublayer at the end of the
`received flame in place of the last nibble(s) received flom the MII.
`
`Other techniques may be employed to respond to RX_ER, provided that the result is that the MAC sublayer
`behaves as though a FrameCheckError occurred in the received frame.
`
`22.2.1.6 Conditions for generation of TX_ER
`
`If, during the process of transmitting a frame, it is necessary to request that the PHY deliberately corrupt the
`contents of the frame in such a manner that a receiver will detect the corruption with the highest degree of
`probability, then the signal TX_ER may be generated.
`
`For example, a repeater that detects an RX_ER during flame reception on an input port may propagate that
`error indication to its output ports by asserting TX_ER during the process of transmitting that flame.
`
`Since there is no mechanism in the definition of the MAC sublayer by which the transmit data stream can be
`deliberately corrupted, the Reconciliation sublayer is not required to generate TX_ER.
`
`22.2.2 Mll signal functional specifications
`
`22.2.2.1 TX_CLK (transmit clock)
`
`TX_CLK (Transmit Clock) is a continuous clock that provides the timing reference for the transfer of the
`TX_EN, TXD, and TX_ER signals flom the Reconciliation sublayer to the PHY. TX_CLK is sourced by the
`PHY.
`
`The TX_CLK flequency shall be 25% of the nominal tlansmit data rate :|: 100 ppm. For example, a PHY
`operating at 100 Mb/s must provide a TX_CLK flequency of 25 MHz, and a PHY operating at 10 Mb/s must
`provide a TX_CLK flequency of 2.5 MHz. The duty cycle of the TX_CLK signal shall be between 35% and
`65% inclusive.
`
`NOTE—See additional information in 22.2.4.1.5.
`
`22.2.2.2 RX_CLK (receive clock)
`
`RX_CLK is a continuous clock that provides the timing reference for the transfer of the RX_DV, RXD, and
`RX_ER signals flom the PHY to the Reconciliation sublayer. RX_CLK is sourced by the PHY. The PHY
`may recover the RX_CLK reference from the received data or it may derive the RX_CLK reference from a
`nominal clock (e.g., the TX_CLK reference).
`
`The minimum high and low times of RX_CLK shall be 35% of the nominal period under all conditions.
`
`While RX_DV is asserted, RX_CLK shall be synchronous with recovered data, shall have a frequency equal
`to 25% of the data rate of the received signal, and shall have a duty cycle of between 35% and 65% inclusive.
`
`When the signal received flom the medium is continuous and the PHY can recover the RX_CLK reference
`and supply the RX_CLK on a continuous basis, there is no need to transition between the recovered clock
`reference and a nominal clock reference on a flame-by-flame basis. If loss of received signal flom the
`medium causes a PHY to lose the recovered RX_CLK reference, the PHY shall source the RX_CLK flom a
`nominal clock reference.
`
`This is an4¢\rchive IEEE Standard.
`
`It has been superseded byogplgggrg/g§§iggEg(..ti{§i§,s;agag@rd.
`
`0058
`
`1025
`
`Aerohive - Exhibit 1025
`
`0058
`
`

`
`CSMNCD
`
`IEEE
`Std 302.3, 1993 Edition
`
`Transitions from nominal clock to recovered clock or from recovered clock to nominal clock shall be made
`
`only while RX_DV is de—asserted. During the interval between the assertion of CR3 and the assertion of
`RX_DV at the beginning of a frame, the PHY may extend a cycle of RX_CLK by holding it in either the
`high or low condition until the PHY has successfully locked onto the recovered clock. Following the de-
`assertion of RX_DV' at the end of a frame, the PHY may extend a cycle of RX_CLK by holding it in either
`the high or low condition for an interval that shall not exceed twice the nominal clock period.
`
`NOTE—This standard neither requires nor assumes a guaranteed phase relationship between the RX_CLK and
`TX_CLK signals. See additional infonnation ir1 22.2.4.1.5.
`
`22.2.2.3 TX_EN {transmit enable}
`
`TX_EN indicates that the Reconciliation snblayer is presenting nibbles on the M11 for transmission. It shall
`be asserted by the Reconciliation sublayer synchronously with the first nibble of the preamble and shall
`remain asserted while all nibbles to be transmitted are presented to the M11. TX_EN shall be negated prior to
`the first TX_CLK following the final nibble of a frame. TX_EN is driven by the Reconciliation sublayer and
`shall transition synchronously with respect to the TX_CLK.
`
`Figure 22-4 depicts TX_EN behavior during a frame transmission with no collisions.
`
`TX_EN
`
`/
`
`\
`
`TXD<3:|J>
`
`fl'fi'E"B'm‘B'll'I'fl‘I'I'I'I’I'I‘I
`1
`1
`1
`1
`1
`1
`1
`1 E 1
`1
`1
`1
`1
`1
`1
`1
`
`CRS
`
`COL
`
`Figure 22-4—Transmission with no collision
`
`22.2.2.4 TXD (transmit data)
`
`TXD is a bundle of 4 data signals (TXD<:3:0>) that are driven by the Reconciliation sublayer. TXD<3:0>
`shall transition synchronously with respect to the TX_CLK. For each IX_CLK period in which TX_EN is
`asserted, TXD<3'.0> are accepted for transmission by the PHY. TXD<0 >is the least significant bit. While
`TX_EN is de-asserted, TXD<3:0> shall have no effect upon the PHY.
`
`Figure 22-4 depicts TXD<3:0> behavior during the transmission of a frame.
`
`Table 22-] summarizes the permissible encodings of "IXD<3:0>, TX_EN, and TX_ER.
`
`22.2.2.5 TX_ER {transmit coding error)
`
`TX_ER. shall transition synchronously with respect to the TX_CLK. When TX_ER is asserted for one or
`more TX_CLK periods while TX_EN is also asserted, the PHY shall emit one or more symbols that are not
`
`This is a|'kfi,§fiBlf1@1lE{l:_|&§fiflH§ifil'Q3e,l£.i]aS been superseded by a later version of this stancgrd.
`
`Aerohive - Exhibi
`
`Aerohive - Exhibit 1025
`
`0059
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`Table 22-1—Permissib|e encodings of TXD<3:0>, TX_EN, and TX_ER
`
`
`
`part of the valid data or delimiter set somewhere in the frame being transmitted. The relative position of the
`error within the frame need not be preserved.
`
`Assertion of the TX_ER signal shall not affect the transmission of data when a PHY is operating at 10 Mb/s,
`or when TX_EN is de—asserted.
`
`Figure 22-5 shows the behavior of TX_ER during the transmission of a frame propagating an error.
`
`Table 22-1 summarizes the permissible encodings of TXD<3:0>, TX_EN, and TX_ER.
`
`TX_EN
`
`/
`
`\
`
`TXD<3:0>
`
`B‘B‘E'G'ii|'G'll'E'E'H'I'I'I'I'I'I
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`
`TX_ER
`
`I
`
`\
`
`The TX_ER signal shall be implemented at the M11 of a PHY, may be implemented at the M11 of a repeater
`that provides an MII port, and may be implemented in MAC sublayer devices. If a Reconciliation sublayer
`or a repeater with an MII port does not actively drive the TX_ER signal, it shall ensure that the TX_ER sig-
`nal is pulled down to an inactive state at all times.
`
`22.2.2.6 RX_DV (Receive Data Valid)
`
`RX_DV (Receive Data Valid) is driven by the PHY to indicate that the PHY is presenting recovered and
`decoded nibbles on the RXD<3:0> bundle and that the data on RXD<3:O> is synchronous to RX_CLK.
`RX_DV shall transition synchronously with respect to the RX_CLK. RX_DV shall remain asserted continu-
`ously from the first recovered nibble of the frame through the final recovered nibble and shall be negated
`prior to the first RX_CLK that follows the final nibble. In order for a received frame to be correctly inter-
`preted by the Reconciliation sublayer and the MAC sublayer, RX_DV must encompass the frame, starting
`no later than the Start Frame Delirniter (SFD) and excluding any End-of-Frame delimiter.
`
`Figure 22-6 shows the behavior of RX_DV during frame reception.
`
`This is an44\rchive IEEE Standard.
`
`It has been superseded byogplagerg/g§§iggEg(..ti{gs$s;agagard.
`
`
`
`Aerohive - Exhibit 1025
`
`0060
`
`

`
`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`RX_DV
`
`[
`
`\
`
`RXD<3:0>
`
`RXER
`
`riiliilfilfilfllfllflldillilJIEIIIIEIIIIEIJ
`
`
`
`LGGBIVE lalal
`
`RXD is a bundle of four data signals (RXD<3:0>) that transition synchronously with respect to the RX_CLK.
`RXD<3:0> are driven by the PHY. For each RX_CLK period in which RX_DV is asserted, RXD<3 :0> transfer
`four bits of recovered data firom the PHY to the Reconciliation sublayer. RXD<0> is the least significant bit.
`While RX_DV is de—asser1ed, RXD<3:0> shall have no efl‘ect on the Reconciliation sublayer.
`
`While RX_DV is de-asserted, the PHY may provide a False Carrier indication by asserting the RX_ER sig-
`nal while driving the value <1 1 10> onto RXD<3:0>. See 24.2.4.4.2 for a description of the conditions under
`which a PHY will provide a False Carrier indication.
`
`In order for a frame to be correctly interpreted by the MAC sublayer, a completely formed SFD must be
`passed across the M11. A PHY is not required to loop data transmitted on TXD<3:0> back to RXD<3:0>
`unless the loopback mode of operation is selected as defined in 22.2.4.l.2.
`
`Figure 22-6 shows the behavior of RXD<3:0> during frame reception.
`
`Table 22-2 summarizes the permissible encoding of RXD<3:0>, RX_ER, and RX_DV, along with the spe-
`cific indication provided by each code.
`
`Table 2—Permissible encoding of RXD<3:0>, RX_ER, and RX_DV
`
`
`
`This is arbeigfigii/@1EfiEE§tanggrg,e,lt,‘has been superseded by a later version of this standard.
`
`t 1025
`
`
`
`0061
`
`Aerohive - Exhibit 1025
`
`0061
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`22.2.2.8 R)(_ER {receive error)
`
`LOCAL AND METROPOUTAN AREA NETWORKS:
`
`RX_ER (Receive Error) is driven by the PHY. RX_ER shall be asserted for one or more RX_CLK periods to
`indicate to the Reconciliation sublayer that an error (e.g., a coding error, or any error that the PHY is capable
`of detecting, and that may otherwise be undetectable at the MAC sublayer) was detected somewhere in the
`frame presently being transferred from the PHY to the Reconciliation sublayer. RX_ER shall transition syn-
`chronously with respect to RX_CLK. While RX_DV is de-asserted, RX_ER shall have no effect on the Rec-
`onciliation sublayer.
`
`While RX_DV is de-asserted, the PHY may provide a False Carrier indication by asserting the RX_ER sig-
`nal for at least one cycle of the RX_CLK while driving the appropriate value onto RXD<3:0>, as defined i.n
`22.2 2.7. See 24.2.4.4.2 for a description of the conditions under which a PHY will provide a False Carrier
`indication.
`
`The effect of RX_ER on the Reconciliation sublayer is defined in 22.2.1.5, Response to RX_ER indication
`from MII.
`
`Figure 22-? shows the behavior of RX_ER during the reception of a frame with errors.
`
`Figure 22-7—Reception with errors
`
`Figure 22-8 shows the behavior of RX_ER, RX_DV and RXD<:3 :O> during a False Carrier indication.
`
`RXEN
`
`Rxn-«an»
`
`rrvrrrvvrrrrrrr
`...E.@.@..€*33.@i&3m@.MERE
`
`Figure 22-8—Fa|se Carrier indication
`
`This is amgirchive IEEE Standard.
`
`It has been superseded by0gp{a§er@igi§§iQigoEq{..t.h_,i§5$;§m;i§ird.
`
`Aerohive - Exhibi
`
`Aerohive - Exhibit 1025
`
`0062
`
`

`
`CSMNCD
`
`22.2.2.9 CR8 {carrier sense)
`
`IEEE
`Std 302.3, 1993 Edition
`
`CRS shall be asserted by the PHY when either the transmit or receive medium is nonidle. CRS shall be de-
`asserted by the PHY when both the transmit and receive media are idle. The PHY shall ensure that CRS
`remai.ns asserted throughout the duration of a collision condition.
`
`CRS is not required to transition synchronously with respect to either the TX_CLK or the RX_CLK.
`
`The behavior of the CRS signal is unspecified when the duplex inode bit 0.8 in the control register is set to a
`logic one, as described in 22.2.4.l.8, or when the Auto—Negotiation process selects a full duplex mode of
`operation.
`
`Figure 22-4 shows the behavior of CR8 during a flame transmission without a collision, while Figure 22-9
`shows the behavior of CR8 during a frame transmission with a collision.
`
`22.22.10 COL {collision detected}
`
`COL shall be asseited by the PHY upon detection of a collision on the medium, and shall remain asserted
`while the collision condition persists.
`
`COL shall be asserted by a PHY that is operating at 10 Mb/s in response to a sr'gnr:F_qualirfv_e17'or message
`from the PMA.
`
`COL is not required to transition synchronously with respect to either the TX_CLK or the RX_CLK.
`
`The behavior of the COL signal is unspecified when the duplex mode bit 0.8 in the control register is set to a
`logic one, as described in 22.2.4.l.8, or when the Auto-Negotiation process selects a full-duplex mode of
`operation.
`
`Figure 22-9 shows the behavior of COL during a frame transmission with a collision.
`
`TXEN
`
`/
`
`N
`
`I
`I
`I
`I
`I
`I
`'l'
`I
`I
`I
`I
`.e.e.e.n.m.e.n.e....min
`
`CR3
`
`COL
`
`Figure 22-9—Transmission with collision
`
`NOTE—The ci.rcuit assembly that contains the Reconciliation snblayer may incorporate a weak pull-up on the COL sig-
`nal as a means of detecting an open circuit condition on the COL signal at the MIL The limit on the value of this pull-up
`is defined in 22.4.4.2.
`
`This is a|'kfi,§fiBlfu@1lE¢i:_|&§fifl|'-E1-fil'.g3e,l;L.;l]aS been superseded by a later version of this stanmrd.
`
`Aerohive - Exhibi
`
`Aerohive - Exhibit 1025
`
`0063
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`22.2.2.11 MDC (management data clock)
`
`MDC is sourced by the Station Management entity to the PHY as the timing reference for transfer of infor-
`mation on the MDIO signal. MDC is an aperiodic signal that has no maximum high or low times. The mini-
`mum high and low times for MDC shall be 160 ns each, and the minimum period for MDC shall be 400 ns,
`regardless of the nominal period of TX_CLK and RX_CLK.
`
`22.2.2.12 MDIO (management data inputloutput)
`
`MDIO is a bidirectional signal between the PHY and the STA. It is used to transfer control information and
`status between the PHY and the STA. Control information is driven by the STA synchronously with respect
`to MDC and is sampled synchronously by the PHY. Status information is driven by the PHY synchronously
`with respect to MDC and is sampled synchronously by the STA.
`
`MDIO shall be driven through three-state circuits that enable either the STA or the PHY to drive the signal.
`A PHY that is attached to the M11 via the mechanical interface specified in 22.6 shall provide a resistive pull-
`up to maintain the signal in a high state. The STA shall incorporate a resistive pull-down on the MDIO signal
`and thus may use the quiescent state of MDIO to determine if a PHY is connected to the MH via the
`mechanical interface defined in 22.6. The limits on the values ofthese pull-ups and pull-downs are defined in
`22.4.4.2.
`
`22.2.3 Frame structure
`
`Data frames transmitted through the MII shall have the frame format shown in figure 22-10.
`
`<inter-frame><preamb|e><sfd><data><efd>
`
`For the MII, transmission and reception of each octet of data shall be done a nibble at a time with the order
`of nibble transmission and reception as shown in figure 22-1 1.
`
`First Bit
`
`|_sB
`
`MAC’s Serial Bit Stream
`
`
`
`MSB
`
`ZZZ Second
`N ibble
`
`LSB
`
`M II
`N ibble
`Stream
`
`This is an4Archive IEEE Standard.
`
`It has been superseded byoapiggerg/g§§iggEg(..l;i;i§$$;agagard.
`
`0064
`
`1025
`
`Aerohive - Exhibit 1025
`
`0064
`
`

`
`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`The bits of each octet are transmitted and received as two nibbles, bits 0 through 3 of the octet corresponding
`to bits 0 through 3 of the first nibble transmitted or received, and bits 4 through 7 of the octet corresponding
`to bits 0 through 3 of the second nibble transmitted or received.
`
`22.2.3.1 Inter-frame
`
`The inter-fi'arne period provides an observation window for an unspecified amount of time during which no
`data activity occurs on the MII. The absence of data activity is indicated by the de-assertion of the RX_DV
`signal on the receive path, and the de-assertion of the TX_EN signal on the transmit path. The MAC inter-
`Framespacing parameter defined in clause 4 is measured from the de-assertion of the CRS signal to the
`assertion of the CRS signal.
`
`22.2.3.2 Preamble and start of frame delimiter
`
`22.2.3.2.1 Transmit case
`
`The preamble <preamble> begins a flame transmission. The bit value of the preamble field at the M11 is
`unchanged from that specified in 7.2.3.2 and shall consist of 7 octets with the following bit values:
`
`10101010101010101010101010101010101010101010101010101010
`
`In the preceding example, the preamble is displayed using the bit order it would have if transmitted serially.
`This means that for each octet the leftmost 1 value represents the LSB of the octet, and the rightmost 0 value
`the octet MSB.
`
`The SFD (Start Frame Delimiter) <sfd> indicates the start of a frame and follows the preamble. The bit value
`of the SFD at the MII is unchanged from that specified in 7.2.3.3 and is the bit sequence:
`
`10101011
`
`The preamble and SFD shall be transmitted through the MII as nibbles starting fiom the assertion of TX_EN
`as shown in table 22-3.
`
`Table 3—Transmitted preamble and SFD
`
`
`
`* 1 st preamble nibble transmitted.
`llst SFD nibb1e transmitted.
`11st data nibble transmitted.
`§D0 through D7 are the first eight bits of the data field from the Protocol Data Unit (PDU).
`
`22.2.3.2.2 Receive case
`
`The conditions for assertion of RX_DV are defined in 22.2.2.6.
`
`This is arbermgiii/@1E,fiEE.§tan§i,gr,g,e,li,§]as been superseded by a later version of this standard.
`
`
`
`Aerohive - Exhibit 1025
`
`0065
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`The alignment of the received SFD and data at the MII shall be as shown in table 22-4 and table 22-5.
`Table 22-4 depicts the case where no preamble nibbles are conveyed across the MII, and table 22-5 depicts
`the case where the entire preamble is conveyed across the MII.
`
`Table 4—Start of receive with no preamble preceding SFD
`
`
`
`*1st SFD nibble received.
`ll st data nibble received.
`ID0 through D7 are the first eight bits of the data field from the PDU.
`
`Table 5—Start of receive with entire preamble preceding SFD
`
`Signal
`
`Bit values of nibbles received through MII
`
`* 1 st preamble nibble received.
`‘fist SFD nibble received.
`11st data nibble received.
`§D0 through D7 are the first eight bits of the data field from the PDU.
`
`22.2.3.3 Data
`
`The data in a well formed frame shall consist of N octets of data transmitted as 2N nibbles. For each octet of
`
`data the transmit order of each nibble is as specified in figure 22-1 1. Data in a collision fragment may consist
`of an odd number of nibbles.
`
`22.2.3.4 End-of-Frame delimiter (EFD)
`
`De-assertion of the TX_EN signal constitutes an End-of-Frame delimiter for data conveyed on TXD<3:0>,
`and de-assertion of RX_DV constitutes an End-of-Frame delimiter for data conveyed on RXD<3:0>.
`
`22.2.3.5 Handling of excess nibbles
`
`An excess nibble condition occurs when an odd number of nibbles is conveyed across the M11 beginning
`with the SFD and including all nibbles conveyed until the End-of-Frame delimiter. Reception of a frame
`containing a non-integer number of octets shall be indicated by the PHY as an excess nibble condition.
`
`This is an5Archive IEEE Standard.
`
`It has been superseded byogplgggrg/g§§iggEg(..tl{§is$s;agagard.
`
`
`
`Aerohive - Exhibit 1025
`
`0066
`
`

`
`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`Transmission of an excess nibble may be handled by the PHY in an imp1ementation—specific manner. No
`assumption should be made with regard to truncation, octet padding, or exact nibble transmission by the
`PHY.
`
`22.2.4 Management functions
`
`The management interface specified here provides a simple, two-wire, serial interface to connect a mar1age-
`ment entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY.
`This interface is referred to as the MII Management Interface.
`
`The management interface consists of a pair of signals that physically transport the management information
`across the MII, a frame format and a protocol specification for exchanging management frames, and a regis-
`ter set that can be read and written using these frames. The register definition specifies a basic register set
`with an extension mechanism.
`
`The basic register set consists of two registers referred to as the Control Register (register 0) and the Status
`Register (register 1). The status and control functions defined here are considered basic and firndamental to
`100 Mb/s PHYs. All PHYs that provide an MII shall incorporate the basic register set. Registers 2 through 7
`are part of the extended register set.
`
`The full set of management registers is listed in table 22-6.
`
`Table 6—M|| management register set
`
`
`
`This is arbegfigii/@1EfiEE§tanggrg,e,li.flhas been superseded by a later version of this standard.
`
`0067
`
`it 1025
`
`Aerohive - Exhibit 1025
`
`0067
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`22.2.4.1 Control register (register 0)
`
`The assignment of bits in the Control Register is shown in table 22-7 below. The default value for each bit of
`the Control Register should be chosen so that the initial state of the PHY upon power up or reset is a normal
`operational state without management intervention.
`
`Table 7—Control register bit definitions
`
`Reset
`
`Loopback
`
`Description
`
`1 = PHY reset
`0 = normal operation
`
`1 = enable loopback mode
`0 = disable loopback mode
`
`Speed Selection
`
`1 = 100 Mb/s
`0 = 10 Mb/s
`
`Auto-Negotiation Enable
`
`1 = Enable Auto-Negotiation Process
`0 = Disable Auto-Negotiation Process
`
`Power Down
`
`Isolate
`
`Restart Auto-Negotiation
`
`Duplex Mode
`
`Collision Test
`
`1 = power down
`0 = normal operationl
`
`1 = electrically Isolate PHY from M11
`0 = normal operationb
`
`1 = Restart Auto-Negotiation Process
`0 = normal operation
`
`1 = Full Duplex:
`0 = Half Duplex
`
`1 = enable COL signal test
`0 = disable COL signal test
`
`Reserved
`
`Write as 0, ignore on Read
`
`‘R/w = Read/Write, sc = Self-Clearing.
`TFor normal operation, both 0.10 and 0.11 must be cleared to zero, see 22.2.4.1.5.
`Ispecifications for full-duplex mode operation are plarmed for future work.
`
`22.2.4.1.1 Reset
`
`Resetting a PHY is accomplished by setting bit 0.15 to a logic one. This action shall set the status and con-
`trol registers to their default states. As a consequence this action may change the internal state of the PHY
`and the state of the physical link associated with the PHY. This bit is self-clearing, and a PHY shall return a
`value of one in hit 0.15 until the reset process is completed. A PHY is not required to accept a write transac-
`tion to the control register until the reset process is completed, and writes to bits of the control register other
`than 0.15 may have no efl'ect until the reset process is completed. The reset process shall be completed
`within 0.5 s from the setting of bit 0.15.
`
`The default value of bit 0.15 is zero.
`
`NOTE—This operation may interrupt data communication.
`
`This is an5¢\rchive IEEE Standard.
`
`It has been superseded byogpigggrg/g§§iggEg(..l;i;is$s;agag@rd.
`