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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`EXPERT DECLARATION OF DR. GODMAR BACK IN SUPPORT OF
`THE PATENT OWNER’S RESPONSE
`
`APPLE, INC.,
`Petitioner
`
`v.
`
`REALTIME DATA LLC,
`Patent Owner
`
`____________________
`
`
`
` Case IPR2016-01739
`Patent 8,880,862
`
`____________________
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`TABLE OF CONTENTS
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`
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`I.  
`
`INTRODUCTION .......................................................................................... 1  
`
`A.   Summary of Issues ........................................................................................... 1  
`
`B.   Summary of Opinions ...................................................................................... 2  
`
`II.  
`
`PROFESSIONAL BACKGROUND .............................................................. 3  
`
`III.   TECHNOLOGY OVERVIEW ....................................................................... 7  
`
`A.   ‘862 Patent ....................................................................................................... 7  
`
`B.   Settsu Reference ............................................................................................ 10  
`
`C.   Zwiegincew Reference .................................................................................. 11  
`
`D.   Dye Reference ................................................................................................ 15  
`
`IV.   LEGAL STANDARDS TO BE APPLIED .................................................. 16  
`
`V.  
`
`PERSON OF ORDINARY SKILL IN THE ART ....................................... 19  
`
`VI.   CLAIM CONSTRUCTION ......................................................................... 21  
`
`A.   Term “Boot Data List” ................................................................................... 21  
`
`B.   Term “Non-Accessed Boot Data” .................................................................. 26  
`
`C.   Apple’s Proposed Construction of “Boot Data” ............................................ 29  
`
`VII.   VALIDITY OF THE ‘862 PATENT ............................................................ 30  
`
`A.   Settsu Does Not Render Obvious the Claimed “Updating the Boot Data
`List.” .............................................................................................................. 30  
`
`B.   Zwiegincew’s Teachings Do Not Provide a Basis to Modify Settsu to Render
`Obvious the Claimed “Updating the Boot Data List.” ................................... 36  
`
`C.   Settsu in view of Zwiegencew Does Not Teach or Suggest “Disassociating
`Non-Accessed Boot Data from the Boot Data List.” ..................................... 41  
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`D.   Settsu in view of Zwiegincew Does Not Render Obvious “Updating the Boot
`Data List in Response to the Utilizing.” ........................................................ 45  
`
`E.   Neither Dye Nor Zwiegincew Discloses “a Plurality of Encoders.” ............. 48  
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`I, Godmar Back, declare as follows:
`
`I.  
`
`INTRODUCTION
`
`
`
`1.   My name is Dr. Godmar Back. I have been retained by Realtime Data
`
`LLC to offer my opinions concerning the validity of U.S Patent No. 8,880,862
`
`(“the ‘862 Patent”).
`
`2.  
`
`Specifically, I have been asked to analyze arguments made by Apple,
`
`Inc. and its expert, Dr. Charles J. Neuhauser, in the petition for inter partes review
`
`(“IPR”) proceeding of the ‘862 Patent, Case No. IPR2016-01739. I understand that
`
`on March 20, 2017, the Patent Trial and Appeal Board (“the Board”) entered a
`
`decision instituting (“the Institution Decision”) this IPR proceeding.
`
`A.  
`
`3.  
`
`Summary of Issues
`
`I understand that Apple’s Petition (and Dr. Neuhauser’s Declaration)
`
`alleges the following five grounds of unpatentability:
`
`a.   Ground 1: claims 5, 35-46, and 97 of the ‘862 Patent are obvious
`over U.S. Patent No. 6,374,353 (“Settsu”);
`b.   Ground 2: claims 5, 35-46, 97, 98 and 112 of the ‘862 Patent are
`obvious over the combination of Settsu in view of U.S. Patent No.
`6,317,818 (“Zwiegincew”);
`c.   Ground 3: claims 5, 35-46, 97 of the ‘862 Patent are obvious over
`the combination of Settsu in view of U.S. Patent No. 6,145,069
`(“Dye”); and
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`d.   Ground 4: claims 5, 35-46, 97, 98 and 112 of the ‘862 Patent are
`obvious over the combination of Settsu in view of Zwiegincew and
`Dye.
`
`4.  
`
`I understand that in its Institution Decision, the Board instituted IPR
`
`on Ground 1 (Settsu) for claims 5, 35-46, and 97. I also understand that the Board
`
`instituted IPR on Ground 2 (Settsu in view of Zwiegincew) for claims 5, 35-46, 97,
`
`98 and 112. Further, I understand that the Board instituted IPR on Ground 3 (Settsu
`
`in view of Dye) for claims 5, 35-46, and 97. Lastly, I understand that the Board
`
`instituted IPR on Ground 4 (Settsu in view of Zwiegincew and Dye) for claims 5,
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`35-46, 97, 98 and 112.
`
`5.  
`
`In forming my opinions, I have reviewed the ‘862 Patent, its file
`
`history, priority application 60/180,114 listed on the cover of the ‘862 Patent, Dr.
`
`Neuhauser’s declaration (“the Neuhauser Declaration”), Apple’s Petition for Inter
`
`Partes Review, the references on which Apple’s Petition and Dr. Neuhauser rely,
`
`Realtime’s Preliminary Response,
`
`the Institution Decision, and materials
`
`referenced herein.
`
`6.   My opinions are based on my experience and knowledge of the
`
`relevant art, as well as the documents discussed in this declaration.
`
`B.  
`
`7.  
`
`Summary of Opinions
`
`As explained in detail below, it is my opinion that each of claims 5,
`
`35-46, 97, 98, and 112 of the ‘862 Patent are not obvious over:
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`a.   Settsu;
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`b.   Settsu in view of Zwiegincew;
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`c.   Settsu in view of Dye; and
`
`d.   Settsu in view of Zwiegincew and Dye.
`
`
`
`8.  
`
`Specifically, Settsu, alone or in view of Zwiegincew and/or Dye, does
`
`not render obvious “updating the boot data list,” as required by claims 5, 35-46, 97,
`
`98, and 112. Also, Settsu in view of Zwiegincew and/or Dye does not render
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`obvious the “updating” step including “disassociating non-accessed boot data from
`
`the boot data list,” as required by claim 98. Further, Settsu in view of Zwiegincew
`
`and/or Dye does not render obvious the “updating” step including “updating the
`
`boot data list in response to the utilizing,” as required by claim 112. Lastly, Dye
`
`does not disclose “a plurality of encoders,” as required by claim 46. As such, it is
`
`my opinion that the challenged claims are not obvious as alleged by Apple and Dr.
`
`Neuhauser.
`
`II.  
`
`PROFESSIONAL BACKGROUND
`
`9.  
`
`I have been working in the field of computer science for over 25
`
`years. My areas of expertise include computer systems, operating systems, and
`
`kernels. My experience includes, as a few examples, research, publications,
`
`lectures, and workshops in the field of computer systems, operating systems, and
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`kernels. My Curriculum Vitae is attached hereto (Exhibit 2009).
`
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`10.  
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`I obtained my undergraduate degree in Mathematics and Computer
`
`Science from Humboldt University of Berlin in 1992, and I studied Computer
`
`Science at the Technical University of Berlin from 1992-1994.
`
`11.   From September 1994 to May 1995, I was a Teaching Assistant in the
`
`Department of Computer Science at University of Utah, where I co-taught senior-
`
`level undergraduate courses and entry-level graduate courses in operating systems,
`
`networking, and compilers.
`
`12.   From June 1995 to November 2001, I was a Research Assistant in the
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`Computer Systems Laboratory at University of Utah, where I conducted research
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`on component-based operating systems (OSKit) and microkernel systems (Fluke).
`
`My research was published at the Second Symposium on Operating Systems
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`Design and Implementation (OSDI) in 1996 and at the 16th ACM Symposium on
`
`Operating Systems Principles (SOSP) in 1997. Also during this time period, I
`
`conducted my dissertation research on runtime systems that support multiple
`
`applications. My research was published at the Seventh Workshop on Hot Topics
`
`in Operating Systems (HotOS) in 1999, at the Fourth Symposium on Operating
`
`Systems Design and Implementation (OSDI) in 2000, and at the USENIX 2000
`
`Annual Technical Conference in 2000. I also received travel scholarship awards
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`from Usenix, ACM, and the IEEE for various conferences such as these.
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`13.  
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`In May 2002, I received my Ph.D. in Computer Science from the
`
`University of Utah. I wrote my dissertation on the topic, “Isolation, Resource
`
`Management and Sharing in the KaffeOS Java Runtime System,” which went on to
`
`win the 2003 ACM SIGPLAN Doctoral Dissertation Award.
`
`14.   Between November 2001 and June 2004, I was a Postdoctoral Scholar
`
`in the Computer Systems Laboratory at Stanford University. During my time at
`
`Stanford, I researched static analysis tools. As part of my research, I developed the
`
`MJ system for checking properties and implementing bug-finding analyses in Java
`
`code. I also worked on the design and implementation of DataScript, an input
`
`description language that supports code generation. I published my work on this
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`language at the ACM Conference on Generative Programming and Component
`
`Engineering Proceedings (GPCE) in 2002. I also taught courses on “Introduction to
`
`Compilers” during my time at Stanford.
`
`15.  
`
`In August 2004, I was appointed as Assistant Professor in the
`
`Department of Computer Science at Virginia Tech. In June 2010, I was promoted
`
`to Associate Professor, the position I currently hold. Between 2004 and 2015, I
`
`taught both graduate and undergraduate courses in “Operating Systems.” I have
`
`also taught undergraduate courses such as “Computer Systems,” “Introduction to
`
`Software Design,” “Systems and Networking Capstone,” and “Cloud Software
`
`Engineering,” and graduate courses such as “Advanced Topics in Program
`
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`Analysis,” “Network Architectures and Protocols,” and “Execution Environments
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`
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`for Cloud Applications.” My current research interests include: operating and
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`runtime systems, virtualization, software engineering, software visualization, web
`
`technology, cloud-based systems, high-performance computing, domain-specific
`
`languages, and library technology.
`
`16.   Throughout my career, I have been an external reviewer for several
`
`professional publications and organizations, including the Journal of Parallel and
`
`Distributed Computing; the Journal of STEM Education; National Science
`
`Foundation; IEEE Transactions on Parallel and Distributed Systems; the Journal of
`
`Simulation Modelling Practice and Theory; IEEE Computer; ASEE Southeast
`
`conference; Proceedings of the IEEE; ACM Transactions on Programming
`
`Languages; the Journal of the ACM; Software Practice and Experience;
`
`Transactions on Information Systems (TOIS); USENIX; the Journal of Systems
`
`and Software; ICCD; SOSP; OSDI; PACT; ECOOP; EUROPAR; and the
`
`Informatik Forum Journal.
`
`17.  
`
`I have also held
`
`leadership positions at several professional
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`conferences and workshops. For instance, I have been the Program Co-Chair for
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`the Operating Systems track at ICCD; a Program Committee Member for the
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`International Conference on Parallel Processing (ICPP); a Program Committee
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`Member of the International Workshop on Programming Support Innovations for
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`Emerging Distributed Applications; and a Program Committee Member for the
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`SPLASH/Wavefront conference.
`
`18.  
`
`I have published 21 conference papers, nine journal articles, chapters
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`in 2 books, and 11 workshop papers. Many of my works relate to computer
`
`systems, operating systems, and kernels.
`
`19.   My compensation is not dependent on the outcome of this case, and I
`
`have no financial interest in the outcome.
`
`III.   TECHNOLOGY OVERVIEW
`
`A.  
`
`‘862 Patent
`
`20.   The ‘862 Patent is generally directed to systems and methods for
`
`providing accelerated loading of operating systems and application programs in a
`
`computer system.1
`
`21.   One method of increasing computer performance at the time of
`
`invention was the use of onboard memory and onboard caches. These onboard
`
`memories and caches are faster than the common-place magnetic HDD’s and thus
`
`allow host systems to quickly access necessary data.2 Thus, data is temporarily
`
`stored in a cache or other high-speed memory, and host systems do not have to
`
`wait for relatively slow hard drives to retrieve the needed data.
`
`1 Ex. 1001, ‘862 Patent at 1:20-26.
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`2 E.g., Ex. 1001, ‘862 Patent at 1:29-31, 20:36-49.
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`22.   Computers at the time of the invention suffered from slow boot times,
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`even with high-speed onboard memories and caches.3 One reason for this is that
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`upon reset, conventional boot device controllers of the time would wait for a
`
`command before loading data for processing.4 Since boot device controllers are
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`typically reset along with the host system, the time spent by the boot device
`
`controller waiting for commands is unproductive.5 Also, once the CPU is
`
`initialized and issues commands requesting data to the boot device controller, time
`
`is wasted while the CPU waits for the boot device controller to carry out the CPU’s
`
`command and provide the requested information. All this wasted time results in
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`delay experienced by the user. Traditional high-speed memories of the time were
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`also volatile memories, the contents of which are erased upon power reset.6
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`Therefore, storing desired information, such as boot information, ahead of time
`
`was not possible.
`
`23.   To address these problems, the ‘862 Patent discloses and claims
`
`methods and systems for loading compressed boot data associated with a boot data
`
`3 E.g., Ex. 1001, ‘862 Patent at 20:45-49.
`
`4 Ex. 1001, ‘862 Patent at 20:38-49.
`
`5 Ex. 1001, ‘862 Patent at 20:38-49.
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`6 E.g., Ex. 1003, Neuhauser Dec. at ¶ 44 (recognizing that flash memory based
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`designs were expensive on a per bit basis at the time of invention).
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`list, and updating the boot data list. Specifically, the claims of the ‘862 are directed
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`
`
`to, among other things, maintaining a list of boot data, loading boot data in
`
`compressed form (based on the list) from a memory into a cache memory,
`
`accessing the loaded boot data, and decompressing the boot data at a rate that
`
`decreases boot time of the operating system relative to loading the operating
`
`system with uncompressed boot data.7
`
`24.   Another aspect of the inventions of the ‘862 Patent is updating the list
`
`of boot data during the boot process by adding to the list any boot data requested
`
`by the computer which was not previously stored in the list, as well as removing
`
`from the list any boot data previously stored in the list but not requested by the
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`CPU.8 The ‘862 Patent’s system also includes a processor configured to load
`
`compressed boot data associated with a boot data list into memory, to access the
`
`loaded boot data, to decompress the access portion of boot data, and to update the
`
`boot data list.9 These systems and methods result in a faster bootup of computer
`
`systems.
`
`
`7 Ex. 1001, ‘862 Patent at 3:34-52, 27:42-60, 28:9-25, 29:15-32, 30:4-26.
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`8 Ex. 1001, ‘862 Patent at 3:53-58, 28:1-8.
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`9 Ex. 1001, ‘862 Patent at 4:4-20.
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`B.  
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`Settsu Reference
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`
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`25.   Settsu is directed to “[a] method of booting up an information
`
`processing apparatus.”10 In addition, Settsu discloses a process for booting up a
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`system that comprises a boot device divided into a mini-operating system (“OS”)
`
`module and an OS main body wherein modules of the OS main body may be
`
`stored as compressed files.11
`
`26.  
`
`In Settsu’s system, certain application programs that need only a
`
`subset of the OS’s functionality can be started after loading only a subset of
`
`functional modules, thus speeding up boot times for this special case.12
`
`27.   As depicted in Settsu Figure 3, reproduced below, the “virtual
`
`memory processing module” is part of the OS main body module. Thus, Settsu’s
`
`system cannot perform virtual memory management until the OS main body
`
`module is loaded and the virtual memory processing module is initialized.
`
`
`10 Ex. 1006, Settsu at Abs.
`
`11 Ex. 1006, Settsu at Abs., 1:51-65, 3:6-12.
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`12 E.g., Ex. 1006, Settsu at Abs., 1:51-65, 7:66-9:3.
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`28.   Apple and Dr. Neuhauser contend that Settsu renders obvious
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`“updating the boot data list.”13 I disagree, as I will explain. I will also explain that
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`that Zwiegincew does not render this limitation obvious, either. Apple does not
`
`contend that Dye discloses this limitation. Apple also does not contend that Settsu
`
`discloses “wherein the updating comprises updating in response to the utilizing” or
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`“wherein the updating comprises disassociating non-accessed boot data.”
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`C.   Zwiegincew Reference
`
`29.   Zwiegincew is directed at the management of program code and data
`
`pages of application program modules during hard page fault intensive scenarios
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`with the aim of improving performance. To understand hard page faults, it is
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`13 E.g., Petition at [INSERT].
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`helpful to understand virtual memory and paging in the context of modern
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`
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`computer systems.
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`30.   Virtual memory is a memory management technique that uses both
`
`hardware and software. When using virtual memory, program code utilizes virtual
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`addresses that are mapped to the physical locations of the data in RAM. The blocks
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`of data that are mapped in this way are known as pages.
`
`31.   When a user or the system starts a new process, modern operating
`
`systems do not load the process’s program code into RAM all at once. Especially
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`when a program is large, not all parts of the program may be needed, and loading
`
`them upfront would waste time and memory. Instead, these systems use a method
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`called “on-demand paging,” where parts of a program are not loaded until the
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`process running the program actually tries to execute them. If and when this
`
`happens, the OS recognizes which part of the program is requested, loads it from
`
`disk into memory, and resumes the process. This memory management process is
`
`performed by the OS’s virtual memory management module, commonly referred to
`
`as “virtual memory manager.” The virtual memory manager keeps track of which
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`virtual addresses have been loaded to RAM and which ones have not. For virtual
`
`addresses that have been loaded to RAM, the virtual memory manager instructs the
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`CPU’s memory management unit (MMU) where to find the physical address of the
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`page in RAM.
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`32.   A hard page fault occurs when a process references a page in its
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`virtual address space that has not been loaded to RAM. In this situation, the
`
`process is interrupted while the page is retrieved from the hard disk and loaded to
`
`RAM. The virtual memory manager updates its tables to indicate that the requested
`
`page is now available in RAM and identifies the location of that page in RAM. The
`
`process can then resume and utilize the page. Because handling a hard page fault
`
`requires accessing the hard disk which is much slower than RAM, these hard page
`
`faults slow down the process. If the OS knew which pages the program was likely
`
`to access, it could prefetch those pages into memory. Then, if the program
`
`accesses them, they are available when needed, thereby avoiding a “hard page
`
`fault.”
`
`33.   To reduce the occurrence of hard page faults, Zwiegincew discloses
`
`that a “scenario file” may pre-fetch pages of application programs prior to the
`
`occurrence of a hard page fault sequence.14 In other words, Zwiegincew proposes
`
`to prevent hard page faults from occurring through the use of these “scenario
`
`files.”
`
`34.   Zwiegincew’s “scenario file” is a file that identifies characteristics,
`
`markers, or other indicators that a hard page fault is likely to occur—a so-called
`
`
`14 Ex. 1010, Zwiegincew at 4:6-19.
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`“page fault scenario.”15 The scenario file can also include a copy or identification
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`
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`of the page file that is needed to avoid the impending hard page fault.16 The
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`system is monitored based on the information in the scenario file and when a hard
`
`page fault scenario is detected and thus a hard page fault is likely to occur, the
`
`system can load the page identified by the scenario file.17 Thus, the scenario file
`
`anticipates and prevents hard page faults, thereby increasing system speed.18
`
`35.   Zwiegincew further discloses the idea of automatically refining the
`
`scenario file so it can more accurately identify hard page fault scenarios.19
`
`Zwiegincew also discloses a mode in which hard page faults are recorded in a log,
`
`thus allowing a subsequent pattern-based algorithm to analyze this log to refine the
`
`page fault markers and indicators in the scenario file to better predict the
`
`occurrence of page faults.20
`
`36.   Apple contends that Zwiegincew in combination with Settsu (or in
`
`combination with Settsu and Dye) renders obvious “updating the boot data list,”
`
`15 Ex. 1010, Zwiegincew at Abs., Fig. 3.
`
`16 Ex. 1010, Zwiegincew at 6:64-67, 7:7-10.
`
`17 Ex. 1010, Zwiegincew at 6:29-39.
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`18 Ex. 1010, Zwiegincew at 6:29-43.
`
`19 Ex. 1010, Zwiegincew at 7:24-49.
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`20 Ex. 1010, Zwiegincew at 6:30-37, 7:25-39, claim 2.
`
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`“wherein the updating comprises updating in response to the utilizing” and
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`
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`“wherein the updating comprises disassociating non-accessed boot data.” I
`
`disagree, as explained below in Sections VII.B.-VII.D.
`
`D.   Dye Reference
`
`37.   Dye describes a flash memory controller having a compression and/or
`
`decompression engine to support, for example, Execute-In-Place architectures,
`
`which results in improved memory density and bandwidth.21 Dye’s flash memory
`
`system comprises a flash memory array 100 and a Compression Enhanced Flash
`
`Memory Controller (“CEFMC”) 200.22 Dye’s memory controller (CEFMC 200)
`
`controls the transmission of small data segments (i.e., row and column data
`
`addressed in DRAM) to and from memory. Embedded within CEFMC 200 are
`
`compression and decompression engines 260, 280.23
`
`38.  
`
`In Ground 3 and 4, Apple relies on Dye as disclosing the compression
`
`limitions. In Ground 4, Apple also relies on Dye as disclosing the compression
`
`limitations. I disagree, as explained below.24
`
`21 Ex. 1008, Dye at Abs., Figs. 7-9, 2:32-39, 2:42-53.
`
`22 Ex. 1008, Dye at 8:29-31.
`
`23 Ex. 1008, Dye at Abs., 8:48-52.
`
`24 Apple does not rely on Dye for teaching or suggesting “updating the boot data
`
`list,” “wherein the updating comprises updating in response to the utilizing” and
`
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`IV.   LEGAL STANDARDS TO BE APPLIED
`
`
`
`39.  
`
`I understand that in an inter partes review, Apple carries the burden of
`
`proving invalidity on a claim-by-claim basis. Each claim must be analyzed
`
`independently. I also understand that Apple must prove invalidity by a
`
`preponderance of the evidence. To meet this burden, Apple must show that it is
`
`more likely than not that the claim is invalid.
`
`40.  
`
`I understand that under the version of 35 U.S.C. § 103 of the patent
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`statutes (in the pre-AIA form of the § 103 statute that applies to the ‘862 Patent), a
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`patent claim may be invalid as obvious in view of a combination of prior art
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`references. Obviousness is determined from the perspective of a hypothetical
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`person of ordinary skill in the art (“POSITA”).
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`41.  
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`I understand that obviousness may be based upon a combination of
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`references. I further understand that the combination of familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. However, I also understand that a patent claim composed
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`of several elements is not proved obvious merely by demonstrating that each of its
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`elements was, independently, known in the prior art.
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`“wherein the updating comprises disassociating non-accessed boot data”
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`limitations, and it is my opinion that Dye does not disclose these limitations.
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`42.  
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`I understand that when a patented invention is a combination of
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`known elements, a court (or the Board) must determine whether there was an
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`apparent reason to combine the known elements in the fashion claimed by the
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`patent at issue by considering the teachings of prior art references, the background
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`knowledge possessed by a person having ordinary skill in the art, and the effects of
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`demands known to people working in the field or present in the marketplace.
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`43.  
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` Further, I understand that a patent claim composed of several
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`limitations is not proved obvious merely by demonstrating that each of its
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`limitations was independently known in the prior art. I also understand that
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`identifying a reason those elements would be combined can be important because
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`inventions in many instances rely upon building blocks long since uncovered, and
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`claimed discoveries almost of necessity will be combinations of what, in some
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`sense, is already known. Accordingly, it is improper to use hindsight in an
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`obviousness analysis and to use the patent’s claims as a “road map.”
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`44.  
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`I also understand that a POSITA would not combine references in
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`order to achieve a benefit or feature that is already present in one of the references
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`being combined. Furthermore, I understand that an invention may not be obvious if
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`the prior art reference(s) teaches away from the proposed modification or
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`combination of prior art references. In addition, an invention may not be obvious if
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`the proposed modification or combination would render the prior art inoperable for
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`its intended purpose. As well, an invention may not be obvious if the proposed
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`modification destroys the principle of operation of the prior art reference subject to
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`modification.
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`45.  
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`I understand that an obviousness analysis requires consideration of:
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`(1) the scope and content of the prior art; (2) differences between the prior art and
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`the claims at issue; (3) the level of ordinary skill in the art; and (4) objective
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`indicia of non-obviousness. Examples of objective indicia of non-obviousness, if
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`present, include commercial success, long-felt but unsolved needs, failure of
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`others, unexpected results, copying, skepticism of experts, industry praise,
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`significant effort or high cost to develop, near simultaneous invention, and industry
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`acceptance via licensing.
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`46.  
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`I understand that objective indicia of non-obviousness can be the most
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`probative evidence of nonobviousness in the record, and enables the court (or the
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`Board) to avert the trap of hindsight. Further, I understand that such evidence must
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`always when present be considered
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`in connection with an obviousness
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`determination. Further, to be afforded substantial weight, the objective indicia of
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`nonobviousness must be tied to the novel elements of the claims at issue, but the
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`objective indicia need to be only reasonably commensurate with the scope of the
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`claims.
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`47.  
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`I understand that all prior art references are to be looked at from the
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`viewpoint of a POSITA. Furthermore, obviousness is analyzed from the
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`perspective of one of ordinary skill in the art at the time of the invention.
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`48.  
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`I have applied these legal standards to my opinions.
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`V.  
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`PERSON OF ORDINARY SKILL IN THE ART
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`49.  
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`It is my understanding that I must analyze and apply the teachings
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`from the prior art from the perspective of a person having ordinary skill in the art
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`as of February 3, 2000, which I understand to be the filing date of the provisional
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`application related to the ‘862 Patent.
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`50.   Based on my experience in the field and review of Dr. Neuhauser’s
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`declaration, I agree with Dr. Neuhauser’s determination of the level of ordinary
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`skill in the art at the time of the invention of the ‘862 Patent. Namely, I agree that a
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`POSITA at the time of the invention had a Bachelor’s Degree in electrical
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`engineering, computer engineering, or a related area of study (such as computer
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`science) with between three and five years of practical experience in the design and
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`implementation of computer systems, such as personal computers. I also agree
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`such a POSITA alternatively had a Master’s Degree in the area of electrical
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`engineering, computer engineering, or a related area of study (such as computer
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`science) and somewhat less practical experience.
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`51.  
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`I am well aware of the qualifications of such a person because I have
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`worked with, supervised, and hired engineers with similar capabilities. By the year
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`2000, I had been awarded degrees in Mathematics and Computer Science. I also
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`had 10 years of practical experience both in industry and academia. As of the year
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`2000, I was teaching and working with individuals who met the above criteria for
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`persons of ordinary skill in the art. In particular, I have taught and worked with
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`distinct groups of graduate students. One particular group entered the graduate
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`program with B.S. degrees in CS/CE/EE and several years of industry training (3
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`years was typical). Finally, I have worked with and taught advanced Ph.D. students
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`that had at least 3 years of post-BS experience and knowledge gained while in the
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`graduate program. During my time in industry, many of my colleagues possessed
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`at least a B.S. in the relevant fields and had several years of work experience.
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`52.   These students and colleagues all possessed knowledge regarding the
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`design and implementation of computer systems, such as personal computers.
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`Further, many of these students ultimately found employment at companies that
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`had an expressed interest in and need for skills relating to computer system design
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`and implementation in this time frame.
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`53.   Thus, I am familiar with the understanding and knowledge of persons
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`of ordinary skill in the art as of February 3, 2000, and was at least as qualified as
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`the POSITA that I have identified above. I have applied the understanding of a
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`POSITA to my opinions in this declaration.
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`VI.   CLAIM CONSTRUCTION
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`54.  
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`I understand that the Board will interpret the claims according to their
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`broadest reasonable interpretation as understood by a POSITA at the time of
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`invention and consistent with the disclosure of the patent, including the
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`specification and drawings. Herein, I specifically address the meaning of the terms
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`“boot data list” and “non-accessed boot data.” For all other terms, I applied the
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`plain and ordinary meaning the terms would have had to a POSITA at the time of
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`invention.
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`A.   Term “Boot Data List”
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`55.   For purposes of this declaration, it is my opinion that a POSITA
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`would have understood the term “boot data list,” as used in claims 1-9, 11-14, 19-
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`21, 95-106, and 111-117 of the ‘862 Patent to mean “record used to identify and
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`load boot data into memory.” In my opinion, this is the broadest reasonable
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`interpretation in light of the specification.
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`56.   Specifically, based on the ‘862 Patent, a POSITA would have
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`understood that the recited “boot data list” refers to a record used to identify and
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`load boot data into