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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________
`
`EXPERT DECLARATION OF DR. GODMAR BACK IN SUPPORT OF
`THE PATENT OWNER’S RESPONSE
`
`APPLE, INC.,
`Petitioner
`
`v.
`
`REALTIME DATA LLC,
`Patent Owner
`
`____________________
`
`
`
` Case IPR2016-01738
`Patent 8,880,862
`
`____________________
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`TABLE OF CONTENTS
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`
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`I.  
`
`INTRODUCTION .......................................................................................... 1  
`
`A.   Summary of Issues ........................................................................................... 1  
`
`B.   Summary of Opinions ...................................................................................... 3  
`
`II.  
`
`PROFESSIONAL BACKGROUND .............................................................. 4  
`
`III.   TECHNOLOGY OVERVIEW ....................................................................... 8  
`
`A.   ‘862 Patent ....................................................................................................... 8  
`
`B.   Sukegawa Reference ...................................................................................... 10  
`
`C.   Dye Reference ................................................................................................ 12  
`
`D.   Settsu Reference ............................................................................................ 13  
`
`E.   Burrows Reference ........................................................................................ 13  
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`F.   Zwiegincew Reference .................................................................................. 14  
`
`IV.   LEGAL STANDARDS TO BE APPLIED .................................................. 17  
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`V.  
`
`PERSON OF ORDINARY SKILL IN THE ART ....................................... 20  
`
`VI.   CLAIM CONSTRUCTION ......................................................................... 22  
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`A.   Term “Boot Data List” ................................................................................... 22  
`
`B.   Term “Non-Accessed Boot Data” .................................................................. 28  
`
`C.   Apple’s Proposed Construction of “Boot Data” ............................................ 31  
`
`VII.   VALIDITY OF THE ‘862 PATENT ............................................................ 32  
`
`A.   Sukegawa Does Not Teach or Suggest the Claimed “Boot Data List.” ........ 32  
`
`B.   Zwiegincew’s Teachings Do Not Provide a Basis to Modify Sukegawa to
`Render Obvious the Claimed “Boot Data List.” ............................................ 38  
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`C.   Sukegawa Does Not Teach or Suggest “Disassociating Non-Accessed Boot
`Data from the Boot Data List.” ...................................................................... 43  
`
`D.   Sukegawa Does Not Teach or Suggest “Accessing Boot Data” Before
`“Loading the Boot Data” and “Servicing a Request for the Boot Data.” ...... 46  
`
`E.   Sukegawa Does Not Teach or Suggest “Loading” or “Accessing” Boot Data
`“That is Associated with a Boot Data List.” .................................................. 48  
`
`F.   Settsu’s Teachings Do Not Provide a Basis to Modify Sukegawa to Render
`Obvious “Loading” Boot Data “That is Associated with a Boot Data List.” 52  
`
`G.   Zwiegincew’s Teachings Do Not Provide a Basis to Modify Sukegawa to
`Render Obvious “Loading” Boot Data “That is Associated with a Boot Data
`List.” .............................................................................................................. 53  
`
`H.   Sukegawa in View of Dye Does Not Render Obvious the Challenged
`Claims. ........................................................................................................... 54  
`
`I.   Sukegawa Does Not Teach or Suggest “Boot Data Compris[ing] a Program
`Code Associated with…an Application Program.” ....................................... 60  
`
`J.   Dye Does Not Disclose Storing Compressed Boot Data in a Hard Disk
`Drive. ............................................................................................................. 61  
`
`K.   Sukegawa Does Not Teach or Suggest “the Utilizing Comprises: Utilizing the
`Stored Additional Portion of the Operating System to at Least Further
`Partially Boot the Computer System” ............................................................ 63  
`
`L.   Dye Does Not Disclose “a Plurality of Encoders.” ....................................... 65  
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`I, Godmar Back, declare as follows:
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`I.  
`
`INTRODUCTION
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`
`
`1.   My name is Dr. Godmar Back. I have been retained by Realtime Data
`
`LLC to offer my opinions concerning the validity of U.S Patent No. 8,880,862
`
`(“the ‘862 Patent”).
`
`2.  
`
`Specifically, I have been asked to analyze arguments made by Apple,
`
`Inc. and its expert, Dr. Charles J. Neuhauser, in the petition for inter partes review
`
`(“IPR”) proceeding of the ‘862 Patent, Case No. IPR2016-01738. I understand that
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`on March 20, 2017, the Patent Trial and Appeal Board (“the Board”) entered a
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`decision instituting (“the Institution Decision”) this IPR proceeding.
`
`A.  
`
`3.  
`
`Summary of Issues
`
`I understand that Apple’s Petition (and Dr. Neuhauser’s Declaration)
`
`allege the following five grounds of unpatentability:
`
`a.   Ground 1: claims 8-12, 14-22, 59-82, 101-104, 114-115, and 117
`of the ‘862 Patent are obvious over the combination of U.S. Patent
`No. 5,860,083 (“Sukegawa”) in view of U.S. Patent No. 6,145,069
`(“Dye”);
`b.   Ground 2: claims 8-12, 14-22, 59-82, 101-104, 114-115, and 117
`of the ‘862 Patent are obvious over the combination of Sukegawa
`in view of Dye and U.S. Patent No. 6,374,353 (“Settsu”);
`c.   Ground 3: claims 8-12, 14-22, 59-82, 101-104, 114-115, and 117
`of the ‘862 Patent are obvious over the combination of Sukegawa
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`in view of Dye and Burrows et al., “On-line Data Compression in a
`Log-structured File System” (“Burrows”);
`d.   Ground 4: claims 8-12, 14-22, 59-82, 101-104, 114-115, and 117
`of the ‘862 Patent are obvious over the combination of Sukegawa
`in view of Dye, Settsu, and Burrows; and
`
`e.   Ground 5: claims 8-12, 14-22, 59-82, 101-104, 114-115, and 117
`of the ‘862 Patent are obvious over the combination of Sukegawa
`in view of Dye and U.S. Patent No. 6,317,818 (“Zwiegincew”).
`
`4.  
`
`I understand that in its Institution Decision, the Board instituted IPR
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`on Ground 1 (Sukegawa in view of Dye) for claims 8-12, 14-22, 59-82, 101-104,
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`114-115, and 117 (the “Challenged Claims”). I also understand that the Board
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`instituted IPR on Ground 2 (Sukegawa in view of Dye and Settsu) for the
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`Challenged Claims. Further, I understand that the Board instituted IPR on Ground
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`3 (Sukegawa in view of Dye and Burrows) for the Challenged Claims. Also, I
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`understand that the Board instituted IPR on Ground 4 (Sukegawa in view of Dye,
`
`Settsu, and Burrows) for the Challenged Claims. Lastly, I understand that the
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`Board instituted IPR on Ground 5 (Sukegawa in view of Dye and Zwiegincew) for
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`the Challenged Claims.
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`5.  
`
`In forming my opinions, I have reviewed the ‘862 Patent, its file
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`history, priority application 60/180,114 listed on the cover of the ‘862 Patent, Dr.
`
`Neuhauser’s declaration (“the Neuhauser Declaration”), Apple’s Petition for Inter
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`Partes Review, the references upon which Apple’s Petition and Dr. Neuhauser
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`rely, Realtime’s Preliminary Response, the Institution Decision, and materials
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`referenced herein.
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`6.   My opinions are based on my experience and knowledge of the
`
`relevant art, the documents identified above, as well as the documents discussed in
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`this declaration.
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`B.  
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`7.  
`
`Summary of Opinions
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`As explained in detail below, it is my opinion that claims 8-12, 14-22,
`
`59-82, 101-104, 114-115, and 117 of the ‘862 Patent are not obvious over:
`
`a.   Sukegawa in view of Dye;
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`b.   Sukegawa in view of Dye and Settsu;
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`c.   Sukegawa in view of Dye and Burrows;
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`d.   Sukegawa in view of Dye, Settsu, and Burrows; or
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`e.   Sukegawa in view of Dye and Zwiegincew.
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`8.  
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`Specifically, Sukegawa does not disclose “a boot data list,” as
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`required by each Challenged Claim. Similarly, Sukegawa, alone or in view of
`
`Zwiegincew, does not render obvious (a) “disassociating non-accessed boot data
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`[or operating system] from the boot data list” or (b) “updating the boot data list” in
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`response to the “accessing” step or “utilizing” step, as required by claims 20, 102,
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`104, 114, 115 and 117. Sukegawa also does not disclose “load[ing]” or “accessing”
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`boot data or operating system (“OS”) “that is associated with a boot data list,” as
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`required by each Challenged Claim. Moreover, Sukegawa in view of the relevant
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`prior art does not render obvious “load[ing]” or “accessing” boot data or OS “that
`
`is associated with a boot data list.” Also, for each Challenged Claim, Dye teaches
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`away from storing compressed boot data in Sukegawa’s hard drive for loading into
`
`flash memory 1. Even further, Sukegawa does not disclose “boot data [or operating
`
`system] compris[ing] a program code associated with…an application program,”
`
`as required by claims 17, 60, 65 and 77. Lastly, Dye does not disclose “a plurality
`
`of encoders,” as required by claims 70 and 82. As such, it is my opinion that the
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`challenged claims are not obvious as alleged by Apple and Dr. Neuhauser.
`
`II.  
`
`PROFESSIONAL BACKGROUND
`
`9.  
`
`I have been working in the field of computer science for over 25
`
`years. My areas of expertise include computer systems, operating systems, and
`
`kernels. My experience includes, as a few examples, research, publications,
`
`lectures, and workshops in the field of computer systems, operating systems, and
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`kernels. My Curriculum Vitae is attached hereto (Exhibit 2009).
`
`10.  
`
`I obtained my undergraduate degree in Mathematics and Computer
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`Science from Humboldt University of Berlin in 1992, and I studied Computer
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`Science at the Technical University of Berlin from 1992-1994.
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`11.   From September 1994 to May 1995, I was a Teaching Assistant in the
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`Department of Computer Science at University of Utah, where I co-taught senior-
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`level undergraduate courses and entry-level graduate courses in operating systems,
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`networking, and compilers.
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`12.   From June 1995 to November 2001, I was a Research Assistant in the
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`Computer Systems Laboratory at University of Utah, where I conducted research
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`on component-based operating systems (OSKit) and microkernel systems (Fluke).
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`My research was published at the Second Symposium on Operating Systems
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`Design and Implementation (OSDI) in 1996 and at the 16th ACM Symposium on
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`Operating Systems Principles (SOSP) in 1997. Also during this time period, I
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`conducted my dissertation research on runtime systems that support multiple
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`applications. My research was published at the Seventh Workshop on Hot Topics
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`in Operating Systems (HotOS) in 1999, at the Fourth Symposium on Operating
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`Systems Design and Implementation (OSDI) in 2000, and at the USENIX 2000
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`Annual Technical Conference in 2000. I also received travel scholarship awards
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`from Usenix, ACM, and the IEEE for various conferences such as these.
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`13.  
`
`In May 2002, I received my Ph.D. in Computer Science from the
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`University of Utah. I wrote my dissertation on the topic, “Isolation, Resource
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`Management and Sharing in the KaffeOS Java Runtime System,” which went on to
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`win the 2003 ACM SIGPLAN Doctoral Dissertation Award.
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`14.   Between November 2001 and June 2004, I was a Postdoctoral Scholar
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`in the Computer Systems Laboratory at Stanford University. During my time at
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`Stanford, I researched static analysis tools. As part of my research, I developed the
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`MJ system for checking properties and implementing bug-finding analyses in Java
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`code. I also worked on the design and implementation of DataScript, an input
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`description language that supports code generation. I published my work on this
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`language at the ACM Conference on Generative Programming and Component
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`Engineering Proceedings (GPCE) in 2002. I also taught courses on “Introduction to
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`Compilers” during my time at Stanford.
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`15.  
`
`In August 2004, I was appointed as Assistant Professor in the
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`Department of Computer Science at Virginia Tech. In June 2010, I was promoted
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`to Associate Professor, the position I currently hold. Between 2004 and 2015, I
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`taught both graduate and undergraduate courses in “Operating Systems.” I have
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`also taught undergraduate courses such as “Computer Systems,” “Introduction to
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`Software Design,” “Systems and Networking Capstone,” and “Cloud Software
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`Engineering,” and graduate courses such as “Advanced Topics in Program
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`Analysis,” “Network Architectures and Protocols,” and “Execution Environments
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`for Cloud Applications.” My current research interests include: operating and
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`runtime systems, virtualization, software engineering, software visualization, web
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`technology, cloud-based systems, high-performance computing, domain-specific
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`languages, and library technology.
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`16.   Throughout my career, I have been an external reviewer for several
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`
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`professional publications and organizations, including the Journal of Parallel and
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`Distributed Computing; the Journal of STEM Education; National Science
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`Foundation; IEEE Transactions on Parallel and Distributed Systems; the Journal of
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`Simulation Modelling Practice and Theory; IEEE Computer; ASEE Southeast
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`conference; Proceedings of the IEEE; ACM Transactions on Programming
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`Languages; the Journal of the ACM; Software Practice and Experience;
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`Transactions on Information Systems (TOIS); USENIX; the Journal of Systems
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`and Software; ICCD; SOSP; OSDI; PACT; ECOOP; EUROPAR; and the
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`Informatik Forum Journal.
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`17.  
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`I have also held
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`leadership positions at several professional
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`conferences and workshops. For instance, I have been the Program Co-Chair for
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`the Operating Systems track at ICCD; a Program Committee Member for the
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`International Conference on Parallel Processing (ICPP); a Program Committee
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`Member of the International Workshop on Programming Support Innovations for
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`Emerging Distributed Applications; and a Program Committee Member for the
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`SPLASH/Wavefront conference.
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`18.  
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`I have published 21 conference papers, nine journal articles, chapters
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`in 2 books, and 11 workshop papers. Many of my works relate to computer
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`systems, operating systems, and kernels.
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`19.   My compensation is not dependent on the outcome of this case, and I
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`
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`have no financial interest in the outcome.
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`III.   TECHNOLOGY OVERVIEW
`
`A.  
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`‘862 Patent
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`20.   The ‘862 Patent is generally directed to systems and methods for
`
`providing accelerated loading of operating systems and application programs in a
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`computer system.1
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`21.   One method of increasing computer performance at the time of
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`invention was the use of onboard memory and onboard caches. These onboard
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`memories and caches are faster than the common-place magnetic HDD’s and thus
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`allow host systems to quickly access necessary data.2 Thus, data is temporarily
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`stored in a cache or other high-speed memory, and host systems do not have to
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`wait for relatively slow hard drives to retrieve the needed data.
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`22.   Computers at the time of the invention suffered from slow boot times,
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`even with high-speed onboard memories and caches.3 One reason for this is that
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`upon reset, conventional boot device controllers of the time would wait for a
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`1 Ex. 1001, ‘862 Patent at 1:20-26.
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`2 E.g., Ex. 1001, ‘862 Patent at 1:29-31, 20:36-49; Ex. 1005, Sukegawa at 1:14-16,
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`42-49.
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`3 E.g., Ex. 1001, ‘862 Patent at 20:45-49; Ex. 1005, Sukegawa at 1:46-49.
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`command before loading data for processing.4 Since boot device controllers are
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`typically reset along with the host system, the time spent by the boot device
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`controller waiting for commands is unproductive.5 Also, once the CPU is
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`initialized and issues commands requesting data to the boot device controller, time
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`is wasted while the CPU waits for the boot device controller to carry out the CPU’s
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`command and provide the requested information. All this wasted time results in
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`delay experienced by the user. Traditional high-speed memories of the time were
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`also volatile memories, the contents of which are erased upon power reset.6
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`Therefore, storing desired information, such as boot information, ahead of time
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`was not possible.
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`23.   To address these problems, the ‘862 Patent discloses and claims
`
`methods and systems for loading compressed boot data associated with a boot data
`
`list, and updating the boot data list. Specifically, the claims of the ‘862 are directed
`
`to, among other things, maintaining a list of boot data, loading boot data in
`
`compressed form (based on the list) from a boot device into a cache memory,
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`4 Ex. 1001, ‘862 Patent at 20:38-49.
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`5 Ex. 1001, ‘862 Patent at 20:38-49.
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`6 See Ex. 1005, Sukegawa at 1:21-26. See also Ex. 1003, Neuhauser Dec. at ¶ 44
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`(recognizing that flash memory based designs were expensive on a per bit basis at
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`the time of invention).
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`accessing the loaded boot data and decompressing the boot data at a rate that
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`decreases boot time of the operating system relative to loading the operating
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`system with uncompressed boot data.7
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`24.   Another aspect of the inventions of the ‘862 Patent is updating the list
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`of boot data during the boot process by adding to the list any boot data requested
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`by the computer which was not previously stored in the list, as well as removing
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`from the list any boot data previously stored in the list but not requested by the
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`CPU.8 The ‘862 Patent’s system also includes a processor configured to load
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`compressed boot data associated with a boot data list into memory, to access the
`
`loaded boot data, to decompress the access portion of boot data, and to update the
`
`boot data list.9 These systems and methods result in a faster bootup of computer
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`systems.
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`B.  
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`Sukegawa Reference
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`25.   Sukegawa describes a “permanent storage” solution in which
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`“information…necessary for starting up…the OS and AP are permanently stored
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`in the flash memory.”10 Sukegawa’s disclosed solution contrasts with the ‘862
`
`7 E.g., Ex. 1001, ‘862 Patent at 3:35-52, Claims 1, 5, 6, 8, 11, 13 and 14.
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`8 E.g., Ex. 1001, ‘862 Patent at 3:53-59, Claims 1, 5, 6, 8, 11, 13 and 14.
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`9 Ex. 1001, ‘862 Patent at 4:4-20.
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`10 Ex. 1005, Sukegawa at 2:11-16. (emphasis added).
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`Patent’s approach to reducing boot times that, during the same power-on cycle,
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`loads compressed boot data associated with a boot data list, accesses the loaded
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`portion, and decompresses the accessed portion at a rate that decreases boot time of
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`the operating system.
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`26.   Sukegawa discloses that there was a problem with cache systems: the
`
`caches utilized a portion of the high-speed DRAM main memory (which is a
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`volatile storage medium), and such memory was cleared when the power to the
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`system is switched off. As a result, “the cache system does not function when the
`
`power is switched on.”11 To overcome this drawback, Sukegawa proposes using
`
`non-volatile memory to permanently store data needed for system startup instead
`
`of a traditional volatile cache.12
`
`27.   Apple and Dr. Neuhauser contend that Sukegawa discloses the claim
`
`elements “boot data list” and “[loading/accessing] boot data [or OS]…associated
`
`with a boot data list.”13 I disagree, as explained below in Sections VII.A. and
`
`VII.E.
`
`11 E.g., Ex. 1005, Sukegawa at 1:50-61.
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`12 Ex. 1005, Sukegawa at 1:53-61(Because “[t]he flash memory … is a non-volatile
`
`storage medium and has a higher access speed than the HDD,” “the cache function
`
`is effectively performed at the time of turning on power.”).
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`13 E.g., Petition at 12-16, 28-29, 32-33.
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`C.   Dye Reference
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`
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`28.   Dye describes a flash memory controller having a compression and/or
`
`decompression engine to support, for example, Execute-In-Place architectures,
`
`which results in improved memory density and bandwidth.14 Dye’s flash memory
`
`system comprises a flash memory array 100 and a Compression Enhanced Flash
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`Memory Controller (“CEFMC”) 200.15 Dye’s memory controller (CEFMC 200)
`
`controls the transmission of small data segments (i.e., row and column data
`
`addressed in DRAM) to and from memory. Embedded within CEFMC 200 are
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`compression and decompression engines 260, 280.16
`
`29.   Dye
`
`does
`
`not
`
`teach
`
`or
`
`suggest
`
`using
`
`the
`
`disclosed
`
`compression/decompression system with traditional platter drives, and is instead
`
`limited to flash media. Also, Dye does not teach or suggest using the disclosed
`
`system in a data storage controller, as in Sukegawa, for accessing data sectors used
`
`to store and access operating system files. Therefore, a POSITA would not have
`
`looked to Dye when considering whether to apply compression to a data storage
`
`controller for a traditional hard drive such as Sukegawa’s HDD 2.
`
`
`14 Ex. 1008, Dye at Abs., Figs. 7-9, 2:32-39, 2:42-53.
`
`15 Ex. 1008, Dye at 8:29-31.
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`16 Ex. 1008, Dye at Abs., 8:48-52.
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`D.  
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`Settsu Reference
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`
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`30.   Settsu is directed to “[a] method of booting up an information
`
`processing apparatus.”17 In addition, Settsu discloses a process for booting up a
`
`system that comprises a boot device divided into a mini-operating system (“OS”)
`
`module and an OS main body wherein modules of the OS main body may be
`
`stored as compressed files.18
`
`31.  
`
`In Settsu’s system, certain application programs that need only a
`
`subset of the OS’s functionality can be started after loading only a subset of
`
`functional modules, thus speeding up boot times for this special case.19
`
`E.  
`
`Burrows Reference
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`32.   Burrows is directed to a particular type of file system utilizing data
`
`compression and reports the results of tests of that system.20 Specifically, Burrows
`
`discloses a log-structured file system aimed at improving performance by
`
`eliminating non-sequential disk writes, which also uses compression software
`
`routines so that data occupies less space on disk.21
`
`17 Ex. 1006, Settsu at Abs.
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`18 Ex. 1006, Settsu at Abs., 1:51-65, 3:6-12.
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`19 E.g., Ex. 1006, Settsu at Abs., 1:51-65, 7:66-9:3.
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`20 Ex. 1007, Burrows at v.
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`21 Ex. 1007, Burrows at 8, 10.
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`33.   Burrow’s disclosures regarding its log-structured file system illustrate
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`
`
`certain obstacles and challenges faced by a POSITA at the time of the filing of the
`
`‘862 Patent when trying to integrate compression into filesystem designs for
`
`traditional, platter-based hard drives.
`
`F.  
`
`Zwiegincew Reference
`
`34.   Zwiegincew is directed at the management of program code and data
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`pages of application program modules during hard page fault intensive scenarios.
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`To understand hard page faults, it is helpful to understand virtual memory and
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`paging in the context of modern computer systems.
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`35.   Virtual memory is a memory management technique that uses both
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`hardware and software. When using virtual memory, program code utilizes virtual
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`addresses that are mapped to the physical locations of the data in RAM. The blocks
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`of data that are mapped in this way are known as pages.
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`36.   When a user or the system starts a new process, modern operating
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`systems do not load the process’s program code into RAM all at once. Especially
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`when a program is large, not all parts of the program may be needed, and loading
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`them upfront would waste time and memory. Instead, these systems use a method
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`called “on-demand paging,” where parts of a program are not loaded until the
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`process running the program actually tries to execute them. If and when this
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`happens, the OS recognizes which part of the program is requested, loads it from
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`disk into memory, and resumes the process. This memory management process is
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`performed by the OS’s virtual memory management module, commonly referred to
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`as “virtual memory manager.”
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`37.   The virtual memory manager keeps track of which virtual addresses
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`have been loaded to RAM and which ones have not. For virtual addresses that
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`have been loaded to RAM, the virtual memory manager instructs the CPU’s
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`memory management unit (MMU) where to find the physical address of the page
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`in RAM.
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`38.   A hard page fault occurs when a process references a page in its
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`virtual address space that has not been loaded to RAM. In this situation, the
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`process is interrupted while the page is retrieved from the hard disk and loaded to
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`RAM. The virtual memory manager updates its tables to indicate that the requested
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`page is now available in RAM and identifies the location of that page in RAM. The
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`process can then resume and utilize the page. Because handling a hard page fault
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`requires accessing the hard disk which is much slower than RAM, these hard page
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`faults slow down the process. If the OS knew which pages the program was likely
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`to access, it could prefetch those pages into memory. Then, if the program
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`accesses them, they are available when needed, thereby avoiding a “hard page
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`fault.”
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`39.   To reduce the occurrence of hard page faults, Zwiegincew discloses
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`
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`that a “scenario file” may pre-fetch pages of application programs prior to the
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`occurrence of a hard page fault sequence.22 In other words, Zwiegincew proposes
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`to prevent hard page faults from occurring through the use of these “scenario
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`files.”23
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`40.   Zwiegincew’s “scenario file” is a file that identifies characteristics,
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`markers, or other indicators that a hard page fault is likely to occur—a so-called
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`“page fault scenario.”24 The scenario file can also include a copy or identification
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`of the page file that is needed to avoid the impending hard page fault.25 The
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`system is monitored based on the information in the scenario file and when a hard
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`page fault scenario is detected and thus a hard page fault is likely to occur, the
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`system can load the page identified by the scenario file.26 Thus, the scenario file
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`anticipates and prevents hard page faults, thereby increasing system speed.
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`22 Ex. 1010, Zwiegincew at 4:6-19.
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`23 Ex. 1010, Zwiegincew at 4:6-19.
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`24 Ex. 1010, Zwiegincew at Abs., Fig. 3.
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`25 Ex. 1010, Zwiegincew at 6:64-67, 7:7-10.
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`26 Ex. 1010, Zwiegincew at 6:29-39.
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`41.   Zwiegincew further discloses the idea of automatically refining the
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`
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`scenario file so it can more accurately identify hard page fault scenarios.27
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`Towards that end, Zwiegincew also discusses a mode in which hard page faults are
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`recorded in a log, thus allowing a subsequent pattern-based algorithm to analyze
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`this log to refine the page fault markers and indicators in the scenario file to better
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`predict the occurrence of page faults.28
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`42.   Apple contends that Zwiegincew in combination with Sukegawa
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`renders obvious “a boot data list,” and “loading” boot data “associated with a boot
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`data list.” I disagree, as explained below in Sections VII.B. and VII.G.
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`IV.   LEGAL STANDARDS TO BE APPLIED
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`43.  
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`I understand that in an inter partes review, Apple carries the burden of
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`proving invalidity on a claim-by-claim basis. Each claim must be analyzed
`
`independently. I also understand that Apple must prove invalidity by a
`
`preponderance of the evidence. To meet this burden, Apple must show that it is
`
`more likely than not that the claim is invalid.
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`44.  
`
`I understand that, under the version of 35 U.S.C. § 103 of the patent
`
`statutes that applies to the ‘862 Patent, a patent claim may be invalid as obvious in
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`27 Ex. 1010, Zwiegincew at 7:24-49.
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`28 Ex. 1010, Zwiegincew at 6:30-37, 7:25-39, claim 2.
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`view of a combination of prior art references. Obviousness is determined from the
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`
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`perspective of a hypothetical person of ordinary skill in the art (“POSITA”).
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`45.  
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`I understand that obviousness may be based upon a combination of
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`references. I further understand that the combination of familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. However, I also understand that a patent claim composed
`
`of several elements is not proved obvious merely by demonstrating that each of its
`
`elements was, independently, known in the prior art.
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`46.  
`
`I understand that when a patented invention is a combination of
`
`known elements, a court (or the Board) must determine whether there was an
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`apparent reason to combine the known elements in the fashion claimed by the
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`patent at issue by considering the teachings of prior art references, the background
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`knowledge possessed by a person having ordinary skill in the art, and the effects of
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`demands known to people working in the field or present in the marketplace.
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`47.  
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` Further, I understand that a patent claim composed of several
`
`limitations is not proved obvious merely by demonstrating that each of its
`
`limitations was independently known in the prior art. I also understand that
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`identifying a reason those elements would be combined can be important because
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`inventions in many instances rely upon building blocks long since uncovered, and
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`claimed discoveries almost of necessity will be combinations of what, in some
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`sense, is already known. Accordingly, it is improper to use hindsight in an
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`
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`obviousness analysis and to use the patent’s claims as a “road map.”
`
`48.  
`
`I also understand that a POSITA would not combine references in
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`order to achieve a benefit or feature that is already present in
`
`one of the references being combined. Furthermore, I understand that an invention
`
`may not be obvious if the prior art reference(s) teaches away from the proposed
`
`modification or combination of prior art references. In addition, an invention may
`
`not be obvious if the proposed modification or combination would render the prior
`
`art inoperable for its intended purpose. As well, an invention may not be obvious if
`
`the proposed modification destroys the principle of operation of the prior art
`
`reference subject to modification.
`
`49.  
`
`I understand that an obviousness analysis requires consideration of:
`
`(1) the scope and content of the prior art; (2) differences between the prior art and
`
`the claims at issue; (3) the level of ordinary skill in the art; and (4) objective
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`indicia of non-obviousness. Examples of objective indicia of non-obviousness, if
`
`present, include commercial success, long-felt but unsolved needs, failure of
`
`others, unexpected results, copying, skepticism of experts, industry praise,
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`significant effort or high cost to develop, near simultaneous invention, and industry
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`acceptance via licensing.
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`50.  
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`I understand that objective indicia of non-obviousness can be the most
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`
`
`probative evidence of nonobviousness in the record, and enables the court (or the
`
`Board) to avert the trap of hindsight. Further, I understand that such evidence must
`
`always when present be considered
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`in connection with an obviousness
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`determination. Further, to be afforded substantial weight, the objective indicia of