throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`James J. Fallon, et al.
`In re Patent of:
`8,880,862 Attorney Docket No.: 39521-0025IP1
`U.S. Patent No.:
`November 4, 2014
`Issue Date:
`Appl. Serial No.: 13/118,122
`Filing Date:
`May 27, 2011
`Title:
`SYSTEMS AND METHODS FOR ACCELERATED
`LOADING OF OPERATING SYSTEMS AND
`APPLICATION PROGRAMS
`
`DECLARATION OF DR. CHARLES J. NEUHAUSER
`
`I.
`
`Introduction
`
`1. My name is Dr. Charles J. Neuhauser. I understand that I am submitting a
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`declaration in connection with an Inter Partes review (“IPR”) proceeding before
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`the United States Patent and Trademark Office for U.S. Patent No. 8,880,862
`
`(“the ’862 Patent”).
`
`
`
`2.
`
`I have been retained on behalf of Apple Inc. to offer technical opinions with
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`respect to the ’862 Patent and the prior art references cited in this IPR. My
`
`compensation is not based on the outcome of this matter.
`
`
`
`3.
`
`I am not a lawyer. However, counsel has advised me of legal concepts that are
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`relevant to IPR proceedings and to the opinions that I offer in this declaration. I
`
`understand that, during IPR, claims of the subject patent are given a broadest
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`reasonable interpretation. Counsel has advised me that the broadest reasonable
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`1
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`Apple v. Realtime
`Proceeding No. IPR2016-01737
`APPLE 1043
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`interpretation must be consistent with the specification, and that claim language
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`should be read in light of the specification and teachings in the underlying patent.
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`
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`4.
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`I have reviewed the ’862 Patent, including the claims of the patent in view of the
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`specification, and I have reviewed the ’862 Patent’s prosecution history. In
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`addition, I have reviewed the following documents: U.S. Patent No. 6,374,353
`
`(“Settsu”), U.S. Patent No. 6,145,069 (“Dye”), U.S. Patent No. 7,190,284 (“Dye
`
`’284”), Burrows et al., “On-line Data Compression in a Log-structured File
`
`System” (1992) (“Burrows”), U.S. Patent No. 6,317,818 (“Zwiegincew”), U.S.
`
`Patent No. 6,633,968 (“Zwiegincew ’968”), U.S. Patent No. 6,434,695
`
`(“Esfahani”), U.S. Patent No. 6,073,232 (“Kroeker”), Jeff Prosise, DOS 6 – The
`
`Ultimate Software Bundle?, PC Magazine, Apr. 13, 1993 (“Prosise”), Decoder,
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`File, Program File, Direct Memory Access, RAM, and RAM Cache, Microsoft
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`Press Computer Dictionary (3d ed. 1997)(“MSFT Dictionary”), Jacob Ziv &
`
`Abraham Lempel, A Universal Algorithm for Sequential Data Compression, IT-
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`23 No. 3 IEEE Transactions on Information Theory 337 (1977)(“Ziv”), James A.
`
`Storer & Thomas G. Szymanski, Data Compression via Textual Substitution, 19
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`No. 4 Journal of the Association for Computing Machinery (1982)(“Storer”),
`
`Kyle Loudon, Mastering Algorithms with C (1999) (“Loudon”), Michael Barr,
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`Programming Embedded Systems in C and C++ (1999)(“Barr”), Eric Pearce,
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`2
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`Windows NT in a Nutshell (1999)(“Pearce”), and Tim O’Reilly, Troy Mott, and
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`Walter Glenn, Windows 98 in a Nutshell (1999)(“O’Reilly”).
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`
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`5.
`
`I provided details of my professional background with my earlier-submitted
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`declarations, and I do not repeat those details here.
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`
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`II. Detailed Discussion
`
`A. One of Ordinary Skill
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`6.
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`It is my understanding that I must analyze and apply the prior art cited above
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`from the perspective of a person having ordinary skill in the art as of February 3,
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`2000 (“one of ordinary skill”), which I understand to be the ’862 Patent’s earliest
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`possible priority date.
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`
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`7. The ’862 Patent relates to accessing data in conventional computer systems.
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`Figure 1 is an exemplary figure that illustrates the basic structure of one
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`embodiment of the ’862 Patent’s system [’862 Patent, 4:36-37, 5:63-65]. This
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`and other similar figures of the ’862 Patent show straightforward and well known
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`structures related to conventional computer systems, such as the widely used
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`personal computer. In my opinion, one of ordinary skill would be a person with a
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`Bachelor’s Degree in electrical engineering, computer engineering, or a related
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`3
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`area of study. In addition, this person would have between three and five years
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`of practical experience in the design and implementation of computer systems,
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`such as personal computers. Alternatively, a person with a Master’s Degree in
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`the area of electrical engineering, computer engineering, or a related area of study
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`and somewhat less practical experience would be similarly qualified.
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`
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`8.
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`I am well aware of the qualifications of such a person because I have worked
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`with, supervised, and hired engineers with similar capabilities. By the year 2000,
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`I had been awarded a Ph.D. in CS/EE with a specialization in computer
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`engineering and had over 30 years of practical experience. Thus, by February 3,
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`2000, I was at least as qualified as the person having ordinary skill in the art that I
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`have identified above. Moreover, I understand the perspective of one of ordinary
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`skill, which I have applied in my analysis.
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`
`
`B.
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`Prior Art and the Claims of the ’862 Patent
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`9. The Patent Owner has requested amendment of the challenged claims,
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`conditional on the Board finding independent claims 1, 6, and 13 unpatentable.
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`Alleged patentability rests with the amendments to the independent claims, with
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`amendments to the dependent claims serving the purpose of conforming the
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`dependent claims to the changes in the independent claims.
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`4
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`10. The amendments introduced by Patent Owner in its proposed substitute claims
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`are directed toward trivial features that one of ordinary skill would have
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`considered obvious over the prior art.
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`
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`11. As I discuss below, for example, one of ordinary skill would have been aware of
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`the relatively high cost of non-volatile flash memory used by Sukegawa, and
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`related constraints on the capacity of Sukegawa’s flash memory. In seeking to
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`reduce utilization of this expensive and limited flash memory, one of ordinary
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`skill would have found it obvious to make use of less costly volatile memory
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`(e.g., RAM) when preloading boot data in a manner otherwise consistent with
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`Sukegawa. Beyond reducing costs, one of ordinary skill would expect this
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`approach to enhance performance.
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`
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`12. Esfahani and Kroeker each provide specific teachings that would further motivate
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`and support such an approach to the implementation of Sukegawa’s system, and
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`if Sukegawa’s system were implemented in the manner described, it would meet
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`the amended claim language.
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`As another example, Settsu, both alone and in combination with Zwiegincew,
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`renders obvious every feature of the proposed substitute claims, including the
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`amended features.
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`
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`C.
`Sukegawa in view of Dye and Kroeker
`13. Sukegawa – one of ordinary skill would have been aware that Sukegawa’s non-
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`volatile flash memory was both expensive and not of limited capacity, and would
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`have been faced with design choices of how to best preload in a situation where
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`cost precludes preloading all of the boot data into non-volatile flash memory.
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`Seeking to reduce the use of this expensive and limited flash memory, one of
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`ordinary skill would have found it obvious to make use of less costly volatile
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`memory (e.g., RAM) when preloading boot data in a manner otherwise consistent
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`with Sukegawa.
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`
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`14. In this situation, one of ordinary skill would have still been motivated by
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`Sukegawa to preload any boot data that exceeds the capacity of the flash memory
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`as quickly as possible after power-on. Indeed, to the extent the non-volatile flash
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`memory lacks such capacity, one of ordinary skill would have found it obvious to
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`preload some boot data into flash memory and then preload any remaining boot
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`data into volatile memory (e.g., RAM) upon power-on. One of ordinary skill
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`would have viewed this solution as advantageous for reducing the need for of
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`Sukegawa’s expensive non-volatile memory, without necessarily slowing
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`Sukegawa’s boot process, as it leverages the time needed to start the boot process
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`to preload additional boot data that would otherwise just be waiting on disk.
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`
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`15. Kroeker – Kroeker’s system preloads boot data associated with a boot data list
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`by transferring boot data into volatile memory during the same boot sequence in
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`which a boot device controller receives a command over a computer bus to load
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`the boot data [Kroeker, Abstract, 2:29-47].
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`
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`16. Specifically, Kroeker recognized that, “[w]hen a computer undergoes a hardware
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`reset (i.e., a power-on or reset), the computer” and its “hard disk drive” execute
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`“power on/reset procedures,” and further recognized that it was typically only
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`after these procedures were complete that the computer “requests data from the
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`disk drive” to initialize an OS “program,” such as “DOS, Windows, UNIX, OS/2,
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`AIX, etc.” [Kroeker, 1:14-29]. Seeking to speed the boot process, Kroeker
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`found an opportunity in the fact “that during hardware resets the disk drive
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`associated with a host computer typically completes its booting process before
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`the host computer is ready for program transfer,” and proposed a preloading
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`solution that uses “this period” to more rapidly communicate an OS program to
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`the host computer [Kroeker, 1:55-64]. In Kroeker’s solution, “before the host
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`computer is ready for data but after the disk drive has completed its reset
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`routine,” Kroeker uses a “prefetch table” to access OS data from the disk and
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`“copies it onto the cache of the disk drive, from where it is transferred to the host
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`computer when the host computer requests it” [Kroeker, Abstract]. Because data
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`is transmitted to the host computer more quickly from the cache than the disk
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`drive, Kroeker’s preloading “increas[es] boot speed of a host computer” by
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`“shortening the load time” [Kroeker, Abstract, 1:9-12].
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`
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`17. As shown in FIG. 1, Kroeker’s disk drive 12 includes data storage disks 16, a
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`“random access memory (RAM) data cache 18” (i.e., volatile memory), and a
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`controller 20 [Kroeker, 3:61-4:21]. Kroeker preloads OS data into cache 18
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`using a process that is illustrated in FIG. 3 and that begins “immediately after the
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`hard disk drive 12 has completed its power-on/reset…routine.” [Kroeker, 4:63-
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`67]. In Kroeker’s process, a “prefetch table is read…into the RAM cache 18,”
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`the prefetch table (i.e., boot data list) including “a listing of the disk locations and
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`lengths of data records that were requested by the host computer 14 in the
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`immediately previous power-on/reset” (i.e., boot data)” [Kroeker, 5:3-7]. Data
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`“represented by the prefetch table” is then read “from the disks 16 into the RAM
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`cache 18” [Kroeker, 4:63-5:21]. A read command (command to load) is then
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`received by the controller “indicating that the host computer 14, pursuant to its
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`initialization, is requesting data records that are part of a computer program such
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`as DOS or Windows,” and the requested records are transferred “from cache 18
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`to the host computer 14” [Kroeker, 5:41-6:13]. Kroeker’s process repeats until
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`“all records designated in the prefetch table have been loaded into cache and then
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`transferred to the host computer 14” [Kroeker, 6:14-36].
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`
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`18. Kroeker relates to shortening the load time of computer programs from a hard
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`disk to a host computer [Kroeker 1:9-12]. In particular, Kroeker describes an
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`approach to shortening the boot time of a host computer [Kroeker Abstract]. The
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`basic approach of Kroeker is to generate a prefetch table that indicates hard disk
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`records requested by the host computer during processing that follows a power-
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`on/reset. On a subsequent power-on/reset the disk controller will load the records
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`indicated in the prefetch table from hard disk to a cache located on the disk
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`controller. This process occurs while the host computer is being reset and before
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`it makes its first request for data from the hard disk. Once host computer reset is
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`completed the requests for data generated by the host computer can be handled
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`quickly from the cache rather than accessing the hard disk [Kroeker Abstract,
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`2:38-47]. Because the cache is composed of RAM it has a much faster access
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`time than the disk and the time to boot the host computer is improved.
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`9
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`19. Kroeker Fig. 1 illustrates the system of Kroeker as it might be configured for a
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`personal computer or work station [3:61-4:3]. On this figure I have made
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`annotations showing how the components of Kroeker relate to certain
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`terminology in the ‘862. The annotations here are consistent with those I have
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`presented for prior art discussed in may prior declarations.
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`20. Disk drive 12 contains a data storage disk 16 and an onboard controller 20.
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`[Kroeker 4:11-16]. Disk drive 12 also includes cache 18 composed of RAM that
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`is used to store data from data storage disk 16 according to the approach I will
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`describe below. [Kroeker 2:38-47, 4:5-10]. Disk drive 12 connects to host
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`computer 14. [Kroeker 3:61-4:3]. Onboard controller 20 includes an adaptive
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`cache module 24, which is storage containing instructions for the onboard
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`controller 20. [Kroeker 4:17-21]. The adaptive cache module 24 holds
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`microcode that provides microinstructions for execution by the onboard
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`controller 20. The adaptive cache module may be ROM, RAM, EEPROM or
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`DRAM. [Kroeker 3;49-54 4:21-28].
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`
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`21. Kroeker Fig. 3 illustrates the operation of the microcode that controls the onboard
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`controller 20 [Kroeker 3:55-56]. Table 1 also illustrates the operation of the
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`controller in a pseudo-language [Kroeker 6:63-67].
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`
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`22. Combination - with this background, one of ordinary skill would have been
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`motivated by Kroeker to update Sukegawa’s system to take advantage of the
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`period “before the host computer is ready for data but after the disk drive has
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`completed its reset routine” to further “increas[e] boot speed of a host computer”
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`by “shortening the load time” [Kroeker, Abstract; 1:9-12; 1:55-2:14]. Indeed,
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`one of ordinary skill would have found it obvious that a portion of Sukegawa’s
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`operating system would not have been preloaded into flash memory unit 1. For
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`11
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`that portion, one of ordinary skill would have been motivated to apply Kroeker’s
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`preloading techniques to shorten the load time from the hard disk and, thereby,
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`increase boot speed [Kroeker, Abstract, 1:9-12; 1:55-2:14].
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`
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`As explained in more detail below, one of ordinary skill would have been
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`motivated to add Kroeker’s volatile cache to Sukegawa’s system as an addition to
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`Sukegawa’s HDD 2. In doing so, one of ordinary skill would have found it
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`obvious to transfer boot data expected to be needed most quickly after power-on
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`into Sukegawa’s non-volatile flash memory 1, and to transfer the remaining boot
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`data from Sukegawa’s HDD 2 into Kroeker’s volatile cache using Kroeker’s
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`prefetch table and/or Sukegawa’s management information table 3A, “before the
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`host computer is ready for data but after the disk drive has completed its reset
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`routine” [Kroeker, Abstract].
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`
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`23. In fact, based on Kroeker’s disclosure, one of ordinary skill would have found
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`reducing the size of Sukegawa’s flash memory 1 to make use of the period when
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`the disk drive is ready, but the host computer is not, to be an “easy to use and
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`cost-effective” solution “for increasing boot speed” [Kroeker, Abstract, 1:9-
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`2:14]. Sukegawa and Kroeker work well together because Sukegawa’s flash
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`memory reduces disk accesses during the boot process and thus allows the
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`loading of RAM to continue efficiently beyond the disk reset period.
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`
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`24. In Sukegawa, boot data that has been identified in a previous power-on/reset
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`cycle is preserved in two ways. First, the actual data is stored in flash memory
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`unit 1 (specifically, permanent storage area 10A and non-volatile cache area
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`10C). Second, the information about where the stored information resides on
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`disk and in the flash memory unit 1 is stored in management information table
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`3A [Sukegawa 5:5-9, 5:43-46, 5:58-63, see also discussion in Ex 1003 ¶¶28-34].
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`One of ordinary skill would have recognized that this arrangement is a type of
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`disk cache because Sukegawa describes it as such [Sukegawa 1:50-61]. In
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`Sukegawa the flash memory unit 1 corresponds to the RAM cache memory of a
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`conventional disk cache. The advantage of using the flash memory (non-volatile
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`memory) instead of conventional RAM (volatile memory) for the disk cache is
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`that the cache contents area available immediately upon power-on/reset, thus
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`saving considerable time during the boot process [Sukegawa 1:55-61].
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`25. Despite the advantage of using non-volatile memory, such as flash memory, in
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`Sukegawa, one of ordinary skill in the art would have understood that some of
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`the advantages described in Sukegawa could be obtained by using a volatile
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`13
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`memory, such as DRAM, for at least part of the memory storage requirements of
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`the flash memory unit 1. In fact, one of ordinary skill would have recognized
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`several very good reasons for doing this. First, in February of 2000 the cost of
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`DRAM was significantly less than the cost flash memory [Dye 1:35-38, 2:28-32].
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`Second, as Dye discloses, flash memory is slower to access than DRAM [Dye
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`‘069 1:53-59, 2:32-39]. Third, flash memory is significantly slower to write than
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`RAM.
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`
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`26. In my first declaration I discussed the following combinations of Sukegawa with
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`Dye and additional prior art: Sukegawa and Dye; Sukegawa, Dye, and Settsu;
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`Sukegawa, Dye, and Burrows; Sukegawa, Dye, Setsu, and Burrows; Sukegawa,
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`Dye, and Zwiegincew. In the discussion that follows I will demonstrate how one
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`of ordinary skill would have extended these combinations with the disclosure of
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`Kroeker. Beyond the details of this discussion, the additional combinations of
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`Sukegawa and Dye discussed previously are unaffected by the inclusion of
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`Kroeker. Thus, the analysis offered in my first declaration [APPLE-1003] would
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`be unaffected as to the dependent claims.
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`27. In February 2000, one of ordinary skill in the art would have been aware of the
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`cost, read access time and write access time characteristics of both flash memory
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`and DRAM. At that point in time flash memory would have been more
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`expensive than DRAM, and also slower. Of course, the non-volatile
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`characteristic of flash is an important advantage, and is used by Sukegawa to
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`preserve boot data over a power-on/reset cycle. Similarly, the contents of
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`management information table 3A must be preserved over power-on/reset
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`because it contains information about the location of data previously loaded into
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`the flash memory unit 1. Specifically, management information table 3A defines
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`which blocks of data have been read from the hard disk drive (HDD) 2, and
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`where those blocks are stored in the flash memory unit 3.
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`28. However, based on the better cost and performance characteristics of DRAM
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`relative to flash memory, one of ordinary skill in the art would have been
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`motivated to consider whether utilization of the expensive flash memory unit 1
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`might be reduced by using DRAM. Indeed, doing so would reduce the cost and
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`improve the read and write access time of the system, and a completely workable
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`approach is found in Kroeker. As I have explained above, the principle of
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`Kroeker is that information stored on a disk drive 16 may be loaded into a
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`DRAM based cache 18. Because the cache 18 is composed of DRAM this
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`loading must be done following power on because any contents of DRAM would
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`have been lost while power was off. Indeed, Kroeker makes use of exactly the
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`same approach as the ‘862 patent, namely loading data from a disk to a cache
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`during the period of time when the host computer is not yet fully initialized, but
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`the disk controller has come out of reset. [Kroeker 2:38-47, 3:58-64]. Thus,
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`DRAM can be used to augment the memory resources of Sukegawa in a way that
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`provides improved performance at reduced cost.
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`
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`29. Here are the details. In my first Declaration [APPLE-1003] I described a system
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`in which the basic structure of Sukegawa is combined with the compression
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`caching capability of Dye. To illustrate this combination, I presented the figure
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`shown below. [APPLE-1003, ¶87].
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`16
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`30. This figure simply shows the basic system of Sukegawa Fig. 1 in which the cache
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`
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`system controller 3 is extended with the data compression/decompression engine
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`of Dye (items 240, 260, 280). [APPLE-1003 ¶87]. The inclusion of the data
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`compression/decompression engine of Dye allows the system of Sukegawa to
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`take advantage of data compression to both reduce the amount of flash memory
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`required by flash memory unit 1 and to enhance the effective transfer rate
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`between the HDD (Hard Disk Drive) 2 of Sukegawa and the flash memory unit 1.
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`[see e.g., Dye Abstract, 3:23-28, 7:31-33, 17:19-38]. To accomplish this high
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`speed data compression and decompression Dye discloses a highly parallel
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`compression/decompression engine. [Dye Figs. 10B, 13, 14, 18:44-49, 18:60-
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`19:3021:30-35]. I have provided a summary of the Dye approach in a previous
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`Declaration. [APPLE-1003, ¶¶48-61]. Aside from improved effective storage
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`density, Dye also discloses that the high speed parallel data
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`compression/decompression engine also improves the effective bandwidth of the
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`disk to cache path because it allows data to be effectively transferred faster than
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`if the data was not compressed. [see, e.g., Dye 17:19-38]. I have discussed the
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`motivation to extend Sukegawa with the teachings of Dye in my previous
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`Declaration. [APPLE-1003, ¶¶ 87-91].
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`31. Based on the state of the art with respect to flash memory and DRAM in
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`
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`February of 2000, one of ordinary skill in the art would have been motivated to
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`extend the system of Sukegawa and Dye with the teachings of Kroeker. The
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`motivation would be to gain the advantage of cost and speed that DRAM would
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`provide. In considering the use of DRAM in a system such as Sukegawa
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`extended by Dye one of ordinary skill in the art would have understood that
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`DRAM does not retain its data contents after a power-off/power-on sequence
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`because this is common engineering knowledge.
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`
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`32. Thus, to use DRAM it is necessary to consider approaches that would effectively
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`preserve prefetched contents. One of ordinary skill, by simply reading the
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`abstract of Kroeker, would have understood that the disclosure of Kroeker solves
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`the problem. The key to Kroeker is that a description of the data to be prefetched
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`directly following power-on/reset is maintained in the prefetch table, which is
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`stored in a reserved area of disk (i.e. a type of non-volatile memory that does not
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`lose information during a power-off situation). [Kroeker 2:66-3:6, 5:22-33].
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`Functionally, the prefetch table of Kroeker is equivalent to the management
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`information table 3A of Sukegawa in that both describe the location and extent of
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`data stored on disk that is to be used following a power-on/reset. In the case of
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`18
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`Sukegawa this information is stored in the flash memory unit 1 because it, like
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`disk, flash memory is non-volatile. [Sukegawa 5:5-9].
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`33. The figure below is similar to the figure from my first Declaration [APPLE-1003
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`¶87], but further modified to show how a system of Sukegawa as extended by
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`Dye and Kroeker would be constructed.
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`34. In this figure I have shown the addition of DRAM to Sukegawa’s cache system
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`controller 3, which would have been straightforward for one of ordinary skill. In
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`the proposed system the DRAM would function just like the flash memory of
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`area 10A, although it would be faster and less expensive.
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`35. In the system of Sukegawa and Dye as enhanced by the disclosure of Kroeker
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`part of the management information table 3A could be assigned to perform the
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`function of the prefetch table in Kroeker. This is would be a straightforward
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`modification for one of ordinary skill in the art because the prefetch table of
`
`Kroeker and the management information table 3A of Sukegawa perform a
`
`nearly identical function. That function is storing information that indicates
`
`where a disk block (or a “record” in the terminology of Kroeker) is stored (or will
`
`be stored) in cache. [Sukegawa 5:5-9, 5:43-46, 5:58-63; Kroeker Abstract, 2:30-
`
`46, steps 30, 40].
`
`
`
`36. Operation of the system of Sukegawa and Dye would be as I have described in
`
`my previous Declaration [APPLE-1003, ¶¶85-91]. In this system as enhanced by
`
`Kroeker the only difference in operation would be that the DRAM added to
`
`Sukegawa’s system would be loaded from HDD 2 directly following the release
`
`of the reset signal, so that by the time the Host System 4 was ready to issue disk
`
`requests the DRAM would be filled with prefetched information identified in the
`
`management information table 3A.
`
`
`
`37. Sukegawa in view of Dye and Kroeker renders obvious all aspects of the
`
`amended independent claims. For the sake of brevity, I limit my discussion to
`
`
`
`20
`
`

`

`
`
`the amended language of substitute independent claim 118. In claim 118, the
`
`original language for “loading” has been amended to “preloading”. Additionally,
`
`the target of the “preloading” has been amended to a “volatile memory”, and
`
`“preloading” has been amended to occur “during the same boot sequence in
`
`which a boot device controller receives a command over a computer bus to load
`
`the portion of boot data.”
`
`
`
`38. Other aspects of the claim that remain unchanged include the type of data that is
`
`preloaded, namely, “boot data”, and the association of the “boot data” with a
`
`“boot data list”. I have discussed these aspects with respect to the combination of
`
`Sukegawa and Dye in my previous Declaration [APPLE-1003 ¶¶130-136] and
`
`that discussion applies here.
`
`
`
`39. In Kroeker, boot data is prefetched from the disk 16 to the volatile cache 18.
`
`This is done during the period following power-on/reset when the host computer
`
`14 is being reset. [Kroeker Abstract, 2:38-47, 3:9-18, Fig. 3, steps 28-29, 5:1-8,
`
`5:17-20, 5:40-50, Table 1]. One of ordinary skill in the art would have
`
`understood that the purpose in Kroeker of prefetching the disk information during
`
`host system reset is to provide this information to the host computer 14 (i.e. the
`
`host computer 4 of Sukegawa combination) for use immediately after the host
`
`
`
`21
`
`

`

`
`
`computer completes its reset. [Kroeker Abstract, 1:14-28, 3:58-64, 2:38-47].
`
`Thus, one of ordinary skill in the art would have understood that the system of
`
`Sukegawa and Dye as modified by Kroeker discloses “preloading” into volatile
`
`memory.
`
`
`
`40. Moreover, one of ordinary skill would have understood from Kroeker that
`
`preloading related to Fig. 3, steps 28-30 would be accomplished “by transferring
`
`the portion of the boot data” from the disk to the cache (i.e. the “memory’).
`
`Kroeker describes this explicitly. [Kroeker Abstract, 1:14-28, 2:38-47, Fig. 3,
`
`step 30, 5:17-20]. One of ordinary skill would further have understood that, in
`
`the system of Sukegawa as modified by Dye and Kroeker, boot data would be
`
`transferred in compressed form, for the reasons that I have discussed in my
`
`previous Declaration [see, e.g., APPLE-1003 ¶¶130-139]. Further, one of
`
`ordinary skill would have understood that, in this system, at least a “portion of
`
`boot data in compressed form” would be transferred into the DRAM.
`
`
`
`41. In the system of Sukegawa and Dye the “boot device controller” is the cache
`
`system controller 3. One of ordinary skill would have understood this because
`
`the HDD 2 is the boot device and the cache system controller 3 controls this
`
`device. [Sukegawa Fig. 1, item 3, 2:58-64]. In the system of Sukegawa and Dye
`
`
`
`22
`
`

`

`
`
`as modified by Kroeker the functions of the Kroeker onboard controller 20 would
`
`be incorporated into the cache system controller 3 of Sukegawa to the extent that
`
`those functions were not already included in Sukegawa cache controller 3.
`
`
`
`42. In the system of Sukegawa and Dye as modified by Kroeker one of ordinary skill
`
`would have understood that the cache system controller 3 “receives a command
`
`over a computer bus to load” data from HDD 2 (similar to Kroeker disk 16).
`
`This is described explicitly by Sukegawa and Kroeker. [Sukegawa Fig. 1, 4:25-
`
`30, Fig. 2, 4:38-46; Kroeker Fig. 1,1:23-28, 2:40-46]. Immediately after a
`
`power-on/reset these commands relate to the loading of “the boot data”.
`
`[Sukegawa 1:39-49, 1:55-61, 2:11-16, 6:49-58; Kroeker Abstract, 1:23-28, 2:38-
`
`47, 5:40-50].
`
`
`
`43. In the system of Sukegawa and Dye as modified by Kroeker the “preloading” of
`
`the DRAM occurs while the host computer 14 is in reset following a power-
`
`on/reset. One of ordinary skill would have understood this because this is shown
`
`explicitly in Kroeker. [Kroeker Abstract, Fig. 3 steps 26-30, 5:1-8, 5:17-20,
`
`Table 1]. Thus, one of ordinary skill would have understood that in Kroeker (and
`
`in the system of Sukegawa and Dye as enhanced by Kroeker) that “preloading
`
`
`
`23
`
`

`

`
`
`occurs during the same boot sequence in which a boot device controller receives
`
`a command over a computer bus to load the portion of boot data”.
`
`D.
`Sukegawa in view of Dye and Esfahani
`44. Sukegawa – as discussed above with respect to Sukegawa in view of Dye and
`
`Kroeker, one of ordinary skill would have found it obvious to make use of less
`
`costly volatile memory (e.g., RAM) in Sukegawa’s system when preloading boot
`
`data in a manner otherwise consistent with Sukegawa.
`
`
`
`45. Esfahani – Esfahani is directed toward booting a computer system in which an
`
`operating system includes a “low-level portion…stored in a relatively small read-
`
`only memory (ROM)” and an “intermediate-level portion…stored as a
`
`compressed ROM image on a disk” [Esfahani, Abstract]. As background,
`
`Esfahani described that a “computer's permanent read-only memory (ROM)…has
`
`traditionally…contained both low-level and high-level operating system (OS)
`
`code” [Esfahani, 1:14-26]. Esfahani explained that computers employed this
`
`design because “ROM was cheaper than random access memory (RAM), and the
`
`available disk space…was at a premium.” [Esfahani, 1:26-35]. As technology
`
`advanced, Esfahani recognized that operating system code “has expanded beyond
`
`the practical limits provided by ROMs” and that, “[t]oday, RAM and disk space
`
`
`
`24
`
`

`

`are inexpensive, have high capacity, and are fast compared to the ROM”
`
`
`
`[Esfahani, 1:36-41, 5:3-5].
`
`
`
`46. With these considerations in mind, Esfahani proposed a change to background
`
`systems that stored both low-level and high-level OS code in ROM. Specifically,
`
`Esfahani proposed storing low-level OS code “in a relatively small Boot ROM”
`
`and storing intermediate-level OS code “as a compressed ROM image on a disk”
`
`[Esfahani, 2:54-61]. “Upon power-up or reset of the computer system, the code
`
`in the boot ROM is executed to read the compressed ROM image into RAM,”
`
`which “is then decompressed and executed as part of the boot sequence.” Id.,
`
`2:63-67. With this “improved OS” where OS code is “separated into logically
`
`distinct pieces” and preloaded into both ROM and RAM, Esfahani realized
`
`several “benefits” [Esfahani, 4:38-5:21]. Notably, by reducing the size of ROM,
`
`“costs tend to be reduced” [Esfahani, 4:38-5:21].
`
`
`
`47. Combination - with this background, one of ordinary skill would have been
`
`motivated to achieve Esfahani’s benefits in Sukegawa. For instance, one of
`
`ordinary skill would have found Esfahani’s benefits directly applicable to
`
`Sukegawa’s system, and would therefore have been motivated to modify
`
`Sukegawa to preload OS data into both non-volatile and volatile memories as
`
`
`
`25
`
`

`

`
`
`discussed in Esfahani, so as “to reduce time to market, development costs, and
`
`manufacturing costs for computer systems.” Esfahani, 2:1-3.
`
`
`
`48. Specifically, to achieve Esfahani’s cost benefit, one of ordinary skill would have
`
`reduced utilization of Sukegawa’s flash memory 1 by preloading into flash
`
`memory 1 only those portions of the OS that are expected to be needed soon after
`
`power-on. Additionally, one of ordinary skill would have maintained portions
`
`expected to be

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