1
`
`APPLE 1024
`
`

`
`
`
`Programming Embedded Systems
`in C and C++
`
`é
`
`Michael Barr
`
`O5RE|LLY®
`Beg/tng- Cambridge - Famlmm v K0‘ln -Paris ~ Sebast0pol- Taipei - Tokyo
`
`2
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`Programming Embedded Systems in 0 and L'++
`by Michael Barr
`
`Copyright © 1999 O’Reilly & Associates, Inc. All rights reserved.
`Printed in the United States of America.
`
`Published by O’Reilly 8: Associates, Inc., 101 Morris Street, Sebastopol, CA 95472.
`
`ElIjI0t'.' Andy Oram
`
`Production Editor: Melanie Wang
`
`Printing History:
`
`January 1999:
`
`First Edition.
`
`Nutshell Handbook, the Nutshell Handbook logo, and the O’Reilly logo are registered
`trademarks of O’Reilly & Associates, Inc. The association between the image of ticks and the
`topic of embedded systems is a trademark of O’Reilly & Associates, Inc. Many of the
`designations used by manufacturers and sellers to distinguish their products are claimed as
`trademarks. Where those designations appear in this book, and O’Reilly & Associates, Inc. was
`aware of a trademark claim, the designations have been printed in caps or initial caps.
`
`While every precaution has been taken in the preparation of this book, the publisher assumes
`no responsibility for errors or omissions, or for damages resulting from the use of the
`information contained herein
`
`ISBN:
`[Ml
`
`1—56592—354~5
`
`[6/O0]
`
`3
`
`

`
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`I
`
`In this chapter:
`~ Types ofMe7no1y
`-‘Memory Testing
`- Validating Memory
`Contents
`
`V
`
`- Working with Flash
`Memam’
`
`l
`
`t’
`
`Memory
`
`Tyrell: If we give them or past, we create 51 ctts/yton for their
`emotions and, consequently, we can control tbetn better.
`Decletzrd: Memories. Yon’re tallatng about mem.orz'es.
`— the movie Blade Runner
`
`_
`
`In this chapter, you will learn everything you need to know about memory in
`embedded systems. In particular, you will learn about the types of memory you
`are likely to encounter, how to test memory devices to see if they are working
`properly, and how to use Flash memory.
`
`Types ofMemory
`
`Many types of memory devices are available for use in modern computer systems.
`As an embedded software ‘engineer, you must be aware of the differences between
`them and understand how to use each type effectively. In our discussion, we will
`approach these devices from a software viewpoint. As you are reading, try to keep
`in mind that the development of these devices took several decades and that there
`are significant physical differences in the underlying hardware. The names of the
`memory types frequently reflect the historical nature of the development process
`and are often more confusing than insightful.
`
`Most software developers think of memory as being either random—access (RAM)
`or read—only (ROM). But, in fact, there are subtypes of each and even a third class
`of hybrid memories. In a RAM device, the data stored at each memory location can
`be read or written, as desired. In a ROM device, the data stored at each memory
`location can be read at will, but never written. In some cases,
`it
`is possible to
`overwrite the data in a ROM-like device. Such devices are called hybrid memories
`because they exhibit some of the characteristics of both RAM and ROM. Figure 6-1
`
`57
`
`4
`
`

`
`
`
`
`
`58
`
`Chapter 6: Memoty
`
`provides a classification system for the memory devices that are commonly found
`in embedded systems.
`
`‘ S
`
`RAM
`
`NVRAM Flash
`
`EEPROM
`
`EPROM PROM Masked
`
`Figure 6-1 . Common memory types in embedded systems
`
`Types of RAM
`
`There are two important memory devices in the RAM family: SRAM and DRAM. The
`main difference between them is the lifetime of the data stored. SRAM (static RAM)
`retains its contents as long as electrical power is applied to the chip. However, if
`the power is turned off or lost temporarily then its contents will be lost forever.
`DRAM (dynamic RAM), on the other hand, has an extremely short data lifetime-
`usually less than a quarter of a second. This is true even when power is applied
`constantly.
`
`In short, SRAM has all the properties of the memory you think of when you hear
`the word RAM. Compared to that, DRAM sounds kind of useless. What good is a
`memory device that retains its contents for only a fraction of a second? By itself,
`such a Volatile memory is indeed worthless. However, a simple piece of hardware
`called a DRAM controller can be used to make DRAM behave more like SRAM.
`(See the sidebar “DRAM Controllers” later in this chapter.) The job of the DRAM
`controller is to periodically refresh the data stored in the DRAM. By refreshing the
`data several times a second, the DRAM controller keeps the contents of memory
`alive for as long as they are needed. So,
`is as useful as SRAM after all.
`
`When deciding which type of RAM to use, a system designer must consider access
`time and cost. SRAM devices offer extremely fast access times (approximately four
`times faster than DRAM) but are much more expensive to produce. Generally,
`SRAM is used only where access speed is extremely important. A lower cost per
`byte makes DRAM attractive whenever large amounts of RAM are required. Many
`embedded systems include both types: a small block of SRAM (a few hundred
`kilobytes) along a critical data path and a much larger block of DRAM (in the
`megabytes) for everything else.
`
`5
`
`

`
`
`
`Memory
`
`y found
`
`Vlasked
`
`AM. The
`
`ic RAM)
`
`vever, if
`forever.
`’etime—
`
`applied
`
`’ou hear
`:>od is a
`
`By itself,
`ardware
`3 SRAM.
`3 DRAM
`
`hing the
`memory
`11.
`
`sr access
`
`zely four
`enerally,
`cost per
`
`d. Many
`hundred
`
`(in the
`
`Types ofMemo1y
`
`59
`
`DRAM Controllers
`
`If your embedded system includes DRAM, there is probably a DRAM controller
`on board (or on—chip) as well. The DRAM controller is an extra piece of hard-
`ware placed between the processor and the memory chips. Its main purpose
`is to perform the refresh operations required to keep your data alive in the
`DRAM. However, it cannot do this properly without some help from you.
`
`One of the first things your software must do is initialize the DRAM controller.
`If you do not have any other RAM in the system, you must do this before cre-
`ating the stack or heap. As a result, this initialization code is usually written in
`assembly language and placed within the hardware initialization module.
`
`Almost all DRAM controllers require a short initialization sequence that consists
`of one or more setup commands. The setup commands tell the controller about
`the hardware interface to the DRAM and how frequently the data there must
`be refreshed. To determine the initialization sequence for your particular sys-
`tem, consult the designer of the board or read the databooks that describe the
`DRAM and DRAM controller. If the DRAM in your system does not appear to
`be working properly, it could be that the DRAM controller either is not initial-
`ized or has been initialized incorrectly.
`
`Types of ROM
`
`Memories in the ROM family are distinguished by the methods used to write new
`data to them (usually called programming) and the number of times they can be
`rewritten. This classification reflects the evolution of ROM devices from hardwired
`
`to one—time programmable to erasable-and—programmable. A common feature
`across all these devices is their ability to retain data and programs forever, even
`
`during a power failure.
`
`The very first ROMS were hardwired devices that contained a preprogrammed set
`of data or instructions. The contents of the ROM had to be specified before chip
`production, so the actual data could be used to arrange the transistors inside the
`chip! Hardwired memories are still used,
`though they are now called “masked
`ROMS” to distinguish them from other types of ROM. The main advantage of a
`masked ROM is a low production cost. Unfortunately, the cost is low only when
`hundreds of thousands of copies of the same ROM are required.
`
`One step up from the masked ROM is the PROM (programmable ROM), which is
`purchased in an unprogrammed state. If you were to look at the contents of an
`unprogrammed PROM, you would see that the data is made up entirely of 1’s. The
`process of writing your data to the PROM involves a special piece of equipment
`called a device programmer. The device programmer writes data to the device one
`
`6
`
`

`
`
`
`' 60
`
`r
`
`Chapter 6'Mem01y
`
`word at a time, by applying an electrical charge to the input pins of the chip.
`Once a PROM has been programmed in this way,
`its contents can never be
`changed. If the code or data stored in the PROM must be changed, the current
`device must be discarded. As a result, PROMS are also known as one—tz'me pro—
`grammable (OTP) devices.
`
`An EPROM (erasable—and—programmable ROM) is programmed in exactly the same
`manner as a PROM. However, EPROMs can be erased and reprogrammed repeat~
`edly. To erase an EPROM, you simply expose the device to a strong source of
`ultraviolet light. (There is a “window” in the top of the device to let the ultraviolet
`light reach the silicon.) By doing this, you essentially reset the entire chip to its ini-
`tial—-—unprogrammed——state. Though more expensive than PROMs, their ability to
`be reprogrammed makes EPROMs an essential part of the software development
`and testing process.
`
`, Hybrid Types
`
`As memory technology has matured in recent years, the line between RAM and
`ROM devices has blurred. There are now several types of memory that combine
`the best features of both. These devices do not belong to either group and can be
`collectively referred to as hybrid memory devices. Hybrid memories can be read
`and written as desired,
`like RAM, but maintain their contents without electrical
`power, just like ROM. Two of the hybrid devices, EEPROM and Flash, are descen~
`dants of ROM devices; the third, NVRAM, is a modified version of SRAM.
`
`EEPROMs -are electrically—erasable-and—programmable. Internally, they are similar
`to EPROMs, but the erase operation is accomplished electrically, rather than by
`exposure to ultraviolet
`light. Any byte within an EEPROM can be erased and
`rewritten. Once written, the new data will remain in the device forever——or at least
`until it is electrically erased. The tradeoff for this improved functionality is mainly
`higher cost. Write cycles are also significantly longer than writes to a RAM, so you
`wouldn’t want to*‘t1se an EEPROM for your main system memory.
`Flash memory is the most recent advancement in memory technology. It com-
`bines all the best features of the memory devices described thus far. Flash mem-
`ory devices are high density, low cost, nonvolatile, fast (to read, but not to write),
`and electrically reprogrammable. These advantages are overwhelming and the use
`of Flash memory has increased dramatically in embedded systems as a direct
`result. From a software viewpoint, Flash and EEPROM technologies are very simi-
`lar. The major difference is that Flash devices can be erased only one sector at a
`time, not byte by byte. Typical sector sizes are in the range of 256 bytes to 16
`kilobytes. Despite this disadvantage, Flash is much more popular‘ than EEPROM
`and is rapidly displacing many of the ROM devices as well.
`
`7
`
`

`
`
`
`Memory Testing
`
`61
`
`The third member of the hybrid memory class is NVRAM (nonvolatile RAM). Non-
`volatility is also a characteristic of the ROM and hybrid memories discussed ear-
`lier. However, an NVRAM is physically very different from those devices. An
`NVRAM is usually just an SRlAM with a battery backup. When the power is turned
`on, the NVRAM operates just like any other SRAM. But when the power is turned
`off, the NVRAM draws just enough electrical power from the battery to retain its
`current contents. NVRAM is fairly common in embedded systems. However,
`it is
`very eXpensive—even more expensive than SRAM—so its applications are typi-
`cally limited to the storage of only a few hundred bytes of system—critical informa-
`tion that cannot be stored in any better way.
`V
`
`Table 6-1 summarizes the characteristics of different memory types.
`
`Table 6-1. Memo7yDeu1'ce C/aazracteristics
`
`'Memor;y
`
`he chip.
`l€V€I‘
`be
`: current
`
`ime pro-
`
`‘he same
`
`1 repeat-
`ource of
`
`ltraviolet
`:0 its ini-
`
`ibility to
`elopment
`
`{AM and
`
`combine
`
`:1 can be
`be read
`electrical
`descen-
`
`e similar
`
`than by
`sed and
`r at least
`
`s mainly
`[, so you
`
`It com-
`
`sh mem-
`
`o write),
`1 the use
`a direct
`
`ery simi-
`ctor at a
`
`ies to 16
`EEPROM
`
`Memory
`Type
`SRAM
`
`DRAM
`Masked
`ROM
`
`PROM
`
`EPROM
`
`.
`Volatile? Writeable?
`yes
`yes
`
`yes
`no
`
`no
`
`no
`
`yes
`no
`
`i
`
`once, with
`programmer
`
`yes, with
`programmer
`
`EEPROM no
`
`yes
`
`Erase
`Size
`byte
`
`byte
`n/a
`
`Erase
`Cycles
`unlimited
`
`unlimited
`n/a
`
`Relative
`Cost
`expensive
`
`Relative
`Speed
`fast
`
`moderate
`inexpensive
`
`moderate
`fast
`
`n/a
`
`I n/a
`
`moderate
`
`entire
`chip
`
`byte
`
`limited (see moderate
`specs)
`
`limited (see
`specs)
`
`expensive
`
`Flash
`
`no
`
`yes
`
`sector
`
`'
`
`limited (see moderate
`specs)
`
`NVRAM
`
`no
`
`yes
`
`byte
`
`none
`
`expensive
`
`fast
`
`Memory Testing
`
`One of the first pieces of serious embedded software you are likely to write is a
`memory test. Once the prototype hardware is ready, the designer would like some
`reassurance that she has wired the address and data lines correctly and that the
`memory chips are working properly. At first this might seem like a fairly simple
`assignment, but as you look at the problem more closely you will realize that it
`can be difficult to detect subtle memory problems with a simple test. In fact, as a
`result of programmer naiveté, many embedded systems include memory tests that
`would detect only the most catastrophic memory failures. Some of these might not
`even notice that the memory chips have been removed from the board!
`
`fast
`
`fast
`
`fast to
`read, slow
`to write
`
`fast to
`read, slow
`to write
`
`8
`
`

`
`Chapter 6'Memo1y
`
`Direct Memory Access
`
`Direct memory access (DMA) is a technique for transferring blocks of data
`directly between two hardware devices. In the absence of DMA, the processor
`must read the data from one device and write it to the other, one byte or word
`at a time. If the amount of data to be transferred is large, or the frequency of
`transfers is high, the rest of the software might never get a chance to run. How-
`ever, if a DMA controller is present it is possible to have it perform the entire
`transfer, with little assistance from the processor.
`
`Here’s how DMA works. When a block of data needs to be transferred, the pro-
`cessor provides the DMA controller with the source and destination addresses
`and the total number of bytes. The DMA controller then transfers the data from
`the source to the destination automatically. After each byte is copied, each
`address is incremented and the number of bytes remaining is reduced by one.
`When the number of bytes remaining reaches zero, the block transfer ends and
`the DMA controller sends an interrupt to the processor.
`
`In a typical DMA scenario, the block of data is transferred directly to or from
`memory. For example, a network controller might want to place an incoming
`network packet into memory as it arrives, but only notify the processor once
`the entire packet has been received. By using DMA, the processor can spend
`more time processing the data once it arrives and less time transferring it
`between devices. The processor and DMA controller must share the address
`and data buses during this time, but this is handled automatically by the hard-
`ware and the processor is otherwise uninvolved with the actual transfer.
`
`The purpose of a memory test is to confirm that each storage location in a mem-
`ory device is working. In other words, if you store the number 50 at a particular
`address, you expect to find that number stored there until another number is Writ-
`ten. The basic idea behind any memory test, then, is to write some set of data val-
`ues to each address in the memory device and verify the data by reading it back. If
`all the values read back are the same as those that were written, then the memory
`device is said to pass the test. As you will see, it is only through careful selection .
`of the set of data values that you can be sure that a passing result is meaningful.
`
`Of course, a memory test like the one just described is unavoidably destructive. In
`the process of testing the memory, you must overwrite its prior contents. Because
`it is generally impractical to overwrite the contents of nonvolatile memories, the
`tests described in this section are generally used only for RAM testing. However, if
`the contents of a hybrid memory are unimportant——as they are during the product
`development stage—these same algorithms can be used to test those devices as
`well. The problem of Validating the contents of a nonvolatile memory is addressed
`in a later section of this chapter.
`
`9
`
`

`
`Memory
`
`Memmy Testing
`
`I
`
`63
`
`
`
`
`
`,...__.........i-u<«..uq_.«xu-mz.v,m.§»n~m.i...m...«_
`
`
`
`Common Memory Problems
`
`Before learning about specific test algorithms, you should be familiar with the
`types of memory problems that are likely to occur. One common misconception
`among software engineers is that most memory problems occur Within the chips
`themselves. Though a major issue at one time (a few decades ago), problems of
`this type are increasingly rare. The manufacturers of memory devices perform a
`variety of post—production tests on each batch of chips. If there is a problem with a
`particular batch,
`it is extremely unlikely that one of the bad chips will make its
`Way into your system.
`
`The one type of memory chip problem you could encounter is a catastrophic fail-
`ure. This is usually caused by some sort of physical or electrical damage received
`by the chip after manufacture. Catastrophic failures are uncommon and usually
`affect large portions of the chip. Because a large area is affected, it is reasonable to
`
`assume that catastrophic failure will be detected by any decent test algorithm.
`
`In my experience, a more common source of memory problems is the circuit
`board. Typical circuit board problems are:
`
`0
`
`Problems with the wiring between the processor and memory device
`
`0 Missing memory chips
`
`-
`
`Improperly inserted memory chips
`
`These are the problems that a good memory test algorithm should be able to
`detect. Such a test should also be able to detect catastrophic memory failures With-
`out specifically looking for them. So let’s discuss circuit board problems in more
`detail.
`
`Electrical wiring problems
`
`An electrical Wiring problem could be caused by an error in design or production
`of the board or as the result of damage received after manufacture. Each of the
`
`wires that connect the memory device to the processor is one of three types: an
`address line, a data line, or a control line. The address and data lines are used to
`
`select the memory location and to transfer the data, respectively. The control lines
`tell the memory device whether the processor wants to read or Write the location
`and precisely when the data will be transferred. Unfortunately, one or more of
`these wires could be improperly routed or damaged in such a Way that it is either
`shorted (i.e., connected to another Wire on the board) or open (not connected to
`anything). These problems are often caused by a bit of solder splash or a broken
`trace, respectively. Both cases are illustrated in Figure 6-2.
`‘
`
`Problems with the electrical connections to the processor will cause the memory
`device to behave incorrectly. Data might be stored incorrectly, stored at the wrong
`
`10
`
`data
`essor
`
`word
`
`cy of
`flow-
`zntire
`
`apro-
`esses
`
`fioni
`each
`one
`
`sand
`
`from
`
`ming
`once
`
`pend
`ng it
`dress
`aard-
`
`a mem-
`
`irticular
`is writ-
`
`lata val—
`back. If
`
`nemoiy
`election .
`
`lgful.
`
`ztive. In
`Secause
`
`ies, the
`ever, if
`
`product
`zices as
`
`dressed
`
`10
`
`

`
`
`
`64
`
`Chapter 6: Memory
`
`
`
`,raP:r,pi:esssorpo *
`
`= ris,issPra¢i9sisor
`
`a
`
`f
`
`T Shortediwire T
`
`T OpieinWire
`
`Figure 6-2. Possible wiring problems
`
`address, or not stored at all. Each of these symptoms can be explained by wiring
`problems on the data, address, and control lines, respectively.
`
`If the problem is with a data line, several data bits might appear to be “stuck
`together” (i.e., two or more bits always contain the same value, regardless of the
`data transmitted). Similarly, a data bit might be either “stuck high” (always 1) or
`“stuck low” (always 0). These problems can be detected by writing a sequence of
`data values designed to test that each data pin can be set to 0 and 1, indepen-
`dently of all the others.
`
`If an address line has a wiring problem, the contents of two memory locations
`might appear to overlap. In other words, data written to one address will instead
`overwrite the contents of another address. This happens because an address bit
`that is shorted or open will cause the memory device to see an address different
`from the one selected by the processor.
`
`Another possibility is that one of the control lines is shorted or open. Although it is
`theoretically possible to develop specific tests for control line problems, it is not
`possible to describe a general test for them. The operation of many control sig-
`nals is specific to the processor or memory architecture. Fortunately, if there is a
`problem with a control line, the memory will probably not work at all, and this
`will be detected by other memory tests. If you suspect a problem with a control
`line, it is best to seek the advice of the board’s designer before constructing a spe-
`cific test.
`
`Missing memory chips
`
`A missing memory chip is clearly a problem that should be detected. Unfortu-
`nately, because of the capacitive nature of unconnected electrical Wires, some
`
`11
`
`11
`
`

`
`
`
`6: Memory
`
`Memory Testing
`
`65
`
`by wiring
`
`be “stuck
`
`ass of the
`
`'ays 1) or
`quence of
`indepen-
`
`locations
`ill instead
`
`ddress bit
`; different
`
`tough it is
`, it is not
`
`>ntrol sig-
`there is a
`
`, and this
`a control
`
`.ng a spe~
`
`Unfortu~
`
`res, some
`
`memory tests will not detect this problem. For example, suppose you decided to
`use the following test algorithm: write the value 1 to the first location in memory,
`verify the value by reading it back, write 2 to the second location, verify the value,
`write 5 to the third location, verify, etc. Because each read occurs immediately after
`the corresponding write, it is possible that the data read back represents nothing
`more than the voltage remaining on the data bus from the previous write. If the
`data is read back too quickly, it will appear that the data has been correctly stored
`in memory——eVen though there is no memory chip at the other end of the bus!
`
`To detect a missing memory chip, the test must be altered. Instead of performing
`the verification read immediately after the corresponding write,
`it is desirable to
`perform several consecutive writes followed by the same number of consecutive
`reads. For example, write the value 1 to the first location, 2 to the second loca-
`tion, and 3 to the third location, then Verify the data at the first location, the sec-
`ond location, etc. If the data values are unique (as they are in the test just
`described), the missing chip will be detected: the first value read back will corre-
`spond to the last value written (5), rather than the first (1).
`
`Improperly inserted chips
`
`If a memory chip is present but improperly inserted in its socket, the system will
`usually behave as though there is a wiring problem or a missing chip. In other
`words, some number of the pins on the memory chip will either not be con-
`nected to the socket at all or will be connected at the wrong place. These pins will
`be part of the data bus, address bus, or control wiring. So as long as you test for
`wiring problems and missing chips, any improperly inserted chips will be detected
`automatically.
`
`Before going on, let’s quickly review the types of memory problems we must be
`able to detect. Memory chips only rarely have internal errors, but if they do, they
`are probably catastrophic in nature and will be detected by any test. A more com~
`mon source of problems is the circuit board, Where a wiring problem can occur or
`a memory chip might be missing or improperly inserted. Other memory problems
`can occur, but the ones described here are the most common and also the sim-
`plest to test in a generic way.
`
`Developing oz Test Strategy
`
`By carefully selecting your test data and the order in which the addresses are
`tested,
`it is possible to detect all of the memory problems described earlier. It is
`usually best to break your memory test
`into small, single-minded pieces. This
`helps to improve the efficiency of the overall test and the readability of the code.
`. More specific tests can also provide more detailed information about the source of
`the problem, if one is detected.
`
`12
`
`12
`
`

`
`
`
`66
`
`Chapter 6'Memo1y
`
`I have found it is best to have three individual memory tests: a data bus test, an
`address bus test, and a device test. The first two test for electrical wiring problems
`and improperly inserted chips; the third is intended to detect missing chips and
`catastrophic failures. As an unintended consequence,
`the device test will also
`uncover problems with the control bus wiring,
`though it cannot provide useful
`information about the source of such a problem.
`
`The order in which you execute these three tests is important. The proper order is:
`data bus test first, followed by the address bus test, and then the device test. That’s
`
`because the address bus test assumes a working data bus, and the device test
`results are meaningless unless both the address and data buses are known to be
`
`good. If any of the tests fail, you should work with a hardware engineer to locate
`the source of the problem. By looking at the data Value or address at which the
`
`test failed, she should be able to quickly isolate the problem on the circuit board.
`
`Data bus test
`
`The first thing we want to test is the data bus wiring. We need to confirm that any
`value placed on the data bus by the processor is correctly received by the mem-
`ory device at the other end. The most obvious way to test that is to write all possi;
`ble data Values and verify that the memory device stores each one successfully.
`However, that is not the most efficient test available. A faster method is to test the
`
`bus one bit at a time. The data bus passes the test if each data bit can be set to O
`and 1, independently of the other data bits.
`
`A good way to test each bit independently is to perform the so—called “walking 1’s
`test.” Table 6-2 shows the data patterns used in an 8-bit version of this test. The
`name, walking 1’s, comes from the fact
`that a single data bit is set
`to 1 and
`“walked” through the entire data word. The number of data values to test is the
`
`same as the width of the data bus. This reduces the number of test patterns from
`2" to n, where 72. is the width of the data bus.
`
`Table 6-2. Consectmfve Dara Valuesfor tlae W/al/ezfng Z ’s Test
`
`00000001
`
`00000010
`
`00000100
`
`00001000
`
`00010000
`
`00100000
`
`01000000
`
`10000000
`
`13
`
`13
`
`

`
` z E
`
`Memory Testing
`
`67
`
`Because We are testing only the data bus at this point, all of the data values can be
`written to the same address. Any address Within the memory device Will do. How~
`ever, if the data bus splits as it makes its Way to more than one memory chip, you
`will need to perform the data bus test at multiple addresses, one Within each chip.
`
`To perform the Walking 1’s test, simply Write the first data value in the table, ver-
`ify it by reading it back, Write the second value, verify, etc. When you reach the
`end of the table, the test is complete. It is okay to do the read immediately after
`the corresponding write this time because we are not yet looking for missing
`chips. In fact, this test may provide meaningful results even if the memory chips
`are not installed!
`
`The function memTestDataBus shows how to implement the walking 1’s test in C.
`It assumes that the caller will select the test address, and tests the entire set of data
`
`values at that address. If the data bus is working properly, the function will return
`0. Otherwise it will return the data value for which the test failed. The bit that is
`
`set in the returned value corresponds to the first faulty data line, if any.
`
`typedef unsigned char datum;
`
`/* Set the data bus width to 8 bits. */
`
`/**********************************************************************
`*
`
`* Function:
`
`mem‘I‘estDataBus()
`
`* *
`
`Description: Test the data bus wiring in a memory region by
`performing a walking 1's test at a fixed address
`within that region. The address (and hence the
`memory region)
`is selected by the caller.
`
`Notes:
`
`Returns:
`
`0 if the test succeeds.
`A nonzero result is the first pattern that failed.
`
`*
`*
`*
`
`* *
`
`* *
`
`* * *
`
`*********************************************************************/
`datum
`mem'I‘estDataBus(volatile datum * address)
`(
`
`datum pattern;
`
`/*
`* Perform a walking 1's test at the given address.
`*/
`
`for (pattern = 1; pattern != 0; pattern <<= 1)
`{
`
`/*
`* Write the test pattern.
`*/
`*address = pattern;
`
`14
`
`Memory
`
`test, an
`‘oblems
`
`lps and
`ill also
`: useful
`
`>rder is:
`1. That’s
`ice test
`
`n to be
`) locate
`rich the
`
`Joard.
`
`zhat any
`e mem—
`
`ll possi;
`essfully.
`test the
`set to 0
`
`king 1’s
`est. The
`
`> 1 and
`at is the
`ns from
`
`14
`
`

`
`
`
`68
`
`Chapter 6: Memory
`
`/*
`* Read it back (immediately is okay for this test).
`*/
`if (*address I= pattern)
`{
`
`return (pattern) ;
`
`l
`
`} r
`
`eturn (0) ;
`
`)
`
`/* memTestDataBus() */
`
`Address bus test
`
`the
`test
`the data bus works properly, you should next
`After confirming that
`address bus. Remember that address bus problems lead to overlapping memory
`locations. There are many possible addresses that could overlap. However, it is not
`necessary to check every possible combination. You should instead follow the
`example of the previous data bus test and try to isolate each address bit during
`testing. You simply need to confirm that each of the address pins can be set to O
`and 1 without affecting any of the others.
`
`The smallest set of addresses that will cover all possible combinations is the set of
`“power—of-two” addresses. These addresses are analogous to the set of data Values
`used in the walking 1’s test. The corresponding memory locations are 00OO1h,
`0O002h, O0OO4h, O0008h, OOO10h, 00O20h, and so forth. In addition, address O0OO0h
`
`must also be tested. The possibility of overlapping locations makes the address
`bus test harder to implement. After writing to one of the addresses, you must
`check that none of the others has been overwritten.
`
`It is important to note that not all of the address lines can be tested in this way.
`Part of the address—the leftmost bits—selects the memory chip itself. Another
`part—-the rightmost bits—might not be significant if the data bus width is greater
`than 8 bits. These extra bits will remain constant throughout the test and reduce
`the number of test addresses. For example, if the processor has 20 address bits, as
`the 80188EB does, then it can address up to 1 megabyte of memory. If you want
`to test a 128~kilobyte block of memory, the three most significant address bits will
`remain constant.* In that case, only the 17 rightmost bits of the address bus can
`actually be tested.
`
`To confirm that no two memory locations overlap, you should first write some ini-
`tial data value at each power-of—two offset within the device. Then write a new
`value-—an inverted Copy of the initial value is a good choice—to the first
`test
`
`* 128 kilobytes is one—eighth of the total 1—megabyte address space.
`
`15
`
`15
`
`

`
`Memory
`
`Memory Testing
`
`69
`
` l i :
`
`3l l
`
`
`
`._____mwWh..mmwmmm_Mmm
`
`offset, and verify that the initial data Value is still stored at every other power—of-
`two offset. If you find a location (other than the one just written) that contains the
`new data Value, you have found a problem with the current address bit. If no
`overlapping is found, repeat the procedure for each of the remaining offsets.
`
`The function memTestAddressBus shows how this can be done in practice. The
`function accepts two parameters. The first parameter is the base address of the
`memory block to be tested, and the second is its size, in bytes. The size is used to
`determine which address bits should be tested. For best results, the base address
`should contain a 0 in each of those bits. If the address bus test fails, the address at
`which the first error was detected will be returned. Otherwise, the function returns
`NULL to indicate success.
`
`l**********************************************************************
`>('
`O WH.O33
`
`memTestAddressBus()
`
`Description: Test the address bus wiring in a memory region by
`performing a walking 1's test on the relevant bits
`of the address and checking for aliasing.
`The test
`will find single—bit address failures such as stuck
`—high, stuck—low, and shorted pins.
`The base address
`and size of the region are