throbber
Attorney Docket No.: 37307-0006IP1
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Hermann Ruckerbauer
`In re Patent of:
`6,438,057
`US Patent No.:
`August 20, 2002
`Issue Date:
`Appl. Serial No.: 09/900,626
`§ 371 (c)(1) Date: July 6, 2001
`Title:
`DRAM REFRESH TIMING ADJUSTMENT DEVICE,
`SYSTEM AND METHOD
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`Attorney Docket No.: 37307-0006IP1
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`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`DECLARATION OF VIVEK SUBRAMANIAN
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`I, Vivek Subramanian, declare as follows:
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`I.
`1.
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`Introduction.
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`I am making this declaration at the request of the Real Party in Interest
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`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
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`Patent No. 6,438,057 (the “ʼ057 Patent”).
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`2.
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`I am being compensated for my work. My compensation does not depend
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`on the outcome of this proceeding.
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`3.
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`I have been asked to consider whether certain references disclose or render
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`obvious the claims of the ʼ057 Patent, either alone or in combination with each
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`other.
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`KINGSTON 1005
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`I have been advised that a patent claim may be invalid as obvious if the
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`Attorney Docket No.: 37307-0006IP1
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`4.
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`differences between the subject matter patented and the prior art are such that the
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`subject matter as a whole would have been obvious at the time of the invention to a
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`person having ordinary skill in the art. I have also been advised that several factual
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`inquiries underlie a determination of obviousness. These inquiries include the
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`scope and content of the prior art, the level of ordinary skill in the field of the
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`invention, the differences between the claimed invention and the prior art, and any
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`objective evidence of non-obviousness.
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`5.
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`I have been advised that objective evidence of non-obviousness directly
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`attributable to the claimed invention, known as “secondary considerations of non-
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`obviousness,” may include commercial success, satisfaction of a long-felt but
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`unsolved need, failure of others, copying, skepticism or disbelief before the
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`invention, and unexpected results. I am not aware of any such objective evidence
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`of non-obviousness that is directly attributable to the subject matter claimed in the
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`ʼ057 Patent at this time.
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`6.
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`In addition, I have been advised that the law requires a “common sense”
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`approach of examining whether the claimed invention is obvious to a person skilled
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`in the art. For example, I have been advised that combining familiar elements
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`according to known methods is likely to be obvious when it does no more than
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`yield predictable results. I have further been advised that this is especially true in
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`instances where there are a limited numbers of possible solutions to technical
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`Attorney Docket No.: 37307-0006IP1
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`problems or challenges.
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`7.
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`I have been informed that all claims of the ʼ057 Patent are subject to this
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`inter partes review.
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`II. Materials Reviewed
`8.
`In forming the opinions I express below, I considered my own knowledge of
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`the art in addition to at least the references below:
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`a. The ʼ057 Patent
`b. The File History of the ʼ057 patent (“ʼ057 file history”)
`c. U.S. Patent 5,784,328 to Irrinki (“Irrinki”)
`d. U.S. Patent 3,851,316 to Kodama (“Kodama”)
`e. U.S. Patent 4,970,497 to Broadwater (“Broadwater”)
`f. Computer Organization and Design by Patterson and Hennessy
`(Morgan Kaufmann Publishers, Inc., 1994)
`g. U.S. Patent 5,278,796 to Tillinghast (“Tillinghast”)
`h. U.S. Patent 6,134,167 to Atkinson (“Atkinson”)
`i. U.S. Patent 5,229,970 to Lee (“Lee ’970”)
`j. Japanese Patent 63-304499 to NEC Corporation (“JPS 499”)
`k. “Low Power Self Refresh Mode DRAM with Temperature
`Detecting Circuit,” by Kagenishi (“Kagenishi paper”)
`l. U.S. Patent 6,134,667 to Suzuki (“Suzuki”)
`m. U.S. Patent 3,812,717 to Miller (“Miller”)
`n. U.S. Patent 5,680,359 to Jeong (“Jeong”)
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`Attorney Docket No.: 37307-0006IP1
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`III. Qualifications
`9.
`I summarize my relevant knowledge and experience below. My Curriculum
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`Vitae contains additional information and is attached as Exhibit 1017.
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`10. I received a B.S. in electrical engineering from Louisiana State University in
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`1994, an M.S. in electrical engineering from Stanford University in 1996, and a
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`Ph.D. in electrical engineering from Stanford University in 1998.
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`11. I co-founded Matrix Semiconductor, Inc. in 1998 to develop high density
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`memory technology.
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`12. I have been teaching in the Electrical Engineering and Computer Sciences
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`Department at the University of California, Berkeley since 2000. I was an
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`Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to 2011,
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`and a Professor from 2011 to the present.
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`13. I have been an adjunct professor at the Sunchon National University in
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`Sunchon, Korea since 2009, leading research in printed electronics.
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`14. I have been an independent consultant in the semiconductor industry since
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`2000, focusing on memory technology, flexible electronics, and RFID technology.
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`15. I have published more than 200 technical papers in journals and at
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`conferences.
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`16. I am a named inventor on over 40 U.S. patents, many of which are in the
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`field of memory design.
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`IV. Person of Ordinary Skill in the Art and State of The Art
`17. In my opinion, a person of ordinary skill in the art as of the time of the ʼ057
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`Patent would have a Master’s degree in Electrical Engineering and 2-5 years of
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`experience working in the field of semiconductor memory design. I believe this to
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`be a reasonable statement of the level of ordinary skill in the art for the patent and
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`claims at issue. I also believe that I was one of ordinary skill in the art through my
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`education and work experience during the time that I was in University.
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`18. The opinions that I provide in this declaration are consistent with the
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`knowledge and experience of one of ordinary skill in the art at the priority date of
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`the ʼ057 Patent.
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`19. At the time of the ʼ057 Patent’s priority date, those of ordinary skill in the
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`art recognized that temperature and the refresh timing rate of a DRAM memory are
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`related. Power could be saved by increasing or decreasing the refresh rate of
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`DRAM based on the temperature. Ex. 1003 at 2:65-3:3; Ex. 1013 at 1; see also
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`Ex. 1004, Ex. 1016
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`20. It was also well known that the temperature of the DRAM array could be
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`detected by placing a temperature sensor on the DRAM semiconductor die itself
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`(i.e., on-chip). Ex. 1003 at 3:21-30.
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`21. At the time of the ʼ057 Patent’s priority date, those of ordinary skill in the
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`art recognized that on-chip temperature sensors could use external circuitry to send
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`the temperature of the DRAM array to external components. Ex. 1011 generally
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`and at 4:19-26.
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`22. The ability for a circuit to detect a temperature and then output the
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`temperature is simply a digital thermometer, which is something that has been
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`around since at least the 1970’s.
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`23. At the time of the ʼ057 patent’s priority date, it was well known in the art
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`that DRAM memory could be packaged with an on-board temperature sensor,
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`which could be used by the DRAM array to vary the refresh rate. Ex. 1010 at
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`3:21-30.
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`24. It was also known that on-chip temperature readings could be sent off a chip
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`for external use. Ex. 1011 generally and at 4:19-26.
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`V. Overview of the ʼ057 Patent
`25. The ʼ057 Patent relates to a DRAM refresh timing adjustment device,
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`system, and method. Ex. 1001 at Abstract.
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`26. The specification discloses that, “[p]referably, the DRAM array is refreshed
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`at a rate that varies in response to the signal.” Ex. 1001 at 2:31-32. Additionally,
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`the DRAM array and the temperature sensor are disposed in a semiconductor
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`package, “the package including at least one connection pin 117 operable to
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`provide the signal on line 116 to external circuitry, such as the refresh unit.” Id. at
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`4:49-53. In accordance with the alleged invention, “the DRAM array 112,
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`temperature sensor 110, and the refresh unit 104” can be “integrated in the same
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`27. semiconductor package such that external circuitry is not required to perform
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`the refresh function.” Id. at 4:53-57.
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`28. As demonstrated in Figure 2 (depicted below), the relationship between the
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`temperature of the DRAM array and the preferred refresh rate of the DRAM array
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`is a linear function, and while it may not always be linear, the relationship “will
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`exhibit a positive slope.” Ex. 1001 at Fig. 2, 3:66-4:6. The alleged invention uses
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`this known relationship “to reduce power consumption of the DRAM array (and
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`any associated circuitry) and improve overall system bandwidth.” Id. at 4:7-10.
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`29. The alleged invention prefers that the temperature sensor is a diode, but
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`Attorney Docket No.: 37307-0006IP1
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`“various other temperature sensing devices and techniques may be employed, such
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`as the use of one or more thermocouples, thermistors, etc.” Ex. 1001 at 5:32-36.
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`VI. Prior Art References
`Atkinson
`30. I have been advised, and my understanding is, that U.S. Patent 6,134,167 to
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`Atkinson (“Atkinson”) is eligible to serve as prior art for the ʼ057 Patent under 35
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`U.S.C. § 102(a) and §102(e). Atkinson was filed on June 4, 1998 and was issued
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`October 17, 2000. See Ex. 1010. Based on my review of the ʼ057 Patent file
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`history, Atkinson was not cited by the USPTO or considered by the Examiner
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`during prosecution of the ʼ057 Patent. See Ex. 1008.
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`Broadwater
`31. I have been advised, and my understanding is, that U.S. Patent 4,970,497 to
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`Broadwater (“Broadwater”) is eligible to serve as prior art for the ʼ057 Patent
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`under 35 U.S.C. § 102(a) and § 102(b). Broadwater was filed in November 1989
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`and issued November 13, 1990. Ex. 1006. Based on my review of the ʼ057 Patent
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`file history, Broadwater was not cited by the USPTO or considered by the
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`Examiner during prosecution of the ʼ057 Patent. See Ex. 1008.
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`Tillinghast
`32. I have been advised, and my understanding is, that U.S. Patent 5,278,796 to
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`Tillinghast (“Tillinghast”) is eligible to serve as prior art for the ʼ057 Patent under
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`35 U.S.C. § 102(a) and § 102(b). Tillinghast was filed April 12, 1991 and issued
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`Attorney Docket No.: 37307-0006IP1
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`January 11, 1994. Ex. 1009. Based on my review of the ʼ057 Patent file history,
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`Tillinghast was cited by the Examiner during prosecution of the ʼ057 Patent, but
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`not in connection with Broadwater. See Ex. 1008.
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`Kodama
`33. I have been advised, and my understanding is, that U.S. Patent 3,851,316 to
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`Kodama (“Kodama”) is eligible to serve as prior art for the ʼ057 Patent under 35
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`U.S.C. § 102(a) and § 102(b). Kodama was filed April 13, 1973 and issued
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`November 26, 1974. Ex. 1004. Based on my review of the ʼ057 Patent file
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`history, Kodama was not cited by the USPTO or considered by the Examiner
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`during prosecution of the ʼ057 Patent. See Ex. 1008.
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`Lee ʼ970
`34. I have been advised, and my understanding is, that U.S. Patent 5,299,970 to
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`Lee (“Lee ʼ970”) is eligible to serve as prior art for the ʼ057 Patent under 35
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`U.S.C. § 102(a) and § 102(b). Lee ʼ970 was filed April 15, 1991 and issued July
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`20, 1993. Ex. 1011. Based on my review of the ʼ057 Patent file history, Lee ʼ970
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`was not cited by the USPTO or considered by the Examiner during prosecution of
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`the ʼ057 Patent. See Ex. 1008.
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`JPS 499
`35. I have been advised, and my understanding is, that Japanese Patent JPS 63-
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`304499 to NEC Corporation (“JPS 499”) is eligible to serve as prior art for the
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`ʼ057 patent under 35 U.S.C. § 102(a) and § 102(b). JPS 499 issued December 12,
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`Attorney Docket No.: 37307-0006IP1
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`1988. Ex. 1012. Based on my review of the ʼ057 patent file history, JPS 499 was
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`not cited by the USPTO or considered by the Examiner during prosecution of the
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`ʼ057 patent. See Ex. 1008.
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`Kagenishi Paper
`36. I have been advised, and my understanding is, that the paper “Low Power
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`Self Refresh Mode DRAM with Temperature Detecting Circuit,” by Kagenishi
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`(“Kagenishi paper”) is eligible to serve as prior art for the ʼ057 patent. Kagenishi
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`paper published May 19, 1993. Ex. 1013. Based on my review of the ʼ057 patent
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`file history, Kagenishi paper was not cited by the USPTO or considered by the
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`Examiner during prosecution of the ʼ057 patent. See Ex. 1008.
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`Jeong
`37. I have been advised, and my understanding is, that U.S. Pat. 5,680,359 to
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`Jeong (“Jeong,” Ex. 1016) is eligible to serve as prior art for the ʼ057 patent.
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`Jeong was filed March 21, 1996, has a priority date of March 24, 1995 and was
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`issued October 21, 1997. Ex. 1016. Based on my review of the ʼ057 patent file
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`history, Jeong was not cited by the USPTO or considered by the Examiner during
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`prosecution of the ʼ057 patent. See Ex. 1008.
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`VII. Certain References Disclose And/Or Render Obvious All Claims of the
`ʼ057 Patent
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`A. Atkinson Renders Obvious All Elements of Claims 1-17 of the
`ʼ057 Patent
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`38. Atkinson teaches a method and apparatus for reducing “battery drain without
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`incurring a substantial penalty in user time or computer resources.” Ex. 1010 at
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`5:47-48. “The refresh logic provides a periodic refresh signal having a frequency
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`that may be varied according to the temperature of the memory device.” Id. at 5:63-
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`65. Atkinson uses, as one example, a temperature sensor that is a thermistor
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`coupled to a capacitor and an invertor. Id. at 7:35-36. “[T]he invertor provides a
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`refresh signal that continuously decreases as the memory temperature decreases and
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`continuously increases as the memory temperature increases.” Id. at 7:41-44.
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`39. Atkinson also discloses a “temperature-sensitive frequency generator []
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`incorporated into main memory, resulting in a self-refreshing memory device[,]”
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`illustrated in Figure 9, where “main memory” “preferably comprises DRAM
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`circuitry[.]” Ex. 1010 at Fig. 9, 7:46-48, 23:32-34, 24:22-25.
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`1.
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` Claim 1
`a. An apparatus, comprising:
`40. Atkinson discloses an apparatus, namely a main memory with a temperature
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`sensor. See Claim 1 limitations set forth below.
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`b. a semiconductor package including at least one
`connection pin;
`41. Atkinson discloses a semiconductor package, as one of ordinary skill in the
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`art would know that SDRAM and Rambus DRAM are packaged semiconductor
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`chips. Ex. 1010 at 8:65-9:5. Additionally, in describing DRAM operation,
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`Attorney Docket No.: 37307-0006IP1
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`Atkinson points one of ordinary skill in the art to Computer Organization and
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`Design by Patterson and Hennessy (Morgan Kaufmann Publishers, Inc., 1994) (Ex.
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`1007), which illustrates DRAM packaged chips. See Ex. 1010 at 4:31-35.
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`42. The packaged memory of Atkinson includes at least one connection pin, as
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`Atkinson discloses that main memory 106 is connected to a memory bus 110. Ex.
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`1010 at 12:4-7; see also id. at 23:32-37 (main memory 906). One of ordinary skill
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`in the art would appreciate that the connections to the memory bus 110 would
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`include at least one connection pin, or it would be obvious to have at least one
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`connection pin.
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`c. at least one dynamic random access memory
`(DRAM) array disposed within the package; and
`43. Atkinson disclose a package that contains at least one DRAM array. Ex.
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`1010 at Figs. 1, 4A, 5, 7-9, 5:57-62, 8:62-9:15. In Atkinson, the package is a
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`computer system where the main memory 106 includes an array of memory
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`devices such as DRAM. See id. at 8:37-9:15.
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`d. at least one temperature sensor in thermal
`communication with the DRAM array, operable to
`produce a signal indicative of a temperature of the
`DRAM array,
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`44. Atkinson discloses a temperature sensor that is in thermal communication
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`with the DRAM array, operable to produce a signal indicative of the temperature
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`of the DRAM array. Atkinson discloses several variants that satisfy this element.
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`First, Figure 8 (depicted below) depicts a refresh generator 850 that includes a
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`Thermistor 800. Ex. 1010 at Fig. 8, 22:39-67. Atkinson describes, “as the
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`thermistor [800] resistance R increases in response to a decrease in memory
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`temperature, the resulting decrease in the time constant value 1/RC lowers the
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`frequency of the refresh signal.” Id. at 22:52-62. Therefore, the refresh signal
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`produced by the refresh generator is indicative of the memory temperature (i.e., the
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`DRAM array temperature) where a decrease in memory temperature decreases the
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`frequency of the refresh signal. Id.
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`45. Atkinson also discloses that the thermistor 800 “is integrated within main
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`memory 906 and thus directly senses the temperature of the memory device.” Ex.
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`1010 at 24:1-26. This embodiment uses main memory 906, but Atkinson explains
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`that “[m]ain memory 906 represents an alternative embodiment of main memory
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`106 that preferably comprises DRAM circuitry, although main memory 906 may
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`also represent a single inline memory module 35 (SIMM), dual inline memory
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`module (DIM), or other circuit card containing memory devices.” Ex. 1010 at
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`23:32-37. Thus, the temperature sensor (element 800) of Atkinson is in thermal
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`communication with the DRAM array (main memory 906) of Atkinson.
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`46. Atkinson also discloses an embodiment where an off-the-shelf temperature
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`sensor is used. Ex. 1010 at 23:5-19 (“[A] voltage controlled oscillator combined
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`with a temperature sensor could replace the refresh generator 850 in FIG. 8. An
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`example of a suitable temperature sensor is the series BR11 Thermobead
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`manufactured by Thermometric AB[.]”). In this embodiment, “the temperature
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`sensor couples to main memory 106, providing a voltage to the VCO that
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`represents the main memory temperature. In response, the VCO produces the
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`refresh signal at the proper frequency for refreshing main memory 106.” Id.; see
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`also id. at Abstract, 6:51-62, 7:46-48. The refresh logic uses the temperature
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`sensor to assert the refresh signal based on the memory temperature. Id. at 6:46-
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`e.
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`coupled to the at least one connection pin such that
`the signal may be provided to external circuitry,
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`49.
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`47. Atkinson discloses that “the temperature sensor couples to main memory
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`106, providing a voltage to the VCO that represents the main memory
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`temperature.” Ex. 1010 at Fig. 8, 23:15-17. The refresh signal (which as shown
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`above indicates temperature of the memory) is provided to the Bridge Logic Unit
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`104. Id. at Fig. 8, 22:39-23:3. While the on-chip embodiment of Atkinson is not
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`described as providing the temperature indicative signal to any external circuitry,
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`such a modification would be obvious to one of ordinary skill in the art. As
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`Atkinson notes, “the embodiments of the invention described above enable a
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`computer system to consume a minimum quantity of power during suspended
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`operation by lowering the memory refresh rate in response to decreases in
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`operating temperature.” Id. at 24:40-45.
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`48.
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` One of ordinary skill in the art would understand that the temperature of the
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`DRAM can affect the overall temperature of a computer, and it is desirable for the
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`system or an outside sensor to be aware of the temperature for thermal
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`management reasons. For example, it may be desirable to communicate the
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`DRAM temperature externally to a fan or other cooling system to enable
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`engagement of that fan or cooling system at higher memory temperature. See Ex.
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`1014 (U.S. Patent 3,812,717 to Miller) at Abstract.
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`49. One of ordinary skill in the art would be motivated to make the signal
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`indicative of memory temperature external on a connection pin, at least to enable
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`its use in a cooling regime, such as the one set forth in Ex. 1014 (Miller). It would
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`also be desirable to make the temperature indicative signal external via a
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`connection pin, to enable throttling of power to reduce heat as well as to monitor
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`and track the memory temperature for diagnostic purposes—all well-known
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`aspects of the art prior to the ʼ057 Patent. See generally Ex. 1006 (Broadwater).
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`f. wherein the DRAM array is refreshed at a rate that
`decreases as the temperature of the DRAM array
`decreases and that increases as the temperature of
`the DRAM array increases.
`50. Atkinson discloses a DRAM array where, if the temperature of the main
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`memory drops, the temperature sensor responds by “asserting the select signal,
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`causing the refresh logic [] to reduce the rate of the refresh signal.” Ex. 1010 at
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`22:2-7; see also id. at Abstract, Figs. 7-9, 13:13-15. Atkinson describes that “the
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`inverter provides a refresh signal that continuously decreases as the memory
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`temperature decreases and continuously increases as the memory temperature
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`increases.” Id. at 7:41-44.
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`51. Atkinson also discloses the refresh generator generating a periodic refresh
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`signal having a frequency proportional to 1/RC where R is the resistance of the
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`thermistor and C is the capacitance of the capacitor. Ex. 1010 at 24:3-11. The
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`refresh frequency decreases approximately in proportion to the decrease in the
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`temperature of DRAM. Id. at 24:14-17. It follows that the refresh frequency
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`would conversely increase approximately in proportion to the increase in
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`temperature of DRAM. See id. at Figs. 4B, 6. Atkinson points out that the greatest
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`power savings can be achieved by monitoring the temperature of main memory
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`and keeping the refresh rate as close as possible to the curve of Figure 6 (depicted
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`below). Id. at 20:53-56.
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`2. Claim 2
`a. The apparatus of claim 1, wherein the at least one
`temperature sensor includes at least one diode
`having a forward voltage drop that varies as a
`function of the temperature of the DRAM array,
`and the signal corresponds to the forward voltage
`drop of the at least one diode.
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`52. The ʼ057 Patent includes a diode as one type of temperature sensing devices.
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`Attorney Docket No.: 37307-0006IP1
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`Ex. 1001 at 2:42-45. Like the ʼ057 Patent, Atkinson explains that “[i]t should be
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`noted that numerous other devices and methods exist for determining the
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`temperature of main memory 106, such as a thermocouple or temperature sensing
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`integrated circuit.” Ex. 1010 at 22:21-24.
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`53. Those of ordinary skill at the time of the filing of the ʼ057 Patent would
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`know that one example of finite alternate types of integrated circuit for detecting
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`temperature is a diode having a forward voltage drop that varies as a function of
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`temperature. For example, Miller from 1974 describes a semiconductor diode
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`“temperature measuring apparatus” in which “[t]he temperature reading is made by
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`measurement of the forward voltage drop across the diode.” Ex. 1015 at Abstract.
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`There is nothing inventive about using this known type of temperature sensor, and
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`it would be obvious for a person of ordinary skill to have selected a diode.
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`Atkinson even notes, “[n]umerous variations and modifications will become
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`apparent to those skilled in the art once the above disclosure is fully
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`appreciated”—making the use of well-known type of temperature sensor all the
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`more obvious. See Ex. 1010 at 24:63-65.
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`3. Claim 3
`a. The apparatus of claim 1, wherein the at least one
`temperature sensor is taken from the group
`consisting of thermocouples and thermistors.
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`54. Atkinson discloses an apparatus where “the temperature is estimated directly
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`using a thermistor or other temperature sensor, and the refresh rate is adjusted
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`accordingly.” Ex. 1010 at 24:60-62.
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`55. It is generally known that the resistance of a thermistor falls as the
`
`temperature rises. Thus, as the temperature of main memory drops, the
`
`temperature of the thermistor also drops. In response to the drop, the resistance of
`
`thermistor increases in a known manner. This relationship is approximately linear.
`
`The voltage on the comparator noninverting input terminal is inversely
`
`proportional to the resistance of thermistor, and the noninverting input terminal
`
`receives an increasing voltage as the temperature of main memory decreases. Id. at
`
`21:38-48. See also claim 1 above.
`
`4. Claim 4
`a. The apparatus of claim 1, wherein the at least one
`temperature sensor includes a diode having a
`forward voltage drop that varies as a function of the
`temperature of the DRAM array; the at least one
`connection pin includes a first pin coupled to an
`anode of the diode and a second pin coupled to a
`cathode of the diode; and the signal corresponds to a
`potential voltage between the first and second pins.
`56. As set forth above in regard to claim 2, it would be obvious to modify
`
`Atkinson to use the forward voltage drop across a diode to detect the temperature
`
`of the main memory 106 or 906. Claim 4 simply recites one of a finite number of
`
`ways in which a two-pole device, such as a diode, can be connected. Given that
`19
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`
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`the claim recites “first pin” and “second pin,” the diode temperature sensor would
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`Attorney Docket No.: 37307-0006IP1
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`necessarily be connected to a first pin and a second pin if it were operational
`
`because, while the anode and the cathode of a diode could be connected to the
`
`same pin, that configuration would be electrically nonsensical as there would be
`
`the same potential on both side of the diode and thus, no voltage drop possible.
`
`Moreover, in such a diode configuration, the signal between the first pin and the
`
`second pin would necessarily be the forward voltage drop of the diode, which
`
`claim 4 defines as the signal. As such, and as with claim 2, it would be obvious to
`
`one of ordinary skill in the art to modify Atkinson to use a diode configuration as
`
`recited in claim 4, which is essentially the same as the obvious variant in claim 2.
`
`5. Claim 5
`a. The apparatus of claim 1, wherein the at least one
`temperature sensor is taken from the group
`consisting of thermocouples and thermistors.
`57. Claim 5 is identical to claim 3. See analysis under claim 3 above.
`
`6. Claim 6
`a. The apparatus of claim 1, further comprising a
`refresh unit operable to refresh the DRAM array at
`a rate that varies in response to the signal.
`58. Atkinson discloses an embodiment where the temperature sensing refresh
`
`generator senses the temperature of the main memory, and “the refresh frequency
`
`20
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`
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`decreases in proportion to the decrease in the temperature.” Ex. 1010 at 24:15-23;
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`Attorney Docket No.: 37307-0006IP1
`
`see also claim 1 above.
`
`
`
`7. Claim 7
`a. The apparatus of claim 6, wherein the refresh unit
`includes a refresh timing unit operable to establish
`the rate at which the DRAM array is refreshed in
`response to the signal.
`59. As set forth above, Atkinson discloses that “a voltage controlled oscillator
`
`combined with a temperature sensor could replace the refresh generator 850 in
`
`FIG. 8.” Ex. 1010 at 23:8-10. In this claim, the temperature sensor generates the
`
`signal that is sent to the voltage controller oscillator (i.e., the refresh timing unit),
`
`which “in response…produces the refresh signal at the proper frequency for
`
`refreshing main memory 106.” Id. at 23:17-20.
`
`60. Each of the other embodiments set forth above with regard to claim 1
`
`similarly include a refresh generator 850 or 950 (i.e., the claimed “refresh timing
`
`unit”). The refresh generator 850 or 950 provides a refresh signal that closely
`
`follows the temperature/frequency response of curve 600, which is based on
`
`receiving a temperature indicative signal from the thermistor 800. Id. at 22:38-67.
`21
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`Attorney Docket No.: 37307-0006IP1
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`8. Claim 8
`a. The apparatus of claim 7, wherein the refresh
`timing unit is operable to decrease the rate at which
`the DRAM array is refreshed as the signal indicates
`that the temperature of the DRAM array decreases.
`61. Atkinson discloses an apparatus where, “[a]s the thermistor resistance R
`
`increases in response to a decrease in memory temperature, the resulting decrease
`
`in the time constant value 1/RC lowers the frequency of the refresh signal. The
`
`frequency of the refresh signal in this embodiment continuously reduces as
`
`temperature decreases, rather than in discrete steps as in prior embodiments.” Ex.
`
`1010 at 22:52-65. The result is to decrease the rate at which the DRAM array is
`
`refreshed as the signal indicates that the temperature of the DRAM array decreases.
`
`9. Claim 9
`a. The apparatus of claim 7, wherein the refresh
`timing unit is operable to increase the rate at which
`the DRAM array is refreshed as the signal indicates
`that the temperature of the DRAM array increases.
`62. As shown in regard to claim 8 above, Atkinson’s response to temperature
`
`change is mathematical based on 1/RC, where R is the resistance through the
`
`thermistor 800. Ex. 1010 at 22:39-65. Therefore, in Atkinson, when the
`
`temperature increases, the minimum refresh frequency increases. See id.
`
`10. Claim 10
`a. The apparatus of claim 7, wherein the at least one
`temperature sensor includes at least one diode
`having a forward voltage drop that varies as a
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`Attorney Docket No.: 37307-0006IP1
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`function of the temperature of the DRAM array,
`and the signal corresponds to the forward voltage
`drop of the at least one diode.
`63. See claims 2 and 4 above.
`
`
`
`11. Claim 11
`a. The apparatus of claim 10, wherein the refresh unit
`is operable to sense the forward voltage drop of the
`diode to determine the temperature of the DRAM
`array.
`64. See claims 2 and 4 above.
`
`12. Claim 12
`a. The apparatus of claim 6, wherein the DRAM array,
`the at least one temperature sensor, and the refresh
`unit are integrated in a semiconductor package.
`65. Atkinson discloses an apparatus wherein “[t]he temperature-sensing refresh
`
`generator is contained entirely within main memory.” Ex. 1010 at 24:22-23. One
`
`version of this embodiment includes I/O controller, bridge logic unit, and main
`
`memory. Id. at 23:30-32. Main memory “preferably comprises DRAM circuitry,”
`
`which includes memory storage logic, switch, and a refresh generator with a
`
`thermistor, inverter, and capacitor. Id. at 23:30-40; see also id. at Fig. 9 (depicted
`
`below). This allows incorporation of this invention into any computer system by
`
`simply substituting the memory modules. Id. at 24:23-25.
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`23
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`Attorney Docket No.: 37307-0006IP1
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`13. Claim 13
`a. A dynamic random access memory (DRAM) chipset,
`comprising:
`66. See analysis for claim 1.b and 1.c above.
`
`b. at least one DRAM chip including
`67. See analysis for claim 1.b and 1.c above.
`
`c. a DRAM array and
`68. See analysis for claim 1.b and 1.c above.
`
`d. at least one temperature sensor in thermal
`communication with the DRAM array,
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`24
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`69. See analysis for claim 1.d above.
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`Attorney Docket No.: 37307-0006IP1
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`e.
`
`the at least one temperature sensor being operable
`to produce a signal indicative of a temperature of
`the DRAM array,
`70. See analysis for claim 1.e above.
`
`f.
`
`the DRAM chip including at least one connection
`pin operable to provide the signal to external
`circuitry; and
`71. See analysis for claim 1.f above.
`
`g. at least one refresh chip operable to refresh the
`DRAM array at a rate that varies in response to the
`signal,
`72. See analysis for claim 1.g above. Atkinson discloses a configuration where
`
`the refresh logic is included, as a separate component of the computer system or
`
`inside a bridge logic device, and can be used with any type of dynamic random
`
`access memory. See Ex. 1010 at 24:47-52.
`
`h. wherein the refresh chip is operable to
`(i)
`decrease the rate at which the DRAM array
`is refreshed as the signal indicates that the
`temperature of the DRAM array decreases;
`and

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