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`Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
`Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
`technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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`
`1
`
`PI 2018
`On Semiconductor v. Power Integrations
`IPR2016-01600
`
`

`

`www.fairchildsemi.com
`
`AN-5841
`Applying SG5841 to Control a Flyback Power Supply
`
`Summary
`This application note describes a detailed design strategy for
`a high-efficiency, compact flyback converter. Design
`considerations, mathematical equations, and guidelines for a
`printed circuit board layout are provided.
`Features
`(cid:131) Green-Mode PWM Controller
`Low Startup Current: 14μA
`(cid:131)
`Low Operating Current: 4mA
`(cid:131)
`Programmable PWM Frequency with Hopping
`(cid:131)
`Peak-Current-Mode Control
`(cid:131)
`Cycle-by-Cycle Current Limiting
`(cid:131)
`Synchronized Slope Compensation
`(cid:131)
`Leading-Edge Blanking (LEB)
`(cid:131)
`Constant Output Power Limit
`(cid:131)
`Totem-Pole Output with Soft Driving
`(cid:131)
`(cid:131) VDD Over-Voltage Clamping
`Programmable Over-Temperature Protection (OTP)
`(cid:131)
`Internal Open-Loop Protection
`(cid:131)
`(cid:131) VDD Under-Voltage Lockout (UVLO)
`(cid:131) GATE Output Maximum Voltage Clamp: 18V
`
`Description
`The SG5841 is a highly integrated PWM controller IC. It
`provides features to satisfy the need for low standby power
`consumption. With low startup current and low operating
`current, high-efficiency power conversion is achieved.
`Typical startup current is only 14μA and operating current is
`around 4mA. In nominal loading conditions, the SG5841
`operates at fixed PWM frequency. As the load decreases, its
`proprietary green-mode circuit gradually reduces the PWM
`frequency. This green-mode function dramatically cuts the
`power loss in no-load and light-load conditions, enabling the
`power supply to meet power conservation requirements.
`Additionally, the controller incorporates many protection
`functions. Once the power supply is overloaded, the
`controller forces the power supply into “hiccup” mode to
`limit output power. The built-in line-voltage compensation
`circuit maintains constant maximum output power for a wide
`input line voltage range. An external negative-temperature-
`coefficient (NTC) thermistor can be connected to the RT pin
`for over-temperature protection.
`
`Figure 1.
`
`Pin Configuration
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`
`www.fairchildsemi.com
`
`2
`
`

`

`AN-5841
`
`Block Diagram
`
`APPLICATION NOTE
`
`Figure 2.
`
`Block Diagram
`
`Startup Circuitry
`When the power is turned on, the input rectified voltage
`VDC charges the hold-up capacitor C1 via a startup resistor
`RIN. RIN can be connected to the VIN or VDD pin directly.
`As the voltage of VDD pin reaches the start threshold
`voltage VDD-ON, the SG5841 activates and drives the entire
`power supply to work.
`
`Due to the low startup current, a large RIN, such as
`1.5M(cid:58)(cid:15) can be used. With a hold-up capacitor of 4.7μF,
`the power-on delay tD_ON is less than 3.3s for 90VAC input.
`If a shorter startup time is required, a two-step startup
`circuit, as shown in Figure 4, is recommended. In this
`circuit, a smaller C1 capacitor can be used to reduce the
`startup time without using a smaller startup resistor RIN
`and increasing the power dissipation on RIN. The energy
`supporting the SG5841 after startup is mainly from a
`bigger capacitor C2.
`
`Single-Step Circuit Providing Power
`Figure 3.
`The maximum power-on delay time is determined as:
`t
`ON
`D
`(cid:16)
`1CR
`(cid:120)
`IN
`
`(cid:171)(cid:171)(cid:171) (cid:172)(cid:170)
`
`e1
`(cid:16)(cid:16)
`
`V
`DD
`
`(cid:16)
`
`ON
`
`(cid:32)
`
`(cid:11)
`V
`DC
`
`(cid:16)
`
`I
`DD
`
`(cid:16)
`
`ST
`
`(cid:120)
`
`R
`IN
`
`(cid:12)
`
`Two-Step Circuit Providing Power
`Figure 4.
`The maximum power dissipation of RIN is:
`(cid:11)
`(cid:12)
`2
`
` max,DC2
`V
`V
`V
`(cid:16)
`
` max,DC
`DD
`R
`R
`IN
`IN
`where VDC,max is the maximum rectified input voltage.
`
`P
` max,RIN
`
`
`(cid:32)
`
`(cid:35)
`
`(2)
`
`(1)
`
`(cid:187)(cid:187)(cid:187) (cid:188)(cid:186)
`
`where:
`the SG5841;
`current of
`startup
`the
`is
`IDD-ST
`tD-ON is the power-on delay of the power supply.
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`2
`
`www.fairchildsemi.com
`
`3
`
`

`

`AN-5841
`Take a wide-range input (90VAC-264VAC) as an example:
`
`APPLICATION NOTE
`
`(3)
`
`
`
`(cid:32)
`
`(cid:35)
`
`mW96
`
`VDC=100V~380V
`2
`380
`P
` max,RIN
`6
`10
`5.1
`(cid:117)
`In addition to the low startup current, SG5841 consumes
`less normal operating current than traditional UC384x.
`To achieve a successful startup and keep a no-load input
`power low enough to meet the power-saving requirements;
`the voltage level of VDD is recommended to be designed
`above 12V at no load.
`If the voltage of VDD falls below UVLO during “adaptive
`off-time modulation,” the unit enters “hiccup” operation.
`
`Oscillation and Green Mode
`Resistor RI programs the frequency of the internal
`oscillator. A 26K(cid:58) resistor RI generates PWM frequency
`as 65KHz:
`
`(cid:11)
`KHz
`
`(cid:12)
`
`(cid:32)
`
`fPWM
`
`1690
`(cid:11)
`(cid:12)(cid:58)
`KR
`I
`The range of the PWM frequency is recommended
`between 47KHz ~ 109KHz.
`
`(4)
`
`Setting PWM Frequency
`Figure 5.
`The proprietary green mode provides off-time modulation
`to reduce the PWM frequency at light-load and no-load
`conditions. The feedback voltage of the FB pin is taken as
`a reference. When the feedback voltage is lower than
`~2.1V, the PWM frequency decreases. Because most
`losses in a switching-mode power supply are proportional
`to the PWM frequency, off-time modulation reduces the
`power consumption of the power supply at light-load and
`no-load conditions. For a typical case of RI = 26K(cid:58), the
`PWM frequency is 65KHz at nominal load and decreases
`to 22KHz at light load, about one-third the nominal PWM
`frequency. The power supply enters “adaptive off-time
`modulation” in zero-load conditions.
`
`Figure 6.
`
`PWM Frequency vs. FB Voltage
`(RI=26K(cid:58))
`
`Adaptive Off-Time Modulation
`Figure 7.
`A frequency hopping function improves the system level
`of EMI performance. The PWM switching frequency hops
`between 65KHz +/- 4.2KHz, with a hopping period of
`around 4.4ms (5841J only).
`
`The FB Input
`The SG5841 is designed for peak-current-mode control. A
`current-to-voltage conversion is done externally with a
`current-sense resistor RS. Under normal operation, the
`peak inductor current is controlled by FB level:
`V
`2.1
`(cid:16)
`FB
`R3
`(cid:120)
`S
`where VFB is the voltage of the FB pin.
`When VFB is less than 1.2V, the SG5841 terminates the
`output pulses.
`
`I
`pk
`
`(cid:32)
`
`(5)
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`3
`
`www.fairchildsemi.com
`
`4
`
`

`

`AN-5841
`
`Figure 8.
`
`Feedback Circuit
`
`(6)
`
`(cid:120)
`
`mA2K
`(cid:116)
`
`Figure 8 is a typical feedback circuit consisting mainly of
`a shunt regulator and an opto-coupler. R1 and R2 form a
`voltage divider for the output voltage regulation. R3 and
`C1 are adjusted for control-loop compensation. A small-
`value RC filter (e.g. RFB= 47(cid:58), CFB= 1nF) from FB to
`GND can increase stability. The maximum sourcing
`current of FB pin is 2mA. The phototransistor must be
`capable of sinking this current to pull FB level down at no
`load. The value of biasing resistor Rb is determined as:
`V
`V
`V
`(cid:16)
`(cid:16)
`D
`Z
`O
`R
`b
`where:
`VD is the drop voltage of photodiode, about 1.2V;
`VZ is the minimum operation voltage, 2.5V of the shunt
`regulator; and
`K is the current transfer rate (CTR) of the opto coupler.
`For and output voltage VO=5V with CTR=100%, the
`maximum value of Rb is 650(cid:58).
`Built-in Slope Compensation
`A flyback converter can be operated in discontinuous
`current mode (DCM) or continuous current mode (CCM).
`There are many advantages to operating the converter in
`CCM. With the same output power, a converter in CCM
`exhibits smaller peak inductor current than in DCM.
`Therefore, a small sized transformer and a low-rating
`MOSFET can be applied. On the secondary side of the
`transformer, the rms output current of DCM can be up to
`twice of CCM. Larger wire gauge and output capacitors
`with larger ripple current rating are required. DCM
`operation also results in higher output voltage spikes. A
`large LC filter has also to be added. Therefore, a flyback
`converter in CCM achieves better performance with lower
`component cost.
`Despite the above advantages of CCM operation, there is
`one concern – stability. In CCM operation, the output
`power is proportional to the average inductor current,
`while the peak current is controlled. This causes the well-
`known sub-harmonic oscillation when the PWM duty
`cycle exceeds 50%. Adding slope compensation (reducing
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`APPLICATION NOTE
`the current-loop gain) is an effective way to prevent this
`oscillation. The SG5841
`introduces a synchronized
`positive-going ramp (VSLOPE) in every switching cycle to
`stabilize the current loop. Therefore, the SG5841 allows
`design of cost-effective, highly efficient, compact flyback
`power supplies operating in CCM without adding any
`external components.
`The positive ramp added is:
`V
`D
`V
`SL
`SLOPE
`where:
`VSL=0.33V;
`D=Duty Cycle.
`
`(cid:32)
`
`(cid:120)
`
`(7)
`
`Synchronized Slope Compensation
`Figure 9.
`Leading Edge Blanking (LEB)
`A voltage signal proportional to the MOSFET current
`develops on the current-sense resistor RS. Each time the
`MOSFET is turned on, a spike induced by the diode
`reverse recovery and by the output capacitances of the
`MOSFET and diode, occurs on the sensed signal. A
`leading-edge blanking time of about 270ns is introduced
`to avoid premature termination of MOSFET. Therefore,
`only a small-value RC filter (e.g. 100(cid:58) + 470pF) is
`required between the SENSE pin and RS. Still, a non-
`inductive resistor for the RS is recommended.
`
`Figure 10. Turn-on Spike
`
`www.fairchildsemi.com
`
`
`4
`
`5
`
`

`

`AN-5841
`Output Driver / Soft Driving
`The output stage is a fast totem-pole gate driver capable
`of directly driving external MOSFETs. An internal Zener
`diode clamps the driver voltage under 18V to protect
`MOSFET’s against over voltage. The maximum duty
`cycle is around 65%. By integrating special circuits to
`control the slew rate of switch-on rising time, the external
`resistor RG may not be necessary to reduce switching
`noise, improving EMI performance.
`
`Figure 11. Gate Drive
`
`APPLICATION NOTE
`
`Constant Output Power Limit
`The maximum output power of a flyback converter can
`generally be determined from the current-sense resistor
`RS. When the load increases, the peak inductor current
`increases accordingly. Once the output current arrives at
`the protection value, the OCP comparator dominates the
`current control loop. OCP occurs when the current-sense
`voltage reaches the threshold value. The output GATE
`driver is turned off after a small propagation delay, tPD.
`The delay time results in unequal power-limit level under
`universal input. A sawtooth power-limiter (saw limiter) is
`designed to solve the unequal power-limit problem. As
`shown in Figure 12, the saw limiter is designed as a
`positive ramp signal (VLIMIT_RAMP) and is fed to the
`inverting input of the OCP comparator. This results in a
`lower current limit at high-line inputs than at low-line
`inputs. However, with fixed propagation delay, tPD, the
`peak primary current would be the same for various line
`input voltages; therefore, the maximum output power can
`practically be limited to a constant value within a wide
`input voltage range without adding any external circuitry.
`
`Figure 12. Constant Power Limit Compensation
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`5
`
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`
`6
`
`

`

`AN-5841
`
`VDD Over-Voltage Clamping
`VDD over-voltage clamping prevents damage due to
`abnormal conditions. Once the VDD voltage is over the
`VDD over-voltage clamping voltage (VDD-CLAMP) and lasts
`for tD-VDDCLAMP, PWM pulses are disabled until VDD drops
`below the VDD over-voltage clamping voltage.
`
`Thermal Protection
`A constant current IRT is provided from pin RT. The
`resistor connected to pin RI decides its magnitude as:
`(cid:11)
`(cid:12)I
`
`μA100
`I
`R/K26
`(cid:58)
`RT
`For example,
`IRT = 100μA if RI = 26K(cid:58)(cid:17)
`
`(cid:32)
`
`(cid:120)
`
`(8)
`
`APPLICATION NOTE
`pin and ground. When VRT, the voltage level of RT pin, is
`less than 0.62V, PWM output is turned off.
`If the thermal protection is not used, connect a small
`capacitor (around 1nF is recommended) from the RT pin
`to the GND pin to prevent interference by noise. This RT
`capacitor cannot be larger than 4.7nF or the thermal
`protection is triggered before a successful startup of
`output voltage.
`
`Lab Note
`Before rework or solder/desolder on the power supply,
`discharge primary capacitors by external bleeding resistor;
`otherwise, the PWM IC may be destroyed by external
`high-voltage during solder/desolder. This device
`is
`sensitive to ESD discharge. To improve production yield,
`production line should be ESD protected according to
`ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1,
`and EOS/ESD S6.1
`
`For over-temperature protection, an NTC thermistor RT in
`series with a resistor RA can be connected between the RT
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`6
`
`www.fairchildsemi.com
`
`7
`
`

`

`AN-5841
`
`APPLICATION NOTE
`
`(cid:131)
`
`Printed Circuit Board Layout
`High-frequency switching current/voltage makes printed
`circuit board layout a very important design issue. Good
`PCB layout minimizes excessive EMI and helps the power
`supply survive during surge/ESD tests.
`Common guidelines:
`To get better EMI performance and reduce line
`(cid:131)
`frequency ripples, the output of the bridge rectifier
`should be connected to capacitor C1 first, then to the
`switching circuits.
`The high-frequency current loop is in C1 –
`Transformer – MOSFET – RS – C1. The area
`enclosed by this current loop should be as small as
`possible. Keep the traces (especially 4(cid:1064)1) short,
`direct, and wide. High-voltage traces related the drain
`of MOSFET and RCD snubber should be kept far
`way from control circuits to prevent unnecessary
`interference. If a heatsink is used for MOSFET,
`connect this heatsink to ground.
`(cid:131) As indicated by 3, the ground of control circuits
`should be connected first, then to other circuitry.
`(cid:131) As indicated by 2, the area enclosed by transformer
`aux winding, D1, and C2 should also be kept small.
`Place C2 close to the SG5841 for good decoupling.
`
`Two suggestions with different pros and cons for ground
`connections are recommended:
`
`(cid:131) GND3(cid:1064)2(cid:1064)4(cid:1064)1: This could avoid common
`impedance interference for sense signals.
`(cid:131) GND3(cid:1064)2(cid:1064)1(cid:1064)4: This could be better for ESD
`testing where the earth ground is not available on the
`power supply. The ESD discharge path goes from
`secondary through the transformer stray capacitance
`to GND2 first. Then the charges go from GND2 to
`GND1 and back to mains. It should be noted that
`control circuits should not be placed on the discharge
`path. Point discharge for common choke can decrease
`high-frequency impedance and increase ESD
`immunity.
`Should a Y-cap between primary and secondary be
`required, connect this Y-cap to the positive terminal
`of C1 (VDC). If this Y-cap is connected to the primary
`GND, it should be connected to the negative
`terminal of C1 (GND1) directly. Point discharge of
`this Y-cap also helps ESD; however, the creepage
`between these two pointed ends should be at least
`5mm according to safety requirements.
`
`(cid:131)
`
`Figure 13. Layout Conciderations
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`7
`
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`
`8
`
`

`

`AN-5841
`
`APPLICATION NOTE
`
`Related Datasheets
`SG5841/J — Highly Integrated Green-Mode PWM Controller
`
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`HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
`APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
`PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
`
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`
`1.
`
`Life support devices or systems are devices or systems
`which, (a) are intended for surgical implant into the body, or
`(b) support or sustain life, or (c) whose failure to perform
`when properly used in accordance with instructions for use
`provided in the labeling, can be reasonably expected to
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`
`2. A critical component is any component of a life support
`device or system whose failure to perform can be
`reasonably expected to cause the failure of the life support
`device or system, or to affect its safety or effectiveness.
`
`© 2006 Fairchild Semiconductor Corporation
`Rev. 1.1.1 • 4/24/08
`
`
`8
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`
`9
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`

`

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`Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
`regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
`specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
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