United States Patent [191
`Maige
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,763,238
`Aug. 9, 1988
`
`[54] EXTENDED OVERLOAD PROTECTION
`CIRCUIT FOR A SWITCH MODE POWER
`SUPPLY HAVING CYCLE DETECTOR,
`MEMORY AND FLIP-FLOP INHIBITION
`[75] Inventor:
`Philippe Maige, Syssinet Pariset,
`France
`[73] Assignee:
`Thomson-CSF, Paris, France
`[21] Appl. No.: 32,559
`[22] Filed:
`Apr. 1, 1987
`[30]
`Foreign Application Priority Data
`Apr. 4, 1986 [FR]
`France .............................. .. 86 04855
`
`[51] Int. Cl.‘ ................... .. H02M 3/335; HOZH 7/122
`[52] US. Cl. ...................................... .. 363/21; 363/49;
`363/56
`[58] Field of Search .................... .. 363/21, 56; 361/95,
`.
`361/96, 97
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,733,540 5/1973 Hawkins .
`
`4,288,831 9/1981 Dolikian . . . . . . . . . . . . .
`
`. . . . . .. 361/927
`
`4,330,816 5/1982 Imazeki et al. . . . .
`. . . . . .. 363/56
`4,476,427 10/1984 Kaneko et al. ...................... .. 361/97
`
`OTHER PUBLICATIONS
`Electronic Components and Applications, vol. 2, No. 1,
`Nov. 1979, pp. 31-48, Eindhoven, NL; H. Houkes:
`“TDAl060-A Comprehensive Integrated Control
`Circuit for SMPS”.
`Primary Examiner-—William H. Beha, Jr.
`Attorney, Agent, or Firm-Oblon, Fisher, Spivak,
`McClelland & Maier
`[57]
`ABSTRACT
`A protection device for switch mode power supplies
`includes a main switch controlled by the output signals
`of a ?ip-?op. The ?ip-?op input receives regulation
`control signals. A ?rst protection circuit supplies prior
`ity signals with respect to the regulation signals on the
`reset input of the ?ip-?op. The protection device also
`includes a cycle detector of the ?rst protection circuit,
`a memory for accumulating at each cycle a value pro
`portional to the duration between a signal of the detec
`tor and the set signal associated with the regulation
`cycle of the following cycle, and inhibiting of the ?ip
`flop when the memory has accumulated a signal higher
`than a predetermined threshold.
`
`6 Claims, 4 Drawing Sheets
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`ON SEMICONDUCTOR EXHIBIT 1008
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`US. Patent
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`Aug. 9, 1988
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`Sheet 1 of 4
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`4,763,238
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`ON SEMICONDUCTOR EXHIBIT 1008
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`US. Patent
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`Aug. 9, 1988
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`Sheet 2 0f 4
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`4,763,238
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`1
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`EXTENDED OVERLOAD PROTECTION CIRCUIT
`FOR A SWITCH MODE POWER SUPPLY HAVING
`CYCLE DETECTOR, MEMORY AND FLIP-FLOP
`INHIBITION
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`25
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`30
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`35
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`4,763,238
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`electric mass galvanically insulated from the primary
`mass.
`In the present description, each of the secondary
`windings has one end connected to the secondary mass.
`The other end supplies a respective low-pass ?ltering
`capacitor through a respective rectifying diode.
`Reference in the following description will be made
`to a single secondary winding ESl, connected by a
`diode 20 to a capacitor 22. The direct output voltage of
`the switch mode supply is the voltage Vs at the termi
`nals of the capacitor 22; but it is well understood that
`other direct output voltages can be obtained at the ter
`minals of the other ?ltering capacitors connected to the
`secondary windings. These output voltages constitute
`stabilized power supplies for utilization circuits (not
`represented). By way of example, a secondary winding
`ES2 supplies a stabilized power voltage of several volts
`for the regulation integrated circuit CI2 to which refer
`ence was made herein-above. It is thus checked that the
`circuit is not powered and therefore cannot supply
`signals as long as the switching does not function.
`The same is true a priori for the base control inte
`grated circuit CH of the power transistor Tp, which
`circuit is powered by a stabilized voltage supplied from
`a secondary winding BS3, from a diode 24 and from a
`capacitor 26 (it will be noted that this winding, although
`being a secondary winding is connected to the primary
`ground and not to the secondary mass, this for the very
`simple reason that the integrated circuit C11 is necessar
`ily galvanically connected to the primary).
`However, as it is necessary to ensure starting of the
`chopped power supply, it has been foreseen that the
`power terminal 28 of the integrated circuit C11 is also
`directly connected to the mains through a high resis
`tance 30 and a diode 32; this is possible since the inte
`grated circuit CIl is connected to the primary ground;
`it is not possible for the circuit CI2 which must remain
`galvanically insulated from the mains. Once the switch
`mode power supply functions normally, the stabilized
`direct voltage issuing from the winding BS3 and from
`the diode 24 has priority over the voltage issuing from
`the mains and from the diode 32; this diode 32 is blocked
`and the direct power supply through the mains no
`longer intervenes after the initial starting phase.
`The role of the integrated circuits C11 and CI2 will
`now be de?ned.
`The regulation circuit CI2 receives from a divider
`bridge 34, placed at the terminals of the capacitor 22,
`i.e. at the output of the stabilized power supply, data as
`to the value of the voltage to be stabilized Vs.
`This data is compared with a desired value and ap—
`plied to a pulse width modulator that establishes peri
`odic square pulses having variable width in function of
`the value of the output voltage Vs; the lower is Vs the
`larger will be the width of the square pulses.
`The square pulses are established at the switching
`frequency of the switch mode supply. This frequency is
`thus established on the side of the secondary of the
`circuit; it is generated either inside the circuit CI2, or
`outside in a circuit (not shown) in the form of a saw
`tooth shaped voltage at the selected switching fre
`quency. This saw-tooth voltage is used in a manner
`known per se to perform the width modulation.
`The variable width square pulses, at the switching
`frequency, are applied to a primary winding 36 of a
`small transformer TX, the secondary winding, 38, of
`which is galvanically insulated from the primary,
`
`40
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention concerns stabilized power
`supplies known as “switch mode power supplies”.
`A switch mode supply functions in the following
`manner: a primary transformer winding receives a cur
`rent that is, for example, issuing from a rectifying bridge
`receiving power from the alternating power mains. The
`current in the transformer is chopped by a switch (for
`example a power transistor) placed in series with the
`primary winding.
`A control circuit of the transistor establishes periodic
`square pulses to turn on the transistor. During the
`square pulse period current passage is authorized; out
`side of this square pulse period current passage is pro
`hibited.
`On one (or several) secondary winding(s) of the
`transformer, an alternating voltage is thus received.
`This voltage is recti?ed and ?ltered in order to produce
`a direct voltage that is the output direct voltage of the
`switch mode supply.
`In order to stabilize the value of this direct voltage,
`the duty cycle of the switch is modi?ed, i.e. the ratio
`between the conduction duration and the blocking du
`ration in a chopped period.
`FIG. 1 represents by way of example a switch mode
`power structure manufactured by the applicant in
`which two integrated circuits are used. One of the cir
`cuits, CI1, acts to control the base of a power switching
`transistor T1, for applying thereto periodic control sig
`nals for putting under conduction and blocking control.
`This base control circuit C11 is placed on the side of the
`primary winding EP of the transformer TA for reasons
`which will become apparent from the description given
`- herein-below. The other integrated circuit, regulation
`circuit CI2, is on the contrary placed on the side of the
`secondary winding E51 and is used to examine the
`output voltage Vs of the power supply in order to pro—
`duce regulation signals that it transmits to the ?rst inte
`grated circuit through a small transformer TX. The ?rst
`integrated circuit CIl uses these regulation signals to
`modify the duty cycle of conduction of the switching
`transistor Tp and thus of adjusting the output voltage
`Vs of the power supply.
`FIG. 1 shows the line of the public electric distribu
`tion mains under reference 10 (local supply circuit or
`mains at 110 or 220 volts, 50 or 60 hertz). This line is
`connected through a ?lter 12 to the input of a rectifying
`bridge 14, the output of which is connected on the one
`hand to a primary electric mass, represented throughout
`by a black triangle pointing downwards, and on the
`other hand to one end of the primary winding EP of the
`supply transformer TA.
`A ?ltering capacitor 16 is placed in parallel on the
`outputs of the rectifying bridge 14. The other end of the
`primary winding is connected to the collector of the
`switching transistor Tp, the emitter of which is con
`nected to the primary mass through a small current
`measuring resistance 18.
`The transformer is provided with several secondary
`windings that are preferably galvanically insulated from
`the mains and connected for example to a secondary
`
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`supplies positive and negative pulses to the rising and
`which is set by the appearance of a positive pulse arriv
`ing at the terminal 40. This is the reason why the oscilla
`descending edges, respectively of the variable width '
`square pulses.
`tor 64 is represented with an input connected to an
`It is these position and frequency pulses determined
`output 72 of a separation and shaping circuit 74 that
`receives the regulation signals from the terminal 40 and
`by the regulation circuit CI2, which constitute regula
`shapesthem by separating the positive pulses from the
`tion signals applied to an input 40 of the base control
`negative pulses. The shaping circuit 74 has two outputs:
`circuit CIl.
`'
`72 for the positive pulses, 76 for the negative pulses (the
`The transformer TX is constituted by several coil
`notation of positive pulse and negative pulse will be
`turns wound on a ferrite rod, the turns of the primary
`retained in order to distinguish the triggering pulses for
`and the turns of the secondary being suf?ciently spaced
`the on state and the triggering pulses for the off state
`apart from one another to respect the galvanic insula
`tion standards between primary circuits and secondary
`even if the shaping circuit establishes pulses of a single
`circuits of the switch mode supply.
`sign on its two outputs 72 and 76).,
`The base control integrated circuit CIl comprises
`The oscillator 64 has two outputs; an output ‘70 sup
`various inputs among which have been mentioned here
`plying a saw-tooth signal and an output 62 supplying a
`in-above a power input 28 and a regulation signal input
`short pulse when the saw-tooth is reset to zero.
`A pulse width modulator 78 is connected on the one
`40; a current measuring input 44 connected to the cur
`rent measuring resistor 18; and an inhibition input al
`hand to the output 70 of the osc?lator and on the other
`lowing to check the magnetization state of a trans
`' hand to an adjustable reference voltage through a resis:
`tor R1 outside the integrated circuit and connected to
`former. Furthermore, inputs can be provided to con
`nect the elements (resistors, capacitors) that should
`an access terminal 80 to the circuit. The modulator 78
`supplies periodic'square pulses synchronized with the
`form part of the integrated circuit itself but which for
`oscillator signals, these square pulses de?ning a maximal
`technological reasons (of bulk) or for practical reasons
`(possibilities of adjustment by the user) are externally
`duration of the on state Tmax beyond which the off
`state of the power transistor must be triggered in any
`mounted.
`The integrated circuit C11 furthermore comprises an
`case as a matter of security. These square pulses of
`modulator 78 are applied to an input of the OR gate 60.
`output 46 which is intended to be connected by a direct
`galvanic connection to the base of the power transistor
`The duration Tmax is adjustable through the external ,
`Tp. This output supplies square pulses for bringing the
`resistor R1.
`7
`The elements that have been described herein-above
`transistor Tp to the on or off state.
`30
`FIG. 2 represents partially the general structure of
`ensure the essential of the operating at normal condition
`of the integrated circuit C11. The following elements
`the integrated circuit C11.
`The. output 46 of the circuit, intended for the base
`are more . speci?cally provided .for controlling the
`control of the transistor Tp, is the output of a push-pull
`anomalous operating or the starting of the power sup
`ply.
`ampli?cation stage designated by the reference 48, this
`stage preferably comprising two separated ampli?ers
`A very low frequency oscillator 82 is connected to an
`external capacitor C2 through an access terminal 86.
`one of which receives square pulses which are inverted
`and delayed by several microseconds for to producing
`This external capacitor'adjusts the very low oscillation
`frequency. The frequency can be 1 hertz, for example.
`to the on state. Such ampli?ers are well known.
`The oscillator 82 is a relaxation oscillator supplying a
`The signals for switching to the on stae are issued
`from a logic flip-?op 50 having a set input 52 and a reset
`saw-tooth signal which is-applied on the one hand to a
`threshold comparator 88 which establishes periodic
`input 54. The set input triggers the on state of the power
`square pulses which are synchronized ‘on the saw-tooth
`transistor. The reset input triggers the off state.
`The set input 52(8) receives the pulses that pass
`at a low frequency of the oscillator. These square pulses
`throughran AND gate 58, so that the triggering of the
`have a brief duration compared to the saw-tooth period.
`This duration is ?xed by the threshold of the compara
`on state only occurs when several conditions are simul
`taneously satis?ed; if a single condition is not satis?ed,
`tor 88. It can be for example of 10% of the period. It
`must be long with respect to the free oscillation period
`this is sufficient to inhibit the triggering of the'on state.
`The reset input 54(R) receives the pulses which pass
`of the high frequency oscillator 64 so that a burst of
`numerous pulses of the high frequency oscillator can be
`through an OR gate 60, so that the interruption of the
`emitted and utilized'during this 10% of the period at
`on state (after triggering of the on state) occurs once a
`halt signal is present on one of the inputs of this gate.
`very low frequency. This burst de?nes an attempt at
`starting during the ?rst part of a starting cycle. It is
`On the diagram of FIG. 2, the AND gate 58 has three '
`inputs. One of these inputs receives periodic pulses
`followed by a pause during the remainder of the period,
`i.e. during the remaining. 90% of the period.
`issuing from an output 6270f a high frequency oscillator
`The oscillator 82 only functions for the starting. It is
`64; the other inputs act to inhibit the transmission of
`these pulses.
`inhibited when the regulation signals appear on the
`The oscillator de?nes the switching period of the
`terminal 40 and indicate that the switch mode supply is
`power supply (20 kilohertz for example). In normal
`functioning. This is the reason why an inhibition control
`operating state the oscillator 64 is synchronized by the
`of this oscillator has been represented, connected to the
`regulation signals. In starting state it is self-oscillating at
`output 72 of the shaping circuit 74 through a ?ip-flop 89
`which changes its condition under the effect of the
`a free frequency de?ned by the values of a resistor R0
`and of a capacitor C0 outside the integrated circuit C11
`pulses appearing at the output 72. It is returned to its
`initial condition by the output 62 of the oscillator 64
`and respectively connected to an access terminal 66 and
`an access terminal 68. The free frequency F0 is as a rule
`when there are no more pulses on the output 71.
`slightly lower than the normal switching frequency.
`The saw-tooth signals of the oscillator at very low
`The oscillator 64 is a relaxation oscillator that pro
`frequency are furthermore transmitted to a circuit 90
`for producing a variable threshold whose function is to
`duces on an output 70 a saw-tooth, the reset to zero of
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`establish a threshold signal (current or voltage) having
`the circuit in its differnt modes. Consequently, any
`a ?rst value Vsl in normal operating condition, and a
`novel contribution to a complex structure such as that
`cyclically variable threshold between the ?rst value and
`described herein-above requires numerous selections
`a second value at starting condition.
`and very numerous attempts between various solutions
`The threshold signal established by the circuit 90 is
`that could appear a priori as simple must be carried out.
`applied to an input of a comparator 92, the other input
`of which is connected to the terminal 44 already men
`tioned, in order to receive on this input a signal that is
`representative of the amplitude of the current ?owing
`through the power switching device. The output of the
`comparator 92 is applied to an input of the OR gate 60.
`It thus triggers the off state of the power transistor Tp,
`after an on state ?ring, the off state occuring, when
`exceeding the threshold (?xed or variable) de?ned by
`the circuit 90 has been detected.
`Another threshold comparator 94 has an input con
`nected to the current measuring terminal 44 while an
`other input receives a signal representing a third thresh
`old value Vs3. The third value Vs3 corresponds to a
`current in the switch which is higher than the ?rst value
`vs1 de?ned by the circuit 90. The output of the compar
`ator 94 is connected through a latch 96 to an input of the
`AND gate 58 whereby if the current in the power
`switch exceeds the third threshold value Vs3, an inter
`ruption of the on state of the transistor Tp is not trig
`gered (this interruption is triggered by the comparator
`92) but an inhibition of any ?ring of the transistor. This
`inhibition lasts until the ?ip-?op 96 is reset to its initial
`state corresponding to a normal operating.
`As a rule, this return will only occur when the inte
`grated circuit CI1 will have ceased to be normally sup
`plied with power and will be again set under voltage.
`For example, the return of the latch 96 occurs through
`a hysteresis threshold comparator 98 which compares
`one fraction of the power supply voltage Vcc of the
`circuit (drawn off from the terminal 28) with a refer
`ence value and which resets the latch during the ?rst
`passage of Vcc above this reference after a drop of Vcc
`below another reference value that is lower than the
`?rst one (hysteresis).
`Moreover, it can be speci?ed that the output of the
`?ip-?op 89 (which detects the presence of regulation
`signals on the terminal 40 thus the normal operating of
`the power supply) is connected to an input of an OR
`gate 100 which receives on another input the output of
`45
`the comparator 88 so that the output of the comparator
`88 ceases to inhibit the ?ring of the transistor Tp (inhibi
`tion during 90% of the very low frequency cycles) once
`the operating of the power circuit becomes normal.
`
`SUMMARY OF THE INVENTION
`Therefore, the present invention provides a device
`for protection against extended overloading in switch
`mode power supplies comprising a main switch con
`trolled by output signals from a ?ip-flop of which the
`inputs for setting to 1 and for resetting to zero receive
`regulation control signals, a ?rst protection circuit sup
`plying on the input for resetting to zero signals which
`have priority with respect to the regulation signals
`when the current in the main switch exceeds a predeter
`mined threshold, further comprising a second protec
`tion circuit itself comprising:
`means for detecting cycles for which the ?rst protec
`tion circuit operates and interrupts the on state of the
`main switch prior to the arrival of the switching off
`order of the regulation signal;
`memorization means accumulating at each cycle a
`value proportional to the duration between a signal of
`the detection means and the setting to 1 signal associ
`ated to the regulation signal of the following cycle; and
`inhibition means for inhibiting the set input of the
`?ip-?op when the memorization means have accumu
`lated a signal higher than a predetermined threshold.
`According to one embodiment of the present inven
`tion, the detection means comprise a second ?ip-?op, a
`third ?ip-?op and an AND gate:
`the second ?ip-?op receiving at its reset input the
`output for starting the regulation, the set input of this
`?ip-?op receiving the output of the AND gate and the
`output of this ?ip-?op controlling the memorization
`means;
`the third ?ip-?op having its set input connected to the
`reset input of the second ?ip-?op, its reset input con
`nected to the reset signal of the regulation signal, and its
`output connected to a ?rst input of the AND gate,
`the second input of the AND gate being connected to
`the output of the ?rst protection circuit.
`According to one embodiment of the present inven
`tion, the memorization means comprise a capacitor
`permanently discharged by discharging means and tem
`porarily charged by charging means only when the
`detection circuit supplies a signal.
`According to another embodiment of the invention,
`the inhibition means comprise a comparator comparing
`the signal accumulated by the memorization means with
`a reference value, the output signal of this comparator
`inhibiting the set input of the ?ip-?op when the memo
`rized signal becomes higher than a reference value.
`
`BRIEF DESCRIPTION OF THE DRAWING
`These objects, features and advantages and others of
`the present invention will become apparent from the
`following embodiment given by way of non-limitative
`illustration with reference to the appended drawing in
`which:
`FIGS. 1 and 2 illustrate a switch mode power supply
`according to the prior art and have been described
`herein-above;
`FIG. 3 is a simpli?ed representation of a protection
`circuit against the overloading of a switch mode power
`supply according to the prior art;
`
`t.. 0
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`OBJECT OF THE INVENTION
`Therefore,‘ in the device previously manufactured by
`the applicant and described in detail herein-above, par
`ticular procedures for the starting phases and particular
`protective procedures in the case of functioning inci
`dents are foreseen.
`The present invention aims at further improving the
`operating safety by detecting operating de?ciencies
`over a longer period of time than was the case with
`circuits of the prior art. Although the invention presents
`a novel and distinct contribution with respect to the
`process of the prior art, the prior device has been de
`scribed in full detail herein-above in order to render
`apparent the numerous restrictions which are imposed
`during production of a novel safety device which must
`take into account all the possible types of operating
`foreseen in an already existing circuit without introduc
`ing de?ciencies or blockages in the normal operating of
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`system 100 is energized, the charge system (current
`FIG. 4 illustrates the protection circuit against over
`loads of long duration according to the present inven
`supply 105) is activated. The ratio between the dis
`tion for switch mode power supplies; and
`charge‘current and the charge current is selected so that
`overall the capacitor 103 is charged. When the voltage
`FIGS. 5-a to to 5-b are time charts intended to illus‘
`trates the functioning of the circuits represented in
`at the terminals of the capacitor reaches a determined
`FIGS. 3 and 4.
`value, fixed by a comparator 106, a flip-?op FF4 is
`triggered which de?nitively inhibits the on state of the
`switch Tp.
`In the circuit 100 for detecting the functioning of the
`current limitation circuit, the flip-flop FF2 has its reset
`input R2 connected to the output 72 of the form shaping
`circuit 74, its set input S2 connected to the output of the
`AND gate 101 and its output Q2 connected to the con»
`trol terminal of the switch 107 of the circuit 102. The
`second ?ip-?op FF3 has its set input S3 connected to
`the output 72 of the shaping circuit 74, itsreset input R3
`connected to the output 76 of this shaping circuit and its
`output Q3 connected to a ?rst input of the AND gate
`101 of which the other input is connected to the output ‘
`of the comparator 92. detecting the excess currents in
`the power transistor Tp.
`FIG. 5 indicates a time chart of the signals appearing
`in different points of the circuit in four particular oper
`ating cases. In FIG. 5
`the line a indicates the signals present at the terminal
`40 or more exactly the control signals from which result
`the signals at the terminal 40 following'the action of the
`insulating transformer TX (cf. FIG. 1). Those signals
`correspond to more or less long square pulses according
`to the error signal detected;
`the line b indicates the signal present at the output 76
`of the shaping circuit 74, normally provoking the set- .
`ting to l of the ?ip-flop 50;
`the line c indicates the signal at the output 76 of the
`shaping circuit 74, normally controlling the reset of the
`flip-flop 50;
`the line d indicates the signal at the output Q2 of the
`?ip-?op FF2 controlling the switch 107;
`the line e indicates the signal Q3 at the output of the ‘
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIG. 3 once again represents in a simpli?ed manner
`the essential components of the circuit represented in
`FIG. 2 constituting a protection circuit against the ex
`cess currents in the main transistor Tp. The on state in
`the transistor Tp is normally controlled by a signal
`available on a terminal 40, resulting from a pulse width
`modulation circuit which controls a ?ip-?op 50 through
`a shaping circuit 74. The ?ip-?op 50 energizes the base
`of the power transistor Tp through a preampli?cation
`circuit (driver) 48 and an access terminal 46. When the
`current in the power transistor exceeds a given thresh
`old, the voltage at the terminals of a resistor 18 available
`at the terminal 44 is compared with a threshold voltage
`Vs by a comparator 92 and, should this voltage exceed
`the threshold, the reset input R of the ?ip-flop 50 is
`energized through an OR gate 60, the other input of 25
`which receives an output signal from the shaping circuit
`74.
`This protection device effectively protects the switch
`Tp against a current overloading but does not always
`allow good protection of the power supply, for example
`in the case of long duration overloading. In fact, there is
`no protection against excessive heating of the trans
`former TA or of the rectifying diodes 20 (of. FIG. 1) or
`of other components of the circuit connected to the
`secondary of the main transformer and it is generally
`necessary to over-size these components in order to
`take into account long duration overloadings which
`could occur as a result, for example, of short-circuiting
`on the secondary winding.
`The invention which will be described herein-below
`with respect to FIGS. 4 and 5 concerns a device which,
`added to the conventional current limitation circuit
`described herein-above, provokes the total and defmi
`tive shut down of the power supply in the case of long
`duration functioning of the current limitation system.
`Expensive over-sizing of certain components is thus
`avoided and the operating safety of the power supply is
`as a whole increased.
`The restarting of the power supply can be obtained
`by the momentary setting out of voltage of the system
`or at least of the device concerned.
`‘ As represented on FIG. 4, the present invention com
`prises a circuit 100 for detecting the operating of an
`overload circuit, comprising ?ip-?ops FF2 and FF3
`and an AND gate 101, and a circuit 102 for memoriza
`55
`tion and inhibition of the switch mode power supply.
`The circuit 102 operates the above described base cur
`rent control ?ip-flop 50 through an AND gate 58.
`The memorization and inhibition circuit 102 com
`prises a capacitor 103, a discharge system constituted by
`a current supply 104 functioning permanently, a system
`for charging this capacitor constituted by a current
`supply 105 controlled in all or nothing by a switch 107
`receiving the output of the detection circuit 100. When
`the detection circuit 100 indicates that the current limi
`65
`tation circuit in the power switch Tp does not function,
`only the discharge system 104 functions and the capaci
`tor 103 remains discharged. When the current limitation
`
`40
`
`45
`
`50
`
`the line f indicates the signal at the input R of the
`?ip-?op 50, i.e. the signal at the output of the OR gate
`60. This signal corresponds to the rising edge of the
`pulse at the output 76 of the shaping circuit 74 or at the
`output of the comparator 92;
`the line g indicates the current in the power transistor
`that corresponds to the signal present on the input 44 of
`the comparator 92;
`the line h indicates the signal at the output of the
`comparator.
`.
`The operating of this circuit in four possible function
`ing modes will now be studied.
`1. Normal operating without overloading
`No signal is supplied to the output of the comparator
`92 and it is the outputs 72 and 76 (signals‘of lines b and
`c) that control the inputs S and R of the ?ip-?op 50. The
`circuit 102 not receiving any output signal from the
`circuit 100 supplies to the output Q4 of the flip-flop FF4
`a high level signal and the AND gate 58 is validated
`thereby allowing the output signal 72 of the shaping
`circuit 74 to reach the input S of the flip-?op 50.
`2. Functioning in lower overloading limit
`As shown by line g of FIG. 5, it concerns the case
`where the reset pulse of the flip-flop 50 tends to bring
`the switch Tp at the off state prior to an overloading
`detection (current in Tp higher than I Max) occuring,
`but where an overloading occurs between the off state
`order and the effective off state of the power transistor.
`
`ON SEMICONDUCTOR EXHIBIT 1008
`Page 9 of 11
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`0
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`4,763,238
`9
`10
`This delay is due to the blocking period or storing time
`of the prior art. This results in very good operating
`security. The risk of spurious triggering of the device
`t, of the switch which is not nil in particular in the case
`where a high voltage bipolar transistor is utilized. The
`close to the lower current limit is thus prevented.
`current limitation comparator 92 is thus energized.
`On the other hand, as has been seen, the device ac
`However, the output signal of the comparator 92 does
`cording to the invention operates well with a power
`not reach the ?ip-?op FF2 to supply an output signal
`switch constituted by a bipolar transistor in which the
`Q2 since the ?ip-?op FF3 has been previously reset by
`storage time is relatively long, but this circuit is per
`the signal 76 and blocks the AND gate 101. the ?ip-flop
`fectly adaptable to a switch of which the off state delay
`FF2 thus remains at zero and as in the preceding case,
`tends towards zero such as a MOS power transistor.
`the circuit 102 is not energized and the regulation cir
`Similarly, accordng to another advantage of the in
`cuit continues to operate normally. It would in fact be
`vention, this circuit is perfectly compatible with the
`inconvenient to shut down the operating of the chop
`other protection and starting assistance circuits which
`ping power supply in this particular case.
`utilized the circuits according to the prior art. Indeed, it
`3. Operating in moderate overloading
`will be noted that the components of the circuit accord
`As in the previous case, it is the output signal 72 of
`ing to the invention are perfectly compatible with the
`the shaping circuit 74 that provokes the bringing to the
`components of the current limitation circuit described
`on state of the power transistor but, as shown by line g,
`herein-above. Furthermore, the AND gate 58 that has
`the overload level of the power transistor Tp is reached
`the circuit