PTO/SB/16 (8/96)
`Approved for use through 01/31/98. OMB 0651-0037
`Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless 1t displays a valid OMB control number.
`Type a plus sign ( +) inside this box [ +]
`Attorney Docket No.
`00551 O.P064Z
`PROVISIONAL APPLICATION FOR PATENT COVER SHEET
`This is a request for filing a PROVISIONAL APPLICATION FOR PATENT under 37 CFR 1.53 (c).
`
`'1f pr,~v
`
`INVENTOR(s}/APPLICANT{s}
`
`LAST NAME
`
`FIRST NAME
`
`MIDDLE NAME/
`INITIAL
`
`Balakrishnan
`
`Djenguerian
`
`Wong
`
`Matthews
`
`Balu
`
`Alex
`
`Kent
`
`David
`
`B
`
`RESIDENCE (CITY AND
`EITHER STATE OR
`FOREIGN COUNTRY}
`
`Saratoga, California
`
`Saratoga. California
`
`Fremont, California
`
`Michael Hugh
`
`San Jose. California
`
`TITLE OF THE INVENTION {280 characters max}
`METHOD AND APPARATUS FOR MAINTAINING A CONSTANT LOAD CURRENT WITH LINE
`VOLTAGE IN A SWITCH-MODE POWER SUPPLY
`
`CORRESPONDENCE ADDRESS {including count~ if not United States}
`
`BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN, LLP
`12400 Wilshire Boulevard Seventh Floor
`Los Angeles, California 90025-1026
`Teleghone: (206} 292-8600
`
`FAX: (206) 292-8606
`
`_x __ Specification
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`
`..
`
`\
`'
`
`ENCLOSED APPLICATION PARTS (check all that aeel~}
`
`Number of Pages
`
`15
`
`Small Entity Statement
`
`Number of Sheets
`
`5
`
`x
`
`Other (specify)
`se12arate Qage with title exQress mail
`label, C0!2l'. of 12ostcard and attornel'.'.s
`signature
`
`METHOD OF PAYMENT OF FILING FEES FOR THIS
`PROVISIONAL APPLICATION FOR PATENT (check one}
`_x __ A check or money order is enclosed to cover the filing fees
`_x __ The Commissioner is hereby authorized to charge
`filing fees and credit Deposit Account No. 02-2666
`
`Filing Fee Amount ($} 150.00
`
`This invention was made by an agency of the United States Government or under contract with an agency of the United States
`Government:
`X
`No
`- - Yes, the name of the U.S. Government Agency and the Government Contract Number are: - - - - - - - -
`
`REGISTRATION NO.--'-""""-'=-.!---(cid:173)
`(if appropriate)
`__ Ad iti al inventors are being named on separately numbered sheets attached hereto
`
`DATE 1-27·-0/
`
`12/01/97
`
`1 -
`
`PTO/SB/05 (12/97)
`
`1
`
`PI 2011
`ON Semiconductor v. Power Integrations
`IPR2016-01600
`
`

`

`' -.
`
`PTO/SB/17(11-00)
`Approved for use through 10/31/2002. OMB 0651-0032
`Patent and Trademark Office: U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are reqwred to respond to a collecbon of information unless 1t displays a valid OMB control number.
`FEE TRANSMITTAL FOR FY 2001
`TOTAL AMOUNT OF PAYMENT($)
`
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`
`Complete if Known:
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`Application No.
`Filing Date Herewith
`First Named Inventor Balu Balakrishnan et al.
`Group Art Unit Not Yet Assigned
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`Attorney Docket No. 00551 O.P064Z
`
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`106
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`107
`490
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`710
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`150
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`201
`206
`160
`207
`245
`208
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`75
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`3.
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`ADDITIONAL FEES
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`Large Entit~
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`Fee
`Code
`($)
`105
`130
`127
`50
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`Small Entit~
`Fee
`Fee
`Code
`($)
`205
`65
`227
`25
`
`139
`147
`112
`
`113
`
`115
`116
`117
`118
`128
`119
`120
`121
`138
`140
`141
`142
`143
`144
`122
`123
`126
`581
`
`146
`
`149
`
`179
`169
`
`130
`2,520
`920*
`
`139
`147
`112
`
`130
`2,520
`920*
`
`1,840*
`
`113
`
`1,840*
`
`110
`390
`890
`1,390
`1,890
`310
`310
`270
`1,510
`110
`1,240
`1,240
`440
`600
`130
`130
`180
`40
`
`710
`
`710
`
`710
`900
`
`215
`216
`217
`218
`228
`219
`220
`221
`138
`240
`241
`242
`243
`244
`122
`123
`126
`581
`
`246
`
`249
`
`279
`169
`
`55
`195
`445
`695
`945
`155
`155
`135
`1,510
`55
`620
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`220
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`130
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`For filing a submission after final rejection
`(see 37CFR1.129(a))
`For each additional invention to be examined
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`

`

`Our Reference: 005510.P064Z
`
`Patent
`
`METHOD AND APPARATUS FOR MAINTAINING A CONSTANT LOAD CURRENT
`WITH LINE VOLTAGE IN A SWITCH MODE POWER SUPPLY
`
`Inventors: Balu Balakrishnan et al.
`
`Respectfully submitted,
`
`KEL Y SOKOLOFF TAYLOR & ZAFMAN LLP
`
`"Express Mail" mailing label number:EL861981391US
`Date of Deposit:
`September 27. 2001
`I hereby certify that I am causing this paper or fee to be deposited with
`the United States Postal Service "Express Mail Post Office to Addressee"
`service on the date indicated above and that this paper or fee has been
`addressed to the Assistant Commissioner for Patents, Washington, D. C.
`20231
`
`imma N. Oks
`me of person mailing paper or fee)
`Oq-2. :f- -O{
`(Date signed)
`
`rson mailing paper or fee)
`
`(Sign
`
`Herewith
`
`Serial/Patent No.: New Application
`Filing/Issue Date:
`Power TntP,.gi:ations, Inc.
`Client:
`METHOD ANDAPPARATUS FOR MAINTA.INING A CONSTANT LOAD CURBENT
`Title:
`WI'l'B I.DIE VOUAGE INA SWI'.OCll MODE POWER SUPPJ Y
`JY.G/rno
`005510 .P064Z
`BSTZ File No.:
`Atty/Secty Initials:
`September 27, 2001
`Date Mailed:
`Docket Due Date: - - - - - - - - - - - -
`The following has been received in the U.S. Patent & Trademark orgg198tt3~1te stamped her0'lfiGG9
`US • Check No._~-
`D Amendment/Response (..____ pgs.)
`Express Mail No.: EL
`•
`$150 • 00
`0 Appeal Bnef (.._ pgs.) (in triplicate)
`D
`Month(s) Extension of Time
`Amt:
`D Application - Utility (_ pgs., with cover and abstract)
`D lrfutm1ionil&:la;ueStaenmt&P10-144l (_ pgs.) D Check No. __ _
`D Application - Rule 1.53(b) Continuation (.._ pgs.)
`D Issue Fee Transmittal
`Amt:
`D Application - Rule 1.53(b) D1V1s1onal (.._ pgs.)
`D Notice of Appeal
`D Application - Rule l.53(b) CIP (.._ pgs.)
`D Petition for Extension of Time
`D Application Rule l.53(d) CPA Transmittal(_ pgs.)
`D Petition for _____ _
`D Application - Design (.._ pgs.)
`•
`Postcard
`D Application - PCT (.._ pgs.)
`D Power of Attorney (.._ pgs.)
`• Application - Provisional cli pgs.)
`D Preliminary Amendment L - pgs.)
`D Assignment and Cover Sheet
`D Reply Brief(.._ pgs.)
`D Response to Notice of Missing Parts
`•
`ceruficate of Mailing
`D Declaration & POA (.._ pgs.)
`D Small Entity Declaration for Indep. Inventor/Small Business
`0 IlsclcsueD<:x:s&Qg&Ccpy<fhlenolsS€re<JI..dtor(_pg>)
`•
`Transmittal Letter, in duplicate
`• Drawings: _5__# of sheets includes _5__ fignres
`•
`Fee Transmittal, in duplicate
`
`• Other: * separate sheet with title, mqlress mail label,, copy of
`postcard, and attorney's signature;
`
`4
`
`

`

`UNITED STATES PROVISIONAL PATENT APPLICATION
`
`FOR
`
`METHOD AND APPARATUS FOR MAINTAINING A CONSTANT LOAD
`CURRENT WITH LINE VOLTAGE IN A SWITCH MODE POWER SUPPLY
`
`Inventors: Balu Balakrishnan
`Alex B. Djenguerian
`Kent Wong
`David Michael Hugh Matthews
`
`Prepared By:
`BLAKELY, SOKOLOFF, TAYLOR&ZAFMANLLP
`12400 Wilshire Boulevard
`Seventh Floor
`Los Angeles, California 90025-1026
`(206) 292-8600
`
`Attorney's Docket No.: 005510.P064Z
`
`"Express Mail" mailing label number:-'E=L=8=6=19'"""8...,,13=9_._1U=S"'-------------
`Date of Deposit
`September 27, 2001
`I hereby certify that I am causing this paper or fee to be deposited with the United States Postal Service
`"Express Mail Post Office to Addressee" service on the date indicated above and that this paper or fee has
`been addressed to the Assistant Commissioner for Patents, Was ·ngton,
`. C. 20231
`RimmaN. Oks
`(Typed or printed name of person mailing paper or fee)
`
`(Signature of person mailing paper or fee)
`
`(Date signed)
`
`5
`
`

`

`005510.P064Z
`
`METHOD AND APPARATUS FOR MAINTAINING A CONSTANT LOAD
`CURRENT WITH LINE VOLTAGE IN A SWITCH MODE POWER SUPPLY
`
`BACKGROUND OF THE INVENTION
`
`5
`
`Field of the Invention
`
`This invention relates generally to power supplies and, more specifically,
`
`the present invention relates to a switched mode power supply.
`
`Background Information
`
`All electronic devices use power to operate. A form of power supply that
`
`10
`
`is highly efficient and at the same time provides acceptable output regulation to
`
`supply power to electronic devices or other loads is the switched-mode power
`
`supply. In many electronic device applications, especially the low power off-line
`
`adapter/charger market, during the normal operating load range of the power
`
`supply an approximately constant output voltage is required below an output
`
`15
`
`current threshold. The current output is generally regulated below an output
`
`voltage in this region of approximately constant output voltage, hereafter referred
`
`to as the output voltage threshold.
`
`In known switched mode power supplies without secondary current
`
`sensing circuitry, minimizing the variation of the output current at the output
`
`20
`
`voltage threshold is performed with complex control schemes. Typically, these
`
`schemes include the measurement of input voltage, output diode conduction time
`
`and peak primary current limit. Some or all of this measured information is then
`
`used to control the regulator in order to reduce the variation of the output current
`
`-1-
`
`6
`
`

`

`005510.P064Z
`
`at the output voltage threshold.
`
`-2-
`
`7
`
`

`

`005510.P064Z
`
`SUMMARY OF THE INVENTION
`
`A power supply that maintains an approximately constant load current
`
`with line voltage below the output voltage threshold is disclosed. In one
`
`embodiment, a regulation circuit includes a semiconductor switch and current
`
`5
`
`sense circuitry to sense the current in the semiconductor switch. The current
`
`sense circuitry has a current limit threshold. The regulation circuit current limit
`
`threshold is varied from a first level to a second level during the time when the
`
`semiconductor switch is on. In one embodiment, the regulation circuit is used in a
`
`power supply having an output characteristic having an approximately constant
`
`10
`
`output voltage below an output current threshold and an approximately constant
`
`output current below an output voltage threshold. In another embodiment, a
`
`power supply is described, which includes a power supply input and a power
`
`supply output and that maintains an approximately constant load current with line
`
`voltage below the output voltage threshold. In one embodiment, the power supply
`
`15
`
`has an output characteristic having an approximately constant output voltage
`
`below an output current threshold and an approximately constant output current
`
`below an output voltage threshold. A regulation circuit is coupled between the
`
`power supply input and the power supply output. The regulation circuit includes a
`
`semiconductor switch and current sense circuitry to sense the current in the
`
`20
`
`semiconductor switch. The current sense circuitry has a current limit threshold.
`
`The regulation circuit current limit threshold is varied from a first level to a
`
`second level during the time when the semiconductor switch is on. In another
`
`-3-
`
`8
`
`

`

`005510.P064Z
`
`aspect, the current limit threshold being reached coincides with the power supply
`
`output characteristic transitioning from providing an approximately constant
`
`output voltage to supplying an approximately constant output current. In yet
`
`another aspect, the semiconductor switch is a MOSFET. Additional features and
`
`5
`
`benefits of the present invention will become apparent from the detailed
`
`description and figures set forth below.
`
`-4-
`
`9
`
`

`

`00551 O.P064Z
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention detailed illustrated by way of example and not
`
`limitation in the accompanying figures.
`
`Figure 1 is a schematic of one embodiment of a switched mode power
`
`5
`
`supply regulator in accordance with the teachings of the present invention.
`
`Figure 2 is a diagram illustrating one embodiment of sawtooth, duty cycle
`
`and intrinsic current limit waveforms in accordance with the teachings of the
`
`present invention.
`
`Figure 3 shows one embodiment of a power supply that has an
`
`10
`
`approximately constant voltage and constant current characteristic in accordance
`
`with the teachings of the present invention.
`
`Figure 4 shows one embodiment of a power supply that has an
`
`approximately constant voltage and constant current characteristic in accordance
`
`with the teachings of the present invention.
`
`15
`
`Figure 5 is a diagram illustrating the typical relationship between the
`
`output current and output voltage of one embodiment of a power supply in
`
`accordance with the teachings of the present invention.
`
`-5-
`
`10
`
`

`

`005510.P064Z
`
`DETAILED DESCRIPTION
`
`Embodiments of methods and apparatuses for maintaining a power supply
`
`output current substantially constant independent of input voltage at the point
`
`where the power supply output characteristic transitions from providing an
`
`5
`
`approximately constant output voltage to supplying an approximately constant
`
`output current are disclosed. In the following description, numerous specific
`
`details are set forth in order to provide a thorough understanding of the present
`
`invention. It will be apparent, however, to one having ordinary skill in the art that
`
`the specific detail need not be employed to practice the present invention. In other
`
`10
`
`instances, well-known materials or methods have not been described in detail in
`
`order to avoid obscuring the present invention.
`
`Reference throughout this specification to "one embodiment" or "an
`
`embodiment" means that a particular feature, structure or characteristic described
`
`in connection with the embodiment is included in at least one embodiment of the
`
`15
`
`present invention. Thus, the appearances of the phrases "in one embodiment" or
`
`"in an embodiment" in various places throughout this specification are not
`
`necessarily all referring to the same embodiment. Furthennore, the particular
`
`features, structures or characteristics may be combined in any suitable manner in
`
`one or more embodiments.
`
`20
`
`In one embodiment here, a switched mode power supply is described in
`
`which the output current below the output voltage threshold, is regulated to be
`
`approximately constant. This provides an approximate constant voltage/constant
`
`-6-
`
`11
`
`

`

`005510.P064Z
`
`current output characteristic. The output current level at the output voltage
`
`threshold in known power supplies sensed at the output of the power supply to
`
`provide feedback to a regulator circuit coupled to the primary winding of the
`
`power supply. If however, the approximate constant current functionality is
`
`5
`
`achieved without feedback from the secondary winding side of the power supply,
`
`the output current at the output voltage threshold is a function of a peak current
`
`limit of the primary regulator.
`
`Embodiments of the present invention reduce the variation of the output
`
`current at the output voltage threshold by reducing the peak current limit variation
`
`10 with changing input voltage. In general, the intrinsic peak current limit is set by
`
`internal circuitry in the regulator to be constant. Once the drain current reaches a
`
`current limit threshold, the switching cycle should terminate. However, a fixed
`
`delay is inherent from the time the threshold is reached until the power metal
`
`oxide semiconductor field effect transistor (MOSFET) is finally disabled. During
`
`15
`
`this delay, the drain current continues to ramp up at a rate equal to the direct
`
`current (DC) input voltage divided by the primary inductance of the transformer
`
`(drain current ramp rate). Therefore, the actual current limit is the sum of the
`
`intrinsic current limit and a ramp-rate dependent component (the overshoot),
`
`which is the drain current ramp rate multiplied by the fixed delay. Thus, at higher
`
`20 DC input voltages, the actual current limit ramps to a higher level above the
`
`intrinsic current limit level than at low DC input voltages. This can result in
`
`-7-
`
`12
`
`

`

`005510.P064Z
`
`variations in the output current delivered to the load at the output voltage
`
`threshold over a range of input line voltages.
`
`The actual current limit is the sum of the intrinsic current limit and the
`
`ramp-rate dependent component (the overshoot). The goal is to maintain a
`
`5
`
`constant actual current limit over DC input voltage variations. Since the ramp(cid:173)
`
`rate component (the overshoot) increases with respect to the DC input voltage, the
`
`only way to maintain a relatively constant current limit would be to reduce the
`
`intrinsic current limit threshold when the DC input voltage rises.
`
`In discontinuous power supply designs, the point in time during the
`
`I 0
`
`switching cycle in which the current limit is reached is dependent on the DC input
`
`voltage. In fact, the time it takes from the beginning of the cycle to the point
`
`where current limit is inversely proportional to the DC input voltage. Thus, the
`
`time elapsed from the beginning of the cycle can be used to gauge the DC input
`
`voltage.
`
`15
`
`Therefore, in order to create an intrinsic current limit which decreases
`
`relative to the DC input voltage, the time elapsed can be used. It is simply
`
`necessary to increase the intrinsic current limit as a function of the time elapsed
`
`during the cycle. A first approximation for increasing the intrinsic current limit
`
`with time can be obtained by using the Equation 1 below:
`
`20
`
`IuM-INTRlNSIC =Ki+ Kz * telapsed,
`
`(Equation 1)
`
`where is hIM-INTRlNSIC the intrinsic current limit, Ki and Kz are constants and 41apsed
`
`is the time elapsed.
`
`-8-
`
`13
`
`

`

`00551 O.P064Z
`
`In one embodiment, the time elapsed can be detected by the oscillator
`
`output waveform. In one embodiment, this waveform is a triangular one. It starts
`
`at its minimum at the beginning of the cycle. It gradually ramps until it reaches
`
`the point of maximum duty cycle. The ramp is substantially linear with time. The
`
`5
`
`intrinsic current limit threshold is basically proportional to the voltage seen at the
`
`input of the current limit comparator. This bias voltage is the product of the
`
`resistor value and the current delivered to this resistor. One way to increase the
`
`intrinsic current limit linearly as a function of the elapsed time would then be to
`
`derive a linearly increasing (with elapsed time) current source. This linearly
`
`10
`
`increasing (with elapsed time) current source can thus be derived from the
`
`oscillator.
`
`Figure 1 shows a schematic of one embodiment of a switched mode power
`
`supply in accordance with the teachings of the present invention. All of the
`
`circuitry shown in this schematic is used to control the switching of the power
`
`15 MOSFET 2. The timing of the switching is controlled by oscillator 5. Oscillator
`
`5 generates three signals: Clock 10, DMAX (Maximum duty cycle) 15, and
`
`Sawtooth 20. The rising edge of Clock signal 10 determines the beginning of the
`
`switching cycle. When Clock signal 10 is high, output latch 90 is set, causing
`
`power MOSFET 2 to begin conducting. The maximum conducting time is
`
`20
`
`determined by DMAX 15 signal being high. When DMAX 15 signal goes low,
`
`latch 90 is reset, thus disabling the power MOSFET 2.
`
`-9-
`
`14
`
`

`

`00551 O.P064Z
`
`The intrinsic current limit is, to the first order proportional to the voltage
`
`on node 22. As stated earlier, the goal of the invention is to generate an intrinsic
`
`current limit proportional to the time elapsed in the switching cycle. The saw
`
`tooth waveform 20 can be used to perform this task. As the base voltage ofNPN
`
`5
`
`transistor 30 rises, the emitter voltage also rises at the same rate. Thus, the current
`
`through resistor 25 is linearly increasing with time elapsed during the switching
`
`cycle. After mirroring this current through current mirror 40, the linearly
`
`increasing (with elapsed time) current source 27 is derived. The current limit
`
`threshold 22 is thus proportional to the product of the combination of linearly
`
`10
`
`increasing current source 27 and base current source 50 with the resistor 17. The
`
`voltage on node 27 is proportional to the power MOSFET drain voltage because
`
`of the voltage divider network formed by resistors 55 and 60. The drain current is
`
`proportional to the drain voltage. As the drain current 7 ramps up during the
`
`switching cycle, the voltage on node 27 rises proportionately. After the voltage on
`
`15
`
`node 27 exceeds the voltage on current limit threshold node 22, comparator 70
`
`disables the power MOSFET by ultimately resetting latch 90.
`
`PWM Comparator 32 modulates the duty cycle based on the feedback
`
`signal coming from the output of the power supply. The higher the feedback
`
`voltage, the higher the duty cycle will be.
`
`20
`
`Figure 2 shows on embodiment of three waveforms: sawtooth 20, duty
`
`cycle max 15, and intrinsic current limit 22. The sawtooth 20 waveform and the
`
`duty cycle max waveform 15 are generated by the oscillator 5. The duty cycle
`
`-10-
`
`15
`
`

`

`005510.P064Z
`
`max 15 signal determines the maximum duration of a power MOSFET switching
`
`cycle, when it is high. The sawtooth waveform 20 starts at the low point when the
`
`duty cycle max waveform 15 goes high. This signals the beginning of the power
`
`MOSFET switching cycle. The high point of the sawtooth 20 is reached at the
`
`5
`
`end of the cycle, at the same time the duty cycle max signal 15 goes low. The
`
`intrinsic current limit 22 signal starts at the low point at the beginning of the cycle
`
`and then linearly increases with elapsed time throughout the cycle. At a time
`
`elapsed of zero, the intrinsic current limit is at Ki. As time elapsed progresses, the
`
`current limit increases by a factor ofK2 * te1apsed.
`
`10
`
`Figure 3 shows one embodiment of a power supply that has an
`
`approximately constant voltage and constant current characteristic in accordance
`
`with the teachings of the present invention. The feedback information is provided
`
`to the regulator 250 at its control pin. The current at the control pin is
`
`proportional to the voltage across resistor 235, which in tum is related to the
`
`15
`
`output voltage. The regulator circuit reduces the duty cycle of the power
`
`MOSFET when the voltage across resistor 235 increases above a threshold. In
`
`this section, the output is in approximately constant voltage mode. The regulator
`
`circuit reduces the current limit of the power MOSFET when the voltage across
`
`resistor 235 decreases below a threshold. The current limit is reduced as a
`
`20
`
`function of the voltage across resistor 235 to keep the output load current
`
`constant. Thus, the load current is proportional to the current limit of the power
`
`-11-
`
`16
`
`

`

`005510.P064Z
`
`MOSFET in regulator 250. By keeping the current limit invariant to line voltage,
`
`the output load current would remain constant at all line voltages.
`
`Figure 4 shows one embodiment of a power supply that has an
`
`approximately constant voltage and constant current characteristic in accordance
`
`5 with the teachings of the present invention. The feedback information is provided
`
`to the regulator 350 at its control pin. The current at the control pin is
`
`proportional to the voltage across resistor 335, which in turn is related to the
`
`output voltage. The regulator circuit reduces the duty cycle of the power
`
`MOSFET when the voltage across resistor 335 increases above a threshold. In
`
`10
`
`this section, the output is in approximately constant voltage mode. The regulator
`
`circuit reduces the current limit of the power MOSFET when the voltage across
`
`resistor 335 decreases below a threshold. The current limit is reduced as a
`
`function of the voltage across resistor 335 to keep the output load current
`
`approximately constant. Thus, the load current is proportional to the current limit
`
`15
`
`of the power MOSFET in regulator 350. By keeping the current limit
`
`substantially constant with line voltage, the output load current would remain
`
`substantially constant at all line voltages.
`
`Figure 5 is a diagram illustrating the typical relationship between the
`
`output current and output voltage of one embodiment of a power supply in
`
`20
`
`accordance with the teachings of the present invention. As can be seen in curve
`
`400, the power supply utilizing the invention exhibits an approximately constant
`
`output current and constant output voltage characteristic. That is, as output
`
`-12-
`
`17
`
`

`

`00551 O.P064Z
`
`current increases, the output voltage remains approximately constant until the
`
`output current reaches an output current threshold. As the output current
`
`approaches the output current threshold, the output voltage decreases as the output
`
`current remains approximately constant over the drop in output voltage until a
`
`5
`
`lower output voltage threshold is reached when the output current can reduce
`
`further as shown by the range of characteristics. It is appreciated that the constant
`
`output voltage and constant output current characteristics of the present invention
`
`are suitable for battery charger applications or the like.
`
`In the foregoing detailed description, the method and apparatus of the
`
`10
`
`present invention has been described with reference to specific exemplary
`
`embodiments thereof. It will, however, be evident that various modifications and
`
`changes may be made thereto without departing from the broader spirit and scope
`
`of the present invention. The present specification and figures are accordingly to
`
`be regarded as illustrative rather than restrictive.
`
`1
`
`-13-
`
`18
`
`

`

`005510.P064Z
`
`ABSTRACT OF THE DISCLOSURE
`
`A power supply including a regulation circuit that maintains an
`
`approximately constant load current with line voltage. In one embodiment, a
`
`regulation circuit includes a semiconductor switch and current sense circuitry to
`
`5
`
`sense the current in the semiconductor switch. The current sense circuitry has a
`
`current limit threshold. The regulation circuit current limit threshold is varied
`
`from a first level to a second level during the time when the semiconductor switch
`
`is on. One embodiment of the regulation circuit is used in a power supply having
`
`an output characteristic having an approximately constant output voltage below an
`
`10
`
`output current threshold and an approximately constant output current below an
`
`output voltage threshold.
`
`-14-
`
`19
`
`

`

`IR
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`Blanking 17
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`Source
`
`Figure 1
`
`PWM Comparator
`
`feedback
`
`I
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`
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`I
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`DMAX
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`Clock
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`Oscillator 5
`
`22
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`40
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`45
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`30
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`60
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`17
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`27
`
`55
`
`20
`
`

`

`---.-~~~~
`Intrinsic Current Limit 22
`
`Figure 2
`
`telapsed
`
`2
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`...
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`telapsed
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`
`Duty Cycle Max 15
`
`t
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`ill
`
`Sawtooth 20
`
`21
`
`

`

`Figure 3.
`
`220
`
`: ••••• u ...... ,. .................... :
`
`240
`
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`
`200
`
`DC output
`
`0 +
`
`205
`
`210 I
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`•
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`i .
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`"''" '"··~·
`
`225f
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`230
`
`235
`
`245
`
`255
`
`HVDCinput
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`Dram Soocre J I I
`
`Control
`
`250
`
`22
`
`

`

`Figure 4.
`
`370
`
`I
`
`375
`
`Source
`
`•
`
`Control I--•-'\/\/'
`
`350
`
`330
`
`335
`
`Drain
`
`•
`
`360
`
`320
`
`340
`
`300
`
`DC output
`
`+
`
`•
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`
`310
`
`305
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`
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`325 f
`
`345
`
`l
`
`355
`
`HVDCinput
`
`0
`
`23
`
`

`

`Figure 5.
`
`'foldback' at low output voltages
`Output Current may or may not
`
`Current
`Output
`
`necessarily a straight line as shown
`
`component characteristics -not
`
`fi characteristics depends on exact
`
`circuit configuration and
`
`Approx Constant Output
`
`~ Current region -exact
`
`-=-1-
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`
`Voltage
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`
`'
`
`..
`
`component characteristics
`circuit configuration and
`
`characteristics depends on exact
`
`Voltage region -exact
`Approx Constant Output
`
`--============··-
`\
`";.:;?.'.:-------------~
`
`400
`
`l'H
`
`24
`
`