506
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO. 5, OCTOBER 1981
`
`Laser Programmable Redundancy and Yield
`in a 64K DRAM
`Improvement
`
`ROBERT T. SMITH, JAMES D. CHLIF’ALA, JOHN F. M. BINDELS, ROY G. NELSON, FREDERICK H. FISCHER,
`AND THOMAS F, MANTZ
`
`-Yield improvement obtained with laser programmed redun-
`Abstmct
`dancy in a 64K DRAM has ranged from 3000 percent during early
`model making to 500-800 percent after two years of volume production.
`The electrical design constraints on 64K redundancy organization are
`reviewed. The explosion and wicking phenomenon of polysilicon links
`by -50 ns, 1.064-pm wavelength laser pulses is dkcussed in relatiou to
`the target geometry,
`laser spot size and targeting accuracy. The system
`hardware and main software modules are detailed.
`In particular,
`the
`algorithms
`for testing,
`repair diagnosis, and target coordinate calcula-
`tion are explained.
`Elemental
`time analysis of the main operational
`steps is reviewed with emphasis on strategy for improved throughput.
`Evolution of the laser programming technology to the next generation
`of VLSI devices involves smaller spot sizes and submicrometer position-
`ing accuracy.
`
`1. INTRODUCTION
`
`DURING the past
`
`two years since first disclosure of fault-
`designs
`[1] - [3],
`technology
`using a
`tolerant memory
`to replace defective elements by redundant
`(spare)
`rows
`laser
`or columns has evolved greatly [4]. What was originally con-
`ceived as a yield improvement
`aid for the early stages of mem-
`ory development
`has matured
`into an extremely cost-effective
`wafer
`fabrication
`tool
`for volume production.
`No longer
`is
`there
`any question
`of whether
`to use redundancy
`in VLSI
`memories,
`rather,
`the current debate is over how much redun-
`dancy is appropriate,
`and whether
`to use laser programming
`or electrically fusible links
`[4] - [10]. An interesting variation
`on the laser programming
`approach, wherein the laser is used
`to connect,
`rather
`than to disconnect,
`circuit elements by rapid
`thermal diffusion from doped to intrinsic polysilicon has also
`been reported
`[11 ].
`Earlier work on laser coding of ROM’s
`[12],
`[13],
`and LSI circuit personalization
`[14],
`[15] was
`not aimed at volume production.
`The work reported herein is
`the first detailed account of a practical cost-effective
`laser pro-
`gramming process applied successfully
`to yield improvement
`of fault-tolerant VLSI memory production.
`The original yield
`incentive
`[2] has been tested and amply verified in two years
`of large scale manufacture,
`
`II. DESIGN CONSTRAINTS ON REDUNDANCY
`ORGANIZATION
`
`The electrical design details of the Bell System fault-tolerant
`64K dynamic RAM have been described elsewhere
`[1],
`[2].
`Only those details necessary to an understanding
`of the imple-
`
`Manuscript received May 8, 1981; revised May 13, 1981.
`The authors are with Bell Laboratories, Alleutown, PA 18103,
`
`and use of redundant memory elements are reviewed
`mentation
`here. The fault-tolerant
`design constraints
`are: 1) a fault-free
`memory requires no programming
`action; 2) electrical perfor-
`mance,
`especially access time,
`is not degraded by the use of
`spare elements; and 3) defective spare elements can be replaced
`by other spares.
`in
`is shown, highly simplified,
`organization
`The redundancy
`Fig. 1. Two spare rows, complete with decoder
`and driver
`circuitry,
`are associated with each 16K quadrant, organized as
`64 rows by 256 columns.
`Either one of these spare rows may
`replace any one of the 64 main rows in the adjacent quadrant,
`or may replace each other,
`if necessary.
`Four spare columns,
`including
`decoder
`and sense amplifier
`circuits, are associated
`with each pair of 16K memory
`quadrants.
`Any one of the
`spare columns may be used to replace any of the 256 columns
`in the adjacent quadrant pair, or any other previously encoded
`spare column in the same group. The issue of fault coverage,
`appropriate
`type and number of spares, and spare element or-
`ganization
`is intimately
`linked to the nature of the most pre-
`valent defects and their density. This will be discussed further
`in Section V.
`row
`of a defective memory element, whether
`Replacement
`or column, may be understood
`by referring to Fig. 2, which
`shows a standard and a spare row decoder schematic. The ac-
`tual decoder
`circuitry
`is somewhat more complex,
`especially
`in the column direction.
`Since the complete
`circuits and op-
`erating principles have been adequately
`described in [2], we
`will concentrate
`here on the decoder
`interchange
`by laser dis-
`connection
`of
`the faulty memory element,
`and programming
`or encoding of a spare decoder,
`The essential difference be-
`tween the standard
`and spare decoder
`is that
`the former has
`half the number of decode transistors
`of the latter. The iden-
`tity of the standard decoders is defined by unique connections
`of address and address complement
`to the appropriate
`decode
`gates. By contrast,
`the spare decoder has both address and the
`complement
`address tied to the gates of decode transistor pairs.
`Hence,
`regardless of the applied address,
`the spare decoder
`is
`heavily deselected,
`satisfying the first design constraint.
`by
`Disconnection
`of a faulty memory row is accomplished
`row
`exploding
`the programmable
`link between the standard
`driver and the row line, using a single laser pulse as described
`in Section III-B. One of the spare decoders is then encoded or
`programmed
`to take on the identity of the faulty element by
`selectively disconnecting
`either
`an address or its complement
`from the six transistor
`pairs in the decode node of the spare.
`This is done by exploding links in the drain connections
`of
`
`0018-9200/81
`
`/1000-0506 $00.75 @ 1981 IEEE
`
`Apple – Ex. 1022
`Apple Inc., Petitioner
`1
`
`

`
`SMITH etaL: LASER PROGRAMMABLEREDUNDANCYAND YIELD IMPROVEMENT
`
`507
`
`r QUAD ff 64 ROWS X 256 COL’S
`
`SPARE
`ROWS
`
`1
`
`3
`
`[
`
`SPARE
`COLUMNS
`
`1
`
`Fig. 1. Schematic layout of 64K DRAM including redundancy
`organization.
`
`Ao, A<
`
`At, A1
`
`STANDARD DECODER
`
`L(*’’-~L
`
`-—-
`
`~
`
`SPARE DECODER
`
`8
`
`LASER
`PROGRAMMABLE
`LINK
`
`A.
`
`~.
`
`Al
`
`<
`
`A2
`
`7Q
`
`v~o
`
`‘n
`
`<
`
`v~~
`
`Cw
`
`*
`
`Fig. 2. Simplified schematic of standard and spare row decoders show-
`ing location of laser programmable links.
`
`the capacitive loading of an encoded
`so that
`these transistors,
`to that of a standard decoder.
`The electrical
`spare is similar
`reselection
`of an encoded spare is virtually indistinguishable
`from that of a normal decoder,
`satisfying the second design
`constraint.
`of
`the explosion
`row requires
`of a defective
`Replacement
`the faulty element and six more
`seven links, one to disconnect
`to encode the spare. Fig. 3 illustrates
`the decoder
`interchange
`phenomenon
`for a row. Replacement
`of a defective column is
`more
`complicated,
`requiring
`fourteen
`link explosions.
`Two
`links are removed to disconnect
`the faulty column from the
`associated 1/0, ~
`line pair, six more to encode the spare col-
`umn decoder,
`and six more to disconnect
`the encoded spare
`column from three each of
`the four
`spare 1/0 and 1/0 line
`pairs. For more detailed circuit description and operation the
`reader is again referred to [2].
`is satisfied by providing additional
`The third design constraint
`disconnect
`links in the spare circuitry so that a defective spare
`may itself be replaced by yet another
`spare.
`
`111, LASER PROGRAMMING SYSTEM
`A. Hardware
`elements of an automatic
`The basic hardware
`ming system for fault-tolerant VLSI memories
`beam positioning
`system and a memory tester,
`and controlled
`by a real-time minicomputer.
`
`laser program-
`are a laser and
`interconnected
`At
`the present
`
`though the
`available,
`time, no such system is commercially
`and integrated with
`basic building blocks
`can be purchased
`relative ease. Even if a complete hardware
`system were avail-
`able, much would be left
`to the user since the major develop-
`ment effort consists of user dependent
`software. This comment
`applies equally well to an alternative
`approach to memory fault
`tolerance based on electrically fusible links [3],
`[5] -[10].
`The
`extent of this software can be gauged better
`from Section IV.
`Fig. 4 is a block diagram showing the interconnection
`be-
`tween the basic hardware
`components
`of a laser programming
`system. Most
`features needed for
`the laser programmer
`are
`available in commercial
`laser trimming systems. Two criteria
`are paramount
`for
`laser programming
`fault-tolerant
`VLSI
`memories,
`effective
`laser spot size and laser positioning
`accu-
`racy. Although some tradeoff between these two parameters
`is
`possible,
`as discussed in Section III-B, a nominal
`spot size of
`about 7-8 Km and a beam positioning accuracy relative to the
`target of *1 Mm is considered minimal.
`for the Bell
`This combination
`has proven entirely adequate
`System 64K DRAM designed three years
`ago with 3.5-urn
`design rules.
`Looking to the future, however,
`the laser pro-
`gramming system should be capable of providing a choice of
`laser wavelengths,
`a range of effective spot sizes, and targeting
`accuracy will need to be improved.
`This is discussed further
`in Section V-C.
`The laser used in the work reported here is a conventional
`
`2
`
`

`
`508
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO. 5, OCTOBER 1981
`
`bearing in
`lens aberrations,
`in minimizing classical
`importance
`the target
`features are of the order of 2-3 laser wave-
`mind that
`The CCTV camera has been specially interfaced
`to
`lengths.
`the
`control minicomputer
`to provide both automatic wafer
`and target die alignment.
`The low-cost memory tester, which is linked to the control
`minicomputer
`by a bidirectional
`byte-wide databus, has several
`hardware features generally found only in larger general-pu~pose
`test
`systems.
`The principal
`such feature
`is a hardware
`error
`buffer, capable of capturing errors on the fly. The buffer may
`also be used to OR together
`the results of several device tests
`to allow detection
`and replacement
`of marginal defects.
`For
`example,
`it has proven highly worthwhile
`to perform multiple
`functional memory
`tests at low and high supply voltages and
`replace marginal defects
`regardless of which voltage extreme
`caused the device failure.
`approach
`In order
`to provide extension of the fault-tolerant
`to other memory
`organizations,
`the buffer
`itself should be
`flexible in organization,
`and expandable. Byte-wide memories
`will, of course,
`require byte-wide drive and sensing capability.
`Flexibility
`of the buffer organization is important
`in one other
`respect,
`namely the
`addressing mode
`for
`reading the stored
`data.
`For example,
`if the redundancy
`scheme involves row
`replacements
`only,
`then rapid analysis of the error buffer
`is
`enhanced if the contents
`can be addressed and read out
`from
`the row direction in byte or multiple-byte
`data chunks. Simi-
`larly,
`if only column replacements
`need to be covered,
`then
`the buffer
`is better addressed and read in the column direction.
`Regardless
`of whether
`row only, column only, or both row
`~.–.––––7
`and column redundancy
`schemes are chosen,
`the buffer organ-
`ization should b,e optimized to match the diagnostic and spare
`!
`!LAsERpROGRAMMER
`allocation
`algorithm.
`Efficient
`analysis of
`the error buffer
`contents
`requires
`that
`they reflect a one-to-one physical map-
`ping of the test memory.
`Topological
`address descrambling
`hardware simplifies both memory test program preparation and
`mapping to the error buffer.
`
`II I
`
`I
`
`I
`
`CONTROL
`COMPUTER
`
`A
`
`(a)
`
`m
`
`—
`
`HARDWARE
`
`-+E
`
`:
`
`—
`
`(b)
`showing (a) disconnected row at 10OOX and
`Fig. 3. SEM photographs
`(b) an encoded and a nonencoded spare row decoder at 664x.
`
`B. Laser Target Explosion Phenomenon and
`Targeting Concerns
`to pro-
`is spatially filtered by an aperture
`The laser output
`duce a TEMW beam. This beam is expanded
`and collimated
`via a Gallilean telescope beam expander,
`attenuated
`to suitable
`power
`level and focused to a small waist at the wafer surface.
`A single laser pulse of approximately
`50-ns duration is used to
`sever a polysilicon target
`link. A short duration laser pulse is
`required to explode the target with no damage to adjacent and
`underlying
`structures.
`The energy per puke is approximately
`10 uJ. Clearly,
`laser targeting accuracy is a central concern in
`the programmable
`redundancy
`approach.
`The targeting strin-
`gency is defined by three factors:
`1) effective laser spot diam-
`eter (ELSD); 2) target
`feature size; and 3) target feature nearest
`neighbor distance.
`the derivation of ELSD. A TEMW mode,
`Fig. 5 illustrates
`circularly
`symmetric, Gaussian power density distribution
`is
`assumed for
`the focused laser pulse at
`the wafer surface. A
`threshold
`power density may be defined such that explosion
`of a polysilicon
`link occurs
`if and only if the incident
`laser
`power density is above the threshold
`level. Therefore, with
`
`~—— —— —..
`
`v
`
`1.06pm
`Nd: YAG LASER a
`
`LENS MOVEMENT
`
`I
`
`CONTROL
`
`I I I
`
`I
`
`I15!!!?7
`
`STEP a
`\ REPEAT
`TABLE
`L——_–––
`—_
`—–—
`—–_—_;
`Fig. 4. Block diagram showinginterconnection between major hardware
`components of laser programming system.
`
`Q-switched Nd-doped YAG laser operated in fundamental mode
`at 1.064 ~m wavelength.
`The final objective
`lens of
`the
`laser optics is also used as a viewing lens for a CCTV monitor-
`ing system.
`The lens is physically
`translated
`over the target
`wafer under control of a disk-based minicomputer, which also
`controls motion
`of a built-in step and repeat
`table.
`Physical
`translation
`of the laser optics presents
`a very useful advantage
`over galvanometric mirror
`scanning alternatives
`since the laser
`beam remains paraxial,
`regardless of target position. This is of
`
`3
`
`

`
`SMITH etal.: LASER PROGRAMMABLEREDUNDANCYAND YIELD IMPROVEMENT
`
`509
`
`A
`POWER/cm2
`
`THRESHOLD POWER
`
`4
`
`RADIUS
`
`RADIUS
`
`Fig. 7. SEM photograph
`
`of an exploded link with 5 .5-vm
`5000X.
`
`ELSD at
`
`MEMORY
`TESTER
`
`I
`
`LASER
`PROGRAMMER
`
`TEST
`
`64K BITS,
`CAPTURE
`AND
`BUFFER ERRORS
`
`?4r--1CONTACT
`l’-+DoTEST
`+--6NO SPARE
`YES‘+ANY
`
`AVAILABLE
`?
`
`)
`
`MORE
`DEFECTS
`?
`
`No
`
`YE:
`
`LOAD. ALIGN
`WAFER
`
`STEP
`TO NEW CHIP,
`PROBE
`
`EFINE
`POSITIONS1PBLAST
`I A--
`
`ALl ON
`
`COMPUTE
`LINK
`
`POLY-Si
`LINKS
`
`D
`
`c
`
`LAST
`CHIP
`?
`
`YES
`
`uNLOAD
`WAFER
`
`NO
`
`Fig. 8. Software system major flows.
`
`only the midclle 7-8 Km
`14-pm length even though
`entire
`experienced
`an incident
`power density above threshold. We
`have observed targeting errors of several microns
`in the direc-
`tion perpendicular
`to the link, in the situation of Fig. 6, with a
`clean severance of the link in question due to the wicking effect.
`If the ELSD is reduced to approximately
`5.5 pm,
`the situation
`is as demonstrated
`in Fig. 7. Note that although the links are
`not blown header
`to header, nonetheless more of the link is
`gone than the 5.5 urn directly illuminated by the laser.
`
`IV. SYSTEM SOFTWARE
`
`A. Major Flows
`process are
`The major
`logic flows of the laser programming
`indicated in Fig. 8. The operator
`loads a wafer on the step and
`repeat
`table chuck. The principal
`axes of the wafer are then
`
`LASER
`EFFECTIVE
`SPOT DIAMETER -:
`
`I
`
`I
`
`1uFig.5. Derivation ofeffective laser spot diameter (ELSD).
`
`rn——
`.;
`L–J
`link, nearest neighbor and laser spot geometries in scale
`represent ation.
`
`I
`
`~––l
`
`IL
`
`/
`
`Fig.6. Target
`
`the incident
`the region inwhich
`listed above,
`the assumptions
`Iaser power density exceeds thethreshold
`level defines acircu-
`lar area at the wafer surface in which any polysilicon will ex-
`plode. An analysis of64K DRAM polysilicon link explosion
`experience has resulted in an ELSD estimate of 7-8 ~m M indi-
`cated in Fig. 5.
`link,
`to scale,, of target
`representation,
`Fig. 6 is a schematic
`links
`nearest neighbor’, and laser spot geometries.
`The target
`are composed
`of heatiy
`doped polysilicon,
`reside beneath a
`phosphorus-doped
`Si02 layer, and are 3 #m wide and 14 ~
`long. The most severe nearest neighbor
`target
`link distance is
`deftied by the row line pitch where,links
`are spaced 9;5 Km on
`center.
`The ELSD is included in Fig. 6 assuming perfect
`tar-
`geting. This illustration
`demonstrates
`both the targeting sensi-
`tivity involved (targeting errors, on the order of microns causing
`possible failure, in link disconnection)
`and the derivation of our
`design rule which states that
`the ELSD should just overfill
`the
`distance between polysilicon edges.(6,5 ~rn).
`The design rule described above benefits
`from a phenomenon
`termed the wicking effect,
`in which thermal energy appears to
`be preferentially, drawn or wicked into the heavily doped poly-
`silicon.
`For
`example, with the perfect
`targeting
`accuracy
`indicated
`in Fig. 6,
`the link in question would explode
`the
`
`4
`
`

`
`510
`
`lEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO. 5, OCTOBER 1981
`
`aligned with the system’s axes. The bulk of the flowchart con.
`sists of a loop one circuit
`through which processes one chip.
`Each pass through the loop terminates
`in a test of the repeat
`criterion,
`i.e., was, the last chip on the wafer just processed?
`If so, the wafer is unloaded.
`If not, another
`loop pass is initiated.
`Each loop pass begins by stepping to the next chip and posi.
`tioning the test probes.
`The first
`testing consists of a quick test designed to rapidly
`identify massive chip failures.
`If the device fails, a contact
`test
`is performed
`and the repeat criterion test
`is executed.
`If
`the chip passes quick test, a full testis
`then performed.
`If there
`are no errors,
`the chip is functional,
`and the repeat criterion
`test
`is executed.
`If there are errors,
`the program enters a loop
`in which one spare row or column is allocated for each error.
`This is called the “repair
`algorithm”
`below.
`There are two
`possible
`exits from the repair algorithm loop.
`1) If there are
`more defects than spares,
`the chip is unrepairable
`and the re-
`peat criterion test is executed.
`2) If there are an equal or greater
`number
`of spares than defects,
`the chip is repairable
`and the
`program enters the target burn section.
`The first
`task in the target burn section involves alignment
`of the system to the chip to a resolution
`better
`than the 2.5-
`pm step size of the step and repeat
`table. Then the coordinates
`of the links are calculated and the laser explodes these targets.
`The program reenters
`the full
`test
`section remembering
`the
`spares that were just used. This test-laser-burn
`loop is repeated
`until either the chip is functional or proves unrepairable.
`
`B. Software Modules
`
`resides in the
`software
`The laser-programmable-redr.indancy
`two principal components
`of the system,
`laser programmer
`and
`memory tester. The code for the laser programmer
`is written
`in Pascal and assembly language;
`that
`for the memory tester is
`written in assembly and pseudo-test
`language.
`The program
`which executes on our development
`system does so with an
`overlay structure due to the great many engineering options and
`the restrictive memory
`limitations
`imposed by the operating
`system. The production code runs nonoverlay for high through-
`put by means of sacrificing all but
`those features essential
`for
`the memory-repair
`proper.
`is its modularity.
`A very desirable
`aspect of this software
`Since the system should be capable of adaptation
`to different
`memory
`devices and/or memory
`testers,
`it
`is important
`to
`modularize
`those
`sections
`of code which are common,
`and
`those which are unique to a specific device or memory tester.
`The software modules
`are four
`in number:
`1) main program,
`2) testing, 3) repair algorithm,
`and 4) laser and stepper move-
`ment and control.
`1), Main Program: This module executes in the control mini-
`computer
`of the laser programmer.
`The main program selects
`from a menu of possible options or execution modes in its first
`section, utilizes these modes in its second section to accomplish
`the desired tasks, and leaves the bulk of execution
`detail
`to a
`large number of procedure
`and function subprograms.
`There
`are four
`types of options:
`a) parameter
`setup (e.g., number of
`laser pulses per burn,
`length of various programmed
`delays,
`wafer map information,
`target coordinates
`data files, etc.); b)
`
`Fig. 9. Address path for diagonrdquick test.
`
`and automatic-align-
`stepper
`targeting,
`laser
`(e.g.,
`calibration
`ment hardware
`calibration,
`etc.); c) selection of execution op-
`tions
`(e:g., manual
`or automatic
`aligrqnent,
`extended
`repair
`information
`report,
`etc.); and d) selection of mode (e.g., laser
`targeting,
`test only,
`test and burn for memory repair, etc.).
`2) Testing: This module executes primarily in the memory
`tester.
`Testing software
`first performs a “quick diagonal” test
`on each memory device to rapidly reject massive, unrepairable
`failures. The diagonal
`lines, shown in Fig. 9, illustrate the bits
`tested in each half of the device, The test consists of a WRITEI
`READ function
`at each diagonal address followed by an incre-
`ment of the row and column address. Each new error along
`this path would require
`a separate
`spare row of column.
`If
`the total
`for either half exceeds the number of spares available
`for that half (8 for the 64K DRAM),
`the memory is unrepair-
`able.
`If the device fails this test, mechanical and electrical probe
`conditions
`are validated by performance
`of a contact
`test.
`If diagonal quick test
`is passed,
`the tester executes
`a com-
`plete functional
`device test at
`two voltage extremes,
`logging
`any errors into the hardware buffer described in Section III-A.
`3) Repair Algon”thm: This module has, at one time or an-
`other, executed in either the memory tester or the laser control
`computer
`(Fig. 8 happens
`to illustrate
`the former), depending
`on available memory in either machine
`and tradeoffs between
`diagnostic
`time and data transmission
`overhead.
`Fig. 10 is a
`schematic
`representation
`of one half of a 64K DRAM with
`spare rows and columns
`and a repairable
`error pattern.
`For
`each hrdf,
`the repair algorithm will assign spare elements one
`by one with the selection criterion being repair of maximum
`number of errors with each successive spare assignment.
`This
`process
`continues
`until
`there
`are no more errors (repairable
`half) or there
`are no more spares and some remaining errors
`(unrepairable
`half).
`The repair algorithm would proceed with tbe situation indi-
`cated in Fig. 10 by first allocating
`a spare column to repair
`column 246 since it is entirely defective. As each spare is as-
`signed,
`the errors in the buffer are deleted and the spare count
`is decremented.
`It deserves emphasis
`that
`there is no laser
`activity at this time since the decision of whether
`laser activity
`is required is being made. The repair algorithm will now replace
`row 11 since it has more errors than any other
`row or column.
`
`5
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`SMITH etal.: LASER PROGRAMMABLE REDUNDANCY AND YIELD IMPROVEMENT
`
`511
`
`I m-“’’’’’”’’’’’’’’’’’’’’’’’’’’’’’’”
`
`%/1
`
`Fig. 11. First three vectors in row target link calculation in quadrant
`zero,
`
`3t-----
`31V4
`L__.+%+
`
`CELLS
`
`ROW 6
`
`i 2 3 4 5 6 7 8 9
`
`I@
`
`I I
`
`ROW 62
`
`Fig. 12. Final vector in row target link calculation in quadrant zero.
`
`(Vl ) moves the laser from the origin to the center of the
`vector
`chip (Vl distorted in Fig. 11 for clarity of presentation) which
`is the axis of symmetry
`for the y-direction
`between the two
`halves.
`Since the desired target
`resides in the upper half,
`the
`next vector (Vz) transports
`laser targeting to a point midway be-
`tween quadrants O and 1, the y-direction
`symmetry
`axis for
`these quadrants.
`Note that
`if the target had been in the lower
`half, a reversal of y-component
`sign for V.. would have resulted
`in the appropriate move between quadrants 2 and 3. Similarly,
`since the target
`is in quadrant O, the next vector
`(V3 ) moves
`the laser to the top of the region containing the row links. Had
`the target been in quadrant
`1, a y-component
`sign reversal
`in
`V3 would have the correct
`result of positioning at the bottom
`of the row link region in that quadrant.
`Fig. 12 is a magnified view of the row link region of quadrant
`0, As can be seen from Fig. 12, V3 leaves the system on row
`address 0, The final vector
`is obtained by adjusting,
`if neces-
`sary,
`the y-component
`sign of the vector
`that
`takes the system
`from row O to row 1 and multiplying by the appropriate
`integer
`which in this case is nine. The resultant
`is V4 and the final
`location is calculated.
`It should be emphasized that no actual
`physical
`laser moves occurred until after addition of V4. All
`coordinates
`are calculated
`internally
`in microns.
`The final
`step prior
`to movement
`requires
`a translation
`of the coordi-
`nates in microns
`to an equivalent number of major detent
`(2.5
`&m) and high-resolution
`(2.5/ 14-flm) steps.
`c) Alignment
`software
`confronts
`the need for positioning
`accuracy greater
`than that of the 2.5-#m step size of the step
`and repeat
`table. After a candidate
`for repair has been iden-
`
`‘“~
`
`‘0”
`SPARES
`
`<
`
`C 246
`
`COLUMN
`‘SPARES
`
`~
`
`C133
`
`Fig. 10. Example ofrepairable halfmemory error map.
`
`column and
`
`leaving onespare
`Columns 133 and 101 arenext,
`three spare rows in this device half,
`Remaining are four singleton errors as indicated by the sym-
`bol “X.”
`Since the search always starts from row O/column O,
`the error at row 58/column
`21 is next
`replaced with the last
`row spare in the top quadrant.
`Row 60/column
`60 takes the
`last spare column in this half. The two singleton errors in the
`lower quadrant
`claim the two row spares for
`that quadrant.
`Since no errors remain,
`this half is potentially
`repairable.
`The repair algorithm software remembers
`the identity of the
`assigned spares. Therefore,
`referencing Fig. 8, on reentry into
`at point D after
`a retest
`sequence
`laser activity,
`if the tester
`detects new errors,
`the repair algorithm will not assign already
`utilized spares. Only entry into the test sequence at point A
`resets the spare count
`for a new chip.
`4) Laser and Step and Repeat Table Movement and Control:
`This module executes in the control minicomputer
`of the laser
`programmer.
`It
`is composed
`of three sections:
`a) basic high
`accuracy movement;
`b)
`feature movement
`and laser control;
`and c) alignment.
`software deals with the
`a) Basic high accuracy movement
`step and repeat
`table (2.5-Mm step size), the linear motors which
`transport
`the focussed laser
`light over
`the chip (2.5-#m step
`size) and the linear motors’ high resolution option (2.5/ 14-pm
`step size). These routines are supplied by the laser programmer
`manufacturer,
`software performs
`and laser control
`b) Feature movement
`the location
`of each laser
`target
`and
`the task of calculating
`performing
`the laser shots. There are two approaches
`for this.
`In a table lookup structure
`the location of every possible tar-
`get is stored. For the 64K DRAM there are 2584 potential
`tar-
`gets which would require 10336 words of memory, creating a
`severe strain on the modest memory resources. The creation and
`maintenance
`of such a database would be quite cumbersome.
`The selected method capitalized on the high degree of sym-
`metry in the 64K DRAM layout. Any and all possible laser
`target
`locations can be calculated via addition of vectors selected
`from a surprisingly small vector
`space if one permits the addi-
`tional
`freedoms of reversing they components
`of some vectors
`and multiplying
`other
`coordinates
`by some integer,
`as illus-
`trated below.
`of
`the position
`assume we wish to calculate
`For example,
`the target
`link connecting row address 9 with its decoder
`in the
`Fig. 11 is a schematic representa-
`upper half of the memory.
`tion of
`the 64K DRAM with cross-hatched
`areas indicating
`The origin of coordinates
`is the
`regions of possible targets.
`upper
`right-hand corner of each chip. The addition of the first
`
`6
`
`

`
`512
`
`IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-16, NO. 5, OCTOBER 1981
`
`LASER PROGRAMMING
`YIELD lMPROVEMEN-
`
`\ 0
`
`0
`
`\
`
`TABLE I
`ROUGHTIME ANALYSISOFELEMENTALOPERATIONALSTEPSIN TEST,
`DIAGNOSIS,ANDSUCCESSFULSINGLE-PASSLASERPROGRAMMING
`OF64K DRAM
`
`Operation
`
`Elapsed Time
`
`1) Double Diagonal Quick Test
`2) Functionality Test–Double
`Pass at Low and High VDD
`3) Diagnostic and Spare Alloca-
`tion Algorithm
`4) Laser Programming Action
`5) Retest for functionality
`
`Several Milliseconds
`
`SeveralHundred Milliseconds
`
`Several Seconds
`Several Seconds
`Several Hundred Milliseconds
`
`I
`0
`
`1
`I
`20
`10
`YIELD IMPROVEMENT
`
`1
`30
`FACTOR
`
`I
`40
`
`Fig. 13. Relative number of functional chips per wafer versus YIF.
`
`steps) to
`tifled the system must be aligned (via high-resolution
`a tolerance
`of tl #m. An operator
`can perform this task by
`manually aligning a cross hair on a magnified closed-circuit
`tele-
`vision image of a known alignment
`feature.
`Since ill operator
`intervention
`is time-consuming
`and degrades throughput,
`this
`task was automated.
`A hardware
`and software
`system was
`developed to selectively enhance
`the closed-circuit TV image
`of an aligmnent
`feature, automatically
`acquire its position and
`compensate
`the laser targeting accordingly.
`
`V, DISCUSSION
`A. 64K Yield Improvement
`Theoretical
`predictions
`of the relative yield of a 64K DRAM
`with 16 spare elements compared to an equivalent nonredun-
`dant design were reported
`as a function of defect density in
`[2].
`The extremely
`attractive
`yield improvement
`incentive
`fueled the development
`of the laser programming
`system de-
`scribed above. The results of two years of actual volume pro-
`duction experience using this technique
`are summarized in Fig.
`13. The yield-improvement
`factor
`(YIF)
`is defined as the ratio
`of the total number of functional
`chips,
`including those func-
`tional without
`laser action, per wafer, divided by the number
`of functional without
`laser action chips. The relative number
`of functional
`chips per wafer is plotted against YIF in Fig. 13.
`The range of YIF’s experienced covers an order of magnitude
`from the
`spectacular
`30,
`typical
`of early prototype model
`making,
`to the very solid 3 representing ultimate improvement
`on the highest yield wafer
`lots. YIF’s of about 5-8 are more
`representative
`of highly mature, well shaken-down production.
`The shape of the curve is gratifying since, even as progress is
`made up the (learning)
`curve from right
`to left,
`the number of
`functional
`chips per wafer increases dramatically.
`For this 64K
`design, the cost effectiveness of the laser programming approach
`has been patently demonstrated
`over the entire range of normal
`manufacturing
`improvement.
`design is the prob-
`of fault-tolerant
`An interesting ingredient
`lem of fault coverage alluded to in Section II. As might be ex-
`pected,
`the average number of spares actually used in the laser
`
`is reduced as basic processing improves
`process
`programming
`with experience.
`How many spares are enough depends very
`much on the circuit design and principal
`failure modes, as well
`as the active chip area and normal defect densities.
`The cost
`effectiveness
`of redesigning a memory chip to capitalize on the
`potential
`area reduction
`due to the smaller number of spares
`required in mature manufacture
`is a complex issue beyond the
`scope of this discussion.
`
`B. Time Analysis and Test Strategy
`of the main elemental op-
`Table I gives a rough breakdown
`erations
`and elapsed times typical of each step for successful,
`single-pass laser programming
`of a 64K DRAM. Multiple loop
`analysis can be estimated
`from this table but
`is not considered
`here since the actual
`incidence is a small fraction of single-pass
`programming.
`and
`the diagnostic
`the sequence,
`dominate
`Two operations
`and the actual
`laser programming
`itself. The
`spare allocation,
`diagnostic
`time depends heavily on the number of spares and
`the type of coverage. The fewer the number of spares and the
`simpler
`the coverage (for example,
`rows only),
`the shorter will
`be the diagnostic
`time required.
`Reductions
`of an order of
`magnitude may well be possible for unidirectional
`fault cover-
`age with very few spares. Even further dramatic
`reduction
`is
`conceivable
`if special preprocessing
`hardware were added to
`the error buffer.
`The major elapsed time in the actual
`laser
`programming operation is dead time, waiting for the laser optics
`to settle after a move.
`Further
`attention
`to the mechanical
`acceleration
`and deceleration
`of the laser optics would pay off
`dramatically in wafer throughput.
`the diagnostic and
`In spite of these potential
`improvements,
`laser programming
`operations will still dominate
`the overall
`throughput.
`This
`fact has interesting
`implications
`for
`test
`strategy and choice of test hardware.
`Since the tester and laser
`are linked by a full handshake protocol
`and one machine must
`wait while the other completes
`its task, there is a great incentive
`to reduce the capital cost of these major subsystems. The laser
`system costs over $200K and is not readily amenable to a low-
`cost version. The tester, on the other hand, can very well be
`optimized
`around the relatively simple type of functional
`test-
`ing involved. A low-cost
`tester
`(<$ 100K)
`is a better
`choice
`than the general purpose, highly accurate machines needed for
`final wafer or package testing.
`
`7
`
`

`
`SMITH etial.: LASER PROGRAMMABLE REDUNDANCY AND YIELD IMPROVEMENT
`
`513
`
`The laser programming operation is more properly identified
`with wafer fabrication than with memory testing.
`Indeed, after
`laser programming,
`the wafers undergo a final silicon nitride
`passivation
`operation,
`to cover up the tiny holes left
`f