US005798974A
`5,798,974
`[11] Patent Number:
`Ulllted States Patent
`Yamagata
`[45] Date of Patent:
`Aug. 25, 1998
`
`
`[19]
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`REALIZING HIGH SPEED ACCESS AND
`kggv Poxgglr‘ CI(l3§:S[¥:_’1PT[0N WITH
`C
`U
`Inventor: Tadato Yamagata. Hyogo. Japan
`
`[75]
`
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha.
`Tokyo. Japan
`
`[21] Appl. No.: 721,075
`
`[22] Filed:
`
`Sep. 26, 1996
`
`4,905,192
`5,299,164
`5,343,429
`5,383,156
`
`......................... 365/200
`2/1990 Nogami eta].
`....................... 365000
`3/I994 Takeuchi et a1.
`..................... 3650.00
`3/1994 Nakayama et al.
`1/1995 Kornatsu ................................. 365/200
`
`P"i"“"'.V Exami"9"—D3Vid C- Nelms
`Assistant Examiner—Trong Phan
`_Attomey, Agent, or FI‘rm—Lowe. Price. LeBlanc & Becker
`
`[571
`
`ABSTRACT
`
`Foreign Application Priority Data
`[30]
`May 15, 1996
`[JP]
`Japan .................................. .. 8-119850
`
`If a row (column) redundant circuit is not used. a compari-
`son between a defective address and an internal address is
`
`Int. CL5 ................................. G11C 7/oo; G11C 3/00
`[51]
`[52] U.S. Cl. ....................... 365/200; 365/225.7; 365/194;
`355/230063 365930-08
`[58] Field of Search ................................. 365/200. 225.7.
`365/194 230 06 230 08
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`not Porformod in 6 row (Column) fu-so Programming Portion
`in accordance with a signal output from a circuit for indi-
`eating if a row (column) redundant circuit is to be used or
`
`not. A comparison outcome signal which is generated when
`these addresses do not match each other is to be output from
`the row (column) fuse programming portion.
`
`4,353,192
`
`8/1989 Tatsumj et a1.
`
`......................... 365/200
`
`13 Chmsr 2" D““'“"o' S'“’°‘S
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`EXTERNAL
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`------------------------------------------------------------------
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`QESDNFELSS _, ggggggs1—-Z-I111-
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`NEAC COLUMN DECODER
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`8 -------------------------------
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`
`Apple — Ex. 1018
`Apple Inc., Petitioner
`1
`
`Apple – Ex. 1018
`Apple Inc., Petitioner
`1
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`U.S. Patent
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`Aug. 25, 1993
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`U.S. Patent
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`Aug. 25, 1993
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`U.S. Patent
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`Aug. 25, 1998
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`Sheet 5 of 20
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`U.S. Patent
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`Aug. 25, 1998
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`Sheet 7 of 20
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`5,798,974
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`Aug. 25, 1998
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`U.S. Patent
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`Aug. 25, 1993
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`Sheet 12 of 20
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`5,798,974
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`FIG. 14
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`Aug. 25, 1993
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`Sheet 15 of 20
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`5,798,974
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`U.S. Patent
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`Aug. 25, 1998
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`Sheet 16 of 20
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`Aug. 25, 1993
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`Sheet 19 of 20
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`
`U.S. Patent
`
`Aug. 25, 1993
`
`Sheet 20 of 20
`
`5,798,974
`
`FlG.22
`PRIOR ART
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`

`
`1
`SEMICONDUCTOR MEMORY DEVICE
`REALIZING HIGH SPEED ACCESS AND
`LOW POWER CONSUMPTION WITH
`REDUNDANT CIRCUIT
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`25
`
`30
`
`35
`
`The present invention relates to a semiconductor memory
`device. and more particularly. to a semiconductor memory
`device provided with a redundant circuit.
`2. Description of the Background Art
`FIG. 19 shows a structure of a semiconductor memory
`device provided with a conventional row-related redundant
`circuit. As illustrated in FIG. 19. the semiconductor memory
`device having a redundant circuit is generally provided with
`a fuse programming circuit for programming a defective
`address by the fuse blowing. And this semiconductor
`memory device includes: address buffer 10 for buffering an
`external address signal and generating an internal row
`address signal RowAdd; control signal generating circuit
`263 which externally inputs an external row address strobe
`signal ext. RTS. an external write enable signal ext. WET and
`the like to generate an internal control signal;
`internal
`address activation signal generating circuit 11 which gener-
`ates an internal address activation signal depending on the
`internal control signal input from control signal generating
`circuit 263. supplies it to address bufier 10 which takes in an
`external address signal. and outputs decoder activation sig-
`nal :1) to delay circuit 8; and sense amplifier activation signal
`generating circuit 9 for receiving decoder activation signal ti)
`and generating a signal to activate a sense amplifier. (cf.
`Page 15. lines 3-12). Arow fuse programming circuit 1. for
`example. compares an input row address with the pro-
`grammed defective row address. then outputs a signal SPA
`which indicates whether a normal word line WL or a spare
`word line SWL is to be activated depending on the outcome
`of the comparison. After signal SPA output from row fuse
`programming circuit 1 and a signal NEA generated accord-
`ing to SPA in a row decoder control circuit 2 constituted by
`an NOR circuit are determined. a decoder activation signal
`(l) of high level is supplied to a row decoder 4 or a spare row
`decoder 6. then the selected word line WL or spare word line
`SWL is activated. Until the outcome of the comparison of
`the addresses is established in row fuse programming circuit
`1. the high level decoder activation signal (1) is delayed in a
`delay circuit 8.
`FIG. 20 is a circuit diagram showing the structure of row
`fuse programming circuit 1. And FIG. 21 is a timing diagram
`showing the operation of the semiconductor memory device
`having the conventional row-related redundant circuit
`shown in FIG. 19. As shown in FIG. 20. row fuse program-
`ming circuit 1 is provided with a row address comparison
`portion 30. A defective address can be programmed by
`blowing either a fuse Fx or a fuse F, (x=O—n) included in row
`address comparison portion 30. If there is no defective
`memory cell. any fuse is not blown. When row fuse pro-
`gramming circuit 1 is on stand-by as shown in FIG. 21(a).
`a precharge signal PR of low level generated in a precharge
`signal generating circuit (not shown) sets a P channel MOS
`transistor Q1 on and the supply voltage is applied to an
`output node N1 from a supply node Vcc. so that program-
`ming circuit 1 outputs signal SPA of high level. At this time.
`the level of output signal SPA becomes high if row addresses
`Ax. A, (x=0—n) designated by an input internal row address
`signal RowAdd shown in FIG. 21(b) matches the previously
`programmed defective addresses. otherwise the level of
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`output signal SPA becomes low as shown in FIG. 21(c) since
`an N channel MOS transistor Q2 is turned on to cause the
`discharge through the fuse.
`As shown by FIG. 2l(e). decoder activation signal it is
`delayed for a delay time D by delay circuit 8 until the logic
`levels of signal SPA shown by FIG. 2l(c) and signal NEA
`shown by FIG. 21(d) are both established. then activated to
`high level. Decoder activation signal (1) accordingly activates
`the selected word line WL or spare word line SWL as shown
`in FIGS. 21(}‘) and 2l(g). respectively.
`FIG. 22 is a timing diagram showing a case in which delay
`time D in FIG. 21(2) is not sufliciently long as shown in FIG.
`22(e). Because delay time D is not long as illustrated by FIG.
`22(e). decoder activation signal on is activated earlier. At this
`time. signal SPA has high level as shown by FIG. 22(c). so
`that all the spare word lines SWL will be activated by spare
`row decoder 6 as shown in FIG. 22(g) if selected or not.
`Therefore. decoder activation signal ti) is delayed for appro-
`priate time not
`to cause such a malfunction. Here the
`precharge signal PR.
`the internal row address signal
`RowAdd. the signal NEA and the normal word line WL
`shown in FIGS. 22(a). 22(b). 22(_d) and 220‘). respectively.
`are related in the same way as those shown in FIGS. 21(0).
`21(b). 21(d) and 21(f).
`Although the semiconductor memory device provided
`with the redundant circuit as described above improves the
`yield. it still has a problem that activation of the word lines
`is delayed altogether.
`
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide a semi-
`conductor memory device in which the earlier activation of
`the word line is possible without comparing the internal
`address with the defective address. if the chip is of good
`quality with respective memory cells formed on the chip
`being free of any defect and there is no need of redundant
`circuit. resulting in the acceleration of the access speed.
`A semiconductor memory device according to one aspect
`of the present invention includes: a plurality of memory cells
`storing data; a redundant circuit used in place of a defective
`memory cell. if any; a driver circuit for writing and reading
`data in the memory cell or the redundant circuit; a defective
`address storing circuit comparing a previously stored defec-
`tive address corresponding to a defective memory cell with
`an address shown by an input address signal to generate a
`comparison outcome signal; and a cell state demonstrating
`circuit showing the redundant circuit should be used or not.
`The cell state demonstrating circuit deactivates the defective
`address storing circuit when there is no necessity of using
`the redundant circuit
`
`invention is.
`A principal advantage of the present
`therefore. the reduced power consumption in the defective
`address storing circuit of the semiconductor memory device
`having a redundant circuit since the defective address stor-
`ing circuit is deactivated when use of the redundant circuit
`is not required.
`The foregoing and other objects. features. aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram showing the overall structure of
`a semiconductor memory device according to the embodi-
`ment of the present invention.
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`FIG. 2 shows a row-related decoder control portion struc-
`tured dilfcrently from the row-related decoder control por-
`tion shown in FIG. 1.
`
`FIG. 3 is a circuit diagram showing one example of the
`row-related determining circuit shown in FIG. 2.
`FIGS. 4(a)—4(g) are timing charts showing the operation
`of the semiconductor memory device provided with the
`row-related decoder control portion shown in FIG. 2.
`FIG. 5 shows another row-related decoder control portion
`structured differently from the row-related decoder control
`portion shown in FIG. 1.
`FIGS. 6(a)—6(g) are timing charts showing the operation
`of the semiconductor memory device provided with the
`row-related decoder control portion shown in FIG. 5.
`FIG. 7 shows still another row-related decoder control
`portion structured dilferently from the row-related decoder
`control portion shown in FIG. 1.
`FIGS. 8(a)—8(g) are timing charts showing the operation
`of the semiconductor memory device provided with the
`row-related decoder control portion shown in FIG. 7.
`FIGS. 9(a}—9(d) are timing charts related to the power
`consumption in the row fuse programming circuit during the
`operation of the semiconductor memory device provided
`with the row-related decoder control portion shown in FIGS.
`2. 5 and 7.
`FIG. 10 shows the structure of the row-related decoder
`control portion shown in FIG. 1.
`FIG. 11 is a circuit diagram showing the structure of the
`row fuse programming circuit shown in FIG. 10.
`FIGS. 12(a)——l2(g) are timing charts showing the opera-
`tion of the semiconductor memory device shown in FIG. 1.
`FIG. 13 shows the structure of the improved version of the
`row-related decoder control portion shown in FIG. 1.
`FIGS. 14(a)—14(g) are timing charts showing the opera-
`tion of the semiconductor memory device provided with the
`row-related decoder control portion in FIG. 13.
`FIG. 15 shows the structure of the column-related decoder
`control portion shown in FIG. 1.
`FIG. 16 is a circuit diagram showing the structure of the
`column fuse programming circuit in FIG. 15.
`FIGS. l7(a)—17(g) are timing charts showing the opera-
`tion of the semiconductor memory device provided with the
`column-related decoder control portion in FIG. 15 when the
`column redundant circuit is used
`
`FIG. 18(a)—18(g) are timing charts showing the operation
`of the semiconductor memory device provided with the
`column-related decoder control portion in FIG. 15 when the
`column redundant circuit is not used.
`
`FIG. 19 shows the structure of the semiconductor memory
`device including a conventional row-related redundant cir-
`cuit.
`
`FIG. 20 is a circuit diagram showing the structure of the
`row fuse programming circuit shown in FIG. 19.
`FIGS. 2l(a)—21(g) are timing charts showing the opera-
`tion of the semiconductor memory device in FIG. 19.
`FIGS. 22(a)-22(g) are timing charts showing the opera-
`tion of the semiconductor memory device in FIG. 19 when
`the delay time set by the delay circuit of FIG. 19 is not long.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The embodiment of the present invention will be herein-
`after described in detail referring to the drawings. It is noted
`
`4
`that like reference characters denote the identical or the
`corresponding parts in the drawings.
`FIG. 1 is a block diagram showing the overall structure of
`the semiconductor memory device according to the embodi-
`ment of the present invention. As illustrated in FIG. 1. the
`semiconductor memory device according to this embodi-
`ment includes: a memory M constituted by a plurality of
`memory cells; a row redundant circuit SR; a column redun-
`dant circuit SC; word lines WL and bit lines BL included in
`memory M: a spare word line SW]. included in row redun-
`dant circuit SR; a spare bit line SBL included in column
`redundant circuit SC; a row decoder 4 and a word line driver
`5 for driving word line WL; a spare row decoder 6 and a
`spare word line driver 7 for driving spare word line SWL; a
`column decoder 22 for driving bit line BL; a spare column
`decoder 24 for driving spare bit line SBL; an address buffer
`10 inputting an external address signal and outputting an
`internal row address signal RowAdd and an internal column
`address signal Col.Add; a row-related decoder control por-
`tion 26 for the control of row decoder 4 and spare row
`decoder 6; and a column-related decoder control portion 28
`for the control of column decoder 22 and spare column
`decoder 24.
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`FIG. 2 shows a row-related decoder control po11ion 36
`structured differently from row-related decoder control por-
`tion 26 in FIG. 1.
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`Row—related decoder control portion 36 is provided with
`a row fuse programming circuit 1. a row decoder control
`circuit 2. a control signal generating circuit 263. an internal
`address activation signal generating circuit 11. a delay
`circuit 8. and a sense amplifier activation signal generating
`circuit 9. as well as switches SW1 and SW2. a delay circuit
`DC1 in which a delay time DTl is set shorter than the delay
`time D in delay circuit 8. and a circuit for indicating whether
`the semiconductor memory device is required to use a row
`redundant circuit or not. hereinafter referred to as row-
`related determining circuit 262.
`The switches SW1 and SW2 are controlled by a signal
`RUSE output from row-related determining circuit 262.
`FIG. 3 is a circuit diagram showing one example of
`row-related determining circuit 262. As illustrated in FIG. 3.
`row-related determining circuit 262 includes a supply node
`Vcc. a high resistance R1 connected in series between
`supply node Vcc and a ground node. a fuse 40, and a node
`N. Fuse 40 is blown when row redundant circuit SR is used
`in the semiconductor memory device. and signal RUSE of
`high level is output from node N. On the other hand. when
`row redundant circuit SR is not used in the semiconductor
`memory device. fuse 40 is not blown and node N and the
`ground node are connected. so that signal RUSE of low level
`is output from node N.
`Next the operation of the semiconductor memory device
`including row-related decoder control portion 36 will be
`described.
`
`If the semiconductor memory device uses row redundant
`circuit SR. switch SW1 connects row fuse programming
`circuit 1 with row decoder control circuit 2 and spare row
`decoder 6 in accordance with signal RUSE of high level
`output from row-related determining circuit 262. so that
`operation is similar to that of the conventional semiconduc-
`tor memory device shown in the timing diagram of FIG. 21.
`The operation of the semiconductor memory device
`which does not use row redundant circuit SR is shown in the
`timing chart of FIG. 4. Because the activation of spare word
`line SWL is not necessary. as shown in FIG. 4 (g). signal
`RUSE of low level output from row-related determining
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`circuit 262 switches switch SW1. and the logic level of a
`signal SPAO output from row fuse programming circuit 1
`attains low (L) as shown by FIG.. 4(0). At this time. since
`only the low level signal is input to row decoder control
`circuit 2. the level of signal NEA output from row decoder
`control circuit 2 attains high (H) as shown by FIG. 4(d).
`After precharge signal PR is activated as shown in FIG.
`4(a). row decoder 4. receives internal row address signal
`RowAdd shown by FIG. 4(b). and waits for the activation of
`decoder activation signal (1). Decoder activation signal :1) is
`delayed for the reduced delay time DTl in delay circuit DC1
`and thereafter activated. as shown by FIG. 4(e) because
`SW2 is switched in accordance with signal RUSE of low
`level output from row-related determining circuit 262. The
`acceleration of the access time is thus realized by the earlier
`activation of decoder activation signal (1) to cause the earlier
`activation of word line WL as shown by FIG. 40‘).
`FIG. 5 shows another row-related decoder control portion
`46 structured differently from row-related decoder control
`portion 26 shown in FIG. 1. As can be seen in FIG. 5.
`row-related decoder control portion 46 has a structure simi-
`lar to that of row-related decoder control portion 36 of FIG.
`2. with a switch SW3 added thereto.
`
`Switch SW3 is controlled by signal RUSE output from
`row-related determining circuit 262. When the semiconduc-
`tor memory device uses row redundant circuit SR. it oper-
`ates similarly to the conventional semiconductor memory
`device as shown in the timing chart of FIG. 21 because row
`decoder 4 and spare row decoder 6 are connected with delay
`circuit 8.
`
`The operation of the semiconductor memory device
`which does not use row redundant circuit SR is described
`following the timing chart of FIG. 6. SW3 is switched in
`accordance with signal RUSE of low level output from
`row-related determining circuit 262 so that row decoder 4
`and spare row decoder 6 are connected with supply node
`Vcc.As shown by FIG. 6(e). the level of a signal «)0 supplied
`from switch SW3 to row decoder 4 and spare row decoder
`6 is set high (H). In this case. internal row address signal
`RowAdd triggers the activation of word line WL as shown
`by (b) and (f) of FIG. 6. resulting in the acceleration of the
`data access compared with the conventional semiconductor
`memory device. Here the precharge signal PR. the signal
`SPAQ. the signal NEA and the spare word line SWL shown
`in FIGS. 6(a). 6(c). 6(dand 6(g). respectively. are related in
`the same way as those shown in FIGS. 4(a). 4(c). 4(d) and
`4(3)-
`Delay time D'I‘2 set in a delay circuit DC2 is determined
`considering the activation timing of the sense amplifier
`activation signal. It is noted that delay time DT2 is set
`shorter than delay time D set in delay circuit 8 when row
`redundant circuit SR is used. in order to cause an earlier
`activation of the sense amplifier in accordance with the
`earlier activation of word line WL.
`FIG. 7 shows still another row-related decoder control
`portion 56 structured ditferently from row-related decoder
`control portion 26 shown in FIG. 1. Row-related decoder
`control portion 56 has a structure similar to that of row-
`related decoder control portion 46 in FIG. 5 except that row
`fuse programming circuit 1 is directly connected to row
`decoder control circuit 2 and spare row decoder 6. Row-
`related decoder control portion 56 is further provided with a
`switch SW4 connected between row decoder cont:rol circuit
`2 and row decoder 4. a switch SW6 connected between
`switch SW2 and spare row decoder 6/row decoder 4. and a
`switch SW5 connected between switch SW6 and row
`decoder 4.
`
`The operation of row-related decoder control portion 56 is
`similar to that of the conventional semiconductor memory
`device when the row redundant circuit is used. The timing
`chart of FIG. 8 shows the operation of decoder control
`portion 56 when the row redundant circuit is not used. Signal
`RUSE of low level output from row-related determining
`circuit 262 causes switching of SW4. SW5. and SW6. so that
`the levels of signal NEA supplied to row decoder 4 and
`decoder activation signal oi) attain high (H). and the level of
`signal (1)1 supplied to spare row decoder 6 attains low (L) as
`shown by (c). (d) and (e) of FIG. 8. Therefore. the input of
`internal row address signal RowAdd to row decoder 4 after
`the activation of precharge signal PR shown in FIG. 8(g).
`immediately causes the activation of word line WL without
`waiting for the outcome of the address comparison in row
`fuse programming circuit 1 as shown by (b) and (f) of FIG.
`8. Here the spare word line SWL is not activated as shown
`by FIG. 8(g) in this case.
`However. row-related decoder control portions 36. 46 and
`56 shown in FIGS. 2. 5 and 7 still have a problem that the
`power is wasted in row fuse programming circuit 1.
`FIG. 9 is a timing chart for explaining the operation of
`row fuse programming circuit 1 with the specific circuit
`structure thereof illustrated in FIG. 20.
`
`When there is no defective memory cell and therefore row
`redundant circuit SR is not used. none of fuses Fx. Fx.
`(x=0—n) shown in FIG. 20 is blown. While the potential of
`node N1 is set to the supply potential when P channel MOS
`transistor Q1 is on and the supply voltage is attained from
`supply node Vcc. the potential of node N] becomes the
`ground potential as shown in FIG. 7(d) every time internal
`row address signal RowAdd is periodically input as shown
`in FIG. 9(0) after the activation of row address strobe signal
`T and precharge signal PR shown in FIGS. 9(a) and 9(b)
`and one or more N channel MOS transistor Q2 turns on and
`the ground voltage is applied through the fuses. Row fuse
`programming circuit 1 therefore periodically repeats the
`charge/discharge at node N1. causing the extra power con-
`sumption.
`The present invention. therefore. further aims at providing
`a semiconductor memory device preventing such wasteful
`power consumption therein.
`Row-related decoder control portion 26 in FIG. 1 for
`achieving above object is hereinafter described.
`Row-related decoder control portion 26 includes: a row
`fuse programming portion 261 connected with address
`butter 10 for storing a defective row address corresponding
`to a defective memory cell and comparing the defective row
`address with the row address shown by internal row address
`signal RowAdd input from address buffer 10; row decoder
`control circuit 2 connected between row fuse progamming
`portion 261 and row decoder 4 for determining whether it
`activates row decoder 4 or not; control signal generating
`circuit 263 which externally inputs an external row address
`strobe signal emf. an external write enable signal ext.
`W and the like to generate an internal control signal: and
`internal address activation signal generafing circuit 11 which
`generates an internal address activation signal depending on
`the internal control signal input from control signal gener-
`ating circuit 263. supplies it to address buffer 10 for mzdring
`address buffer 10 take in an external address signal. and
`outputs decoder activation signal (1). Row-related decoder
`control portion 26 further includes: delay circuit 8 connected
`with internal address activation signal generating circuit 11
`for delaying decoder activation signal it generated in the
`circuit 11 for delay time D; delay circuit DC1 connected to
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`internal address activation signal generating circuit 11 in
`parallel with delay circuit 8 for delaying decoder activation
`signal 41) for delay time DTl which is shorter than delay time
`D: row-related determining circuit 262 showing whether the
`semiconductor memory device is required to use row redun-
`dant circuit SR; switch SW2 connected with row decoder 4.
`spare row decoder 6 and sense amplifier activation signal
`generating circuit 9 for switching the delay of decoder
`activation signal 4) in delay circuit 8 and the delay of the
`signal cl) in delay circuit DC1 according to signal RUSE
`output from row-related determining circuit 262; and sense
`amplifier activation signal generating circuit 9 for generating
`a sense amplifier activation signal according to decoder
`activation signal (1) supplied from switch SW2.
`FIG. 10 shows the structure of row-related decoder con-
`trol portion 26 in more detail.
`As shown in FIG. 10. row fuse programming portion 261
`includes a plurality of row fuse programming circuits RFC.
`and row decoder control circuit 2 is constituted by an NOR
`circuit. The structure of row-related determining circuit 262
`is similar to that shown in FIG. 3.
`Next with reference to FIG. 11. FIG. 11 is a circuit
`diagram illustrating the specific structure of row fuse pro-
`gramming circuit RFC. As shown in FIG. 11. row fuse
`programming circuit RFC includes. as the conventional row
`fuse programming circuit 1. output node N1. row address
`comparison portion 30 for comparing a defective row
`address with an internal row address AX. Xx (x=O—n) rep-
`resented by the input internal row address signal RowAdd.
`supply node Vcc. and P channel MOS transistor Q1 with its
`source connected to supply nod