12
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 1, JANUARY 1991
`
`A Flexible Redundancy Technique for
`High-Density DRAM’s
`
`Masashi Horiguchi, Member, IEEE, Jun Etoh, Masakazu Aoki, Member, IEEE,
`a y 0 0 Itoh, Senior Member, IEEE, and Tetsurou Matsumoto
`
`Abstract -This paper points out the limitations of conventional re-
`dundancy techniques and proposes a novel redundancy technique for
`high-density DRAM’s, especially DRAM’s using multidivided data-line
`structures. The proposed technique features a flexible relationship be-
`tween spare lines and spare decoders. It provides higher usage efficiency
`of both spare lines and spare decoders, as well as lower probability of
`unsuccessful repair. With this technique the yield improvement factor of
`64-Mb DRAM’s and beyond is estimated to be more than twice that with
`the conventional technique in the early stages of production.
`
`I. INTRODUCTION
`EDUNDANCY techniques have been widely used as
`
`R effective methods of enhancing the production yield of
`
`semiconductor memories [1]-[6]. However, with the increase
`in memory density, the following problems have arisen:
`1) the number of spare lines and spare decoders required
`to maintain production yield has increased because of
`raw-yield degradation, and causes an increase in chip
`area.
`2) it is now necessary to recognize the effect of defects on
`spare lines that replace defective lines, which is due to
`the increased number of memory cells connected to a
`line, and causes a decrease in yield.
`This paper proposes a novel redundancy technique for
`solving these problems. The technique features a flexible
`relationship between spare lines for replacing defective lines
`and spare decoders for memorizing defective addresses,
`whereas this relationship was fixed in the conventional tech-
`niques. Since this results in more efficient usage of both
`spare lines and spare decoders, a larger yield-improvement
`factor can be achieved with a smaller chip-area penalty.
`In Section 11 the limitations of the conventional redun-
`dancy techniques are pointed out. Qualitative and quantita-
`tive descriptions of the new technique are given in Sections
`I11 and IV, respectively. Finally, an advanced revision of the
`new technique is proposed in Section V.
`
`11. LIMITATIONS OF THE CONVENTIONAL
`REDUNDANCY
`TECHNIQUE
`After the first introduction of redundancy in DRAM’s, the
`number of spare lines required for redundancy has steadily‘
`
`Manuscript received March 8, 1990; revised June 27, 1990.
`M. Horiguchi, J. Etoh, M. Aoki, and K. Itoh are with the Central
`Research Laboratory, Hitachi Ltd., Kokubunji. Tokyo 185, Japan.
`T. Matsumoto is with the Device Development Center, Hitachi Ltd..
`Ohme, Tokyo 198, Japan.
`IEEE Log Number 9038913.
`
`X: Row Decoder
`Y: Column Decoder
`a. -awl
`
`Fig. 1. Conventional redundancy technique applied to a DRAM with-
`out memory-array division.
`
`increased. The number increases by about 1.5-2 times for
`every new DRAM generation.’ This is caused mainly by the
`raw-yield degradation due to the chip-area increase (1.5
`times/generation [7]). On the other hand, there is a trend of
`DRAM-array multidivision, especially in data lines (bit lines).
`The number of data-line divisions almost doubles every
`generation to ensure a high signal/noise ratio and to mini-
`mize data-line charging/discharging current [7].’ The multi-
`divided data-line structure [SI in particular has become widely
`used for this purpose.
`The increase in both the number of spare lines and the
`number of subarrays causes serious problems in high-density
`DRAM’s as described below.
`Fig. 1 shows the well-known redundancy technique [31, [41
`applied to a DRAM without memory array division. Redun-
`dant data lines are omitted here for simplicity. The memory
`has L (here, L = 4) spare word lines SW,,-SW, and as many
`spare decoders SD,,- SD,. Defective word addresses are
`programmed in the spare decoders and compared with the
`input address. Thus, at most L defective normal word lines
`can be repaired. In this example, defective normal word lines
`W, - W, are replaced by spare word lines S WO - S W,, respec-
`tively, as shown by the arrows in the figure. Programming
`defective addresses in normal decoders [5], [6] is not suitable
`for high-density DRAM’s because of the very small decoder
`pitches and is not considered hereafter.
`Now let us consider dividing the memory array into subar-
`rays. Note that inter-subarray replacement (to replace a
`defective normal line in a subarray by a spare line in another
`subarray) should be avoided in DRAM redundancy, because
`
`‘See 1980-1989 ISSCC Digesf of Technical Papers.
`
`0018-9200/91/0100-0012$01.00 0 1991 IEEE
`
`Apple – Ex. 1013
`Apple Inc., Petitioner
`1
`
`

`
`HORIGUCHI et al.: FLEXIBLE REDUNDANCY TECHNIQUE FOR DRAM’S
`
`~
`
`13
`
`Fig. 3. FRT applied to a DRAM with memory array division.
`
`In the second approach (Fig. 2(b)), every spare line in
`every subarray has its own spare decoder. The number of
`spare decoders is therefore 4L, where L is the number of
`spare word lines in a subarray. Each spare decoder compares
`both intra-subarray and inter-subarray address signals.
`This approach has the following advantages over the first
`approach (Fig. 2(a)). First, since a smaller L is statistically
`required (here, L = 2) to repair as many defects, the usage
`efficiency of spare lines is higher (50% in this example). This
`is because the probability of excessive defects in a particular
`subarray is small under random defect distribution. Second,
`since in the whole memory only one normal line at a time is
`replaced by a spare line, the probability of a defect in the
`spare line is lower. This approach, however, has the disad-
`vantage of lower usage efficiency of spare decoders (half)
`than that of the first approach. This results in an increase in
`the area of spare decoders.
`Since in Fig. 2 there are only four subarrays, these prob-
`lems are not as serious. However, they would be critical in
`the design of ultrahigh-density DRAM’S in the future be-
`cause of the aforementioned trend for both the number of
`spare lines and the number of subarrays to increase.
`
`111. FLEXIBLE REDUNDANCY
`TECHNIQUE
`A novel redundancy technique, named the flexible redun-
`dancy technique (FRT), is proposed to overcome the prob-
`lems described in Section 11. In this section only qualitative
`features of the technique are described. Quantitative yield
`analysis will be given in the next section.
`Fig. 3 shows the FRT applied to a DRAM with array
`division. The spare lines and spare decoders are not con-
`nected directly, but through the OR gates G, and GI. Each
`spare decoder compares both intra-subarray and inter-sub-
`array address signals. Each logical-oR of the outputs of the
`two spare decoders is commonly applied to all the subarrays.
`The inter-subarray address signals select one of the four
`spare word lines. In this example, the addresses of defective
`normal word lines WO, W,, W,, and W, are programmed in
`spare decoders SD,,, SD,, SD,, and SD,, respectively. Word
`lines WO, W,, W,, and W, are thereby replaced by spare
`word lines SW,,, SW,,, SW,,, and SW,,, respectively.
`This technique features a flexible relationship between
`spare lines and spare decoders. In the conventional tech-
`
`aM,a,,.lo :
`2
`
`i
`(b)
`Fig. 2. Conventional redundancy technique applied to a DRAM with
`memory-array division. (a) Number of spare decoders equals number of
`spare lines in a subarray. (b) Every spare line in every subarray has its
`own spare decoder.
`
`I
`
`of the cumbersome control of memory-array associated cir-
`cuitry, especially the sense circuit. Two approaches to meet-
`ing this requirement are shown in Fig. 2(a) and (b). Here the
`memory array MA in Fig. 1 is divided into four subarrays,
`MA,-MA,, only one of which is selected.
`In the first approach (Fig. 2(a)), the number of spare
`decoders equals L , the number of spare word lines in a
`subarray. The total number of spare word lines is therefore
`4L. Each spare decoder compares only the intra-subarray
`address signals (here, a,-a,-,),
`and the output of a spare
`decoder is commonly supplied to all the subarrays. The
`inter-subarray address signals (here, a, -2 and a, - ,) in turn
`select one of the four spare word lines. It is obvious that as
`many defective word lines can be repaired as are shown in
`Fig. 1, if L is the same as that of Fig. 1.
`In this approach four normal lines (one in each subarray)
`are replaced simultaneously by spare lines, as shown by the
`arrows in the figure. That is, to replace one defective normal
`line, three other normal lines with the same intra-subarray
`address are also replaced even if they are not defective. This
`causes the following two problems:
`
`since the usage efficiency of spare lines is lower (a
`quarter that of Fig. 1, only 25%), the number of spare
`lines should be much larger, which results in chip-area
`increase; and
`the probability of unsuccessful repair due to defects in
`the spare lines that replaced the normal lines is higher,
`which results in yield degradation.
`
`2
`
`

`
`14
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 1. JANUARY 1991
`
`niques, this relationship is fixed so that a spare line can be
`activated only by a particular spare decoder. For example,
`spare word line SW,,
`in Fig. 2(a) is activated only by spare
`decoder SD,, and SW,,
`in Fig. 2(b) is activated only by SD,.
`However, in FRT, a spare line can be activated by one of
`several spare decoders. For example, spare word line SW2,,
`in Fig. 3 can be activated by either SD, or S D I through OR
`gate Go. Additionally, a spare decoder can activate one of
`several spare lines. For example spare decoder SD,, can
`activate either SW,,, SW,,, SW2,, or SW,,.
`This flexible relationship provides the advantages of both
`the conventional approaches described in Section 11. First,
`both spare-line usage efficiency and spare-decoder usage
`efficiency are good in FRT, while the former is poor and the
`latter is good in the first conventional approach (Fig. 2(a)),
`and the former is good and the latter is poor in the second
`approach (Fig. 2(b)). This enables smaller chip-area penalty
`due to redundancy. Second, FRT has as low an unsuc-
`cessful-repair probability as the second approach, while the
`first approach has high probability. This is because only one
`normal line at a time is replaced by a spare line.
`Another advantage of FRT is that more flexible selection
`of the number of spare lines in a subarray L and the number
`of spare decoders R enables a more efficient redundancy
`circuit. Generally, the following relation stands between L
`and R:
`
`M L
`L < R < -
`m
`where M is the number of physical subarrays, and m is the
`number of subarrays in which defective normal lines are
`simultaneously replaced by spare lines. Therefore M / m is
`the number of logically independent subarrays. The left-hand
`inequality sign indicates that the number of spare lines in a
`subarray in excess of the number of spare decoders is use-
`less. The right-hand inequality sign indicates that the num-
`ber of spare decoders in excess of the number of logically
`independent spare lines is useless ( M L / m is the number of
`logically independent spare lines in a whole memory). The
`relationship between L and R is fixed in the conventional
`redundancy techniques: m = M and R = L in the first ap-
`proach, and m = 1 and R = M L in the second approach. In
`FRT, however, L and R can be chosen independently so
`long as (1) stands.
`
`IV. YIELD ANALYSIS
`In this section, yield improvement factors through both
`conventional redundancy techniques and FRT are calcu-
`lated.
`
`A. Calculation Method
`The calculation is based on following assumptions:
`
`number of defects
`
`a) defect distribution is random-the
`follows Poisson distribution;
`b) one defect causes 1+ j lines to fail-the
`number j
`follows Poisson distribution of the mean value of A
`(here, A = 0.2 is assumed).
`Poisson distribution models have been used for the yield
`analysis of memories with redundancy because of mathemat-
`ical simplicity [2], [3], [9]. In this paper, the Poisson model is
`
`also used because it is sufficient for comparison between the
`conventional technique and FRT. However, more accurate
`yield estimation will require a model which takes the devia-
`tion from Poisson distribution [lo] into account.
`The calculation process is as follows. First, the defect-den-
`sity ratio is estimated. The ratio between the defect density
`of the array and the peripheral circuit is assumed to be
`inversely proportional to the square of the layout rule [8].
`Here, the layout rule of the peripheral circuit is assumed to
`be one generation behind that of the memory array:
`
`( 3 )
`
`where D , and D, are the repairable and unrepairable
`defect densities, respectively, of memory array and associ-
`ated circuitry (decoders, drivers, etc.), and D, is the defect
`density of the peripheral circuit. The ratio of D, to DI is
`dependent on the memory-cell fabrication process. Here
`D, : D, = 6 : 1
`is assumed. On the other hand
`( D , + D I ) S , + DpSp = D ( S, + S p )
`(4)
`stands, where S,
`is the area of the memory array and
`associated circuitry, S,
`is the area of the peripheral circuit,
`and D is the effective defect density. The defect-density
`ratio is calculated from these equations.
`Next, the probability Pi that a chip has i repairable defects
`and is successfully repaired is calculated. In particular P,, is
`the probability of a chip being "perfect":
`P, = exp ( - ( S, + R A s,) D,) . exp ( - ( S, + LMA s,) 01)
`( sM D M ) exp ( - s M D M ) 'U [ . [ , - , L , R
`i!
`is the increase in S,
`where AS,
`per spare line in a
`subarray, AS, is the increase in S, per spare decoder, and U
`is the successful-repair probability.
`Unlike
`the conventional redundancy techniques, suc-
`cess/failure of defect repair in FRT depends not only on the
`total number of defects but also on their distribution. For
`example, a chip with i defects ( L < i < R ) concentrated in a
`subarray cannot be repaired. This is due to the deficiency of
`spare lines even if there are sufficient spare decoders. The
`derivation of CT is as follows.
`Let us consider a particular defect distribution:
`1 , . . ' 3 d , 9 do)
`d = ( dL, d,-
`(6)
`where d, is the number of subarrays with exactly 1 defects
`Cld, = i). The probability that such a
`( C d , = M ' = M,",
`defect distribution is observed is given by
`M ' !
`1
`
`: )
`
`(5)
`
`L ! d l . ( L
`
`~
`
`I
`~ I . . . . . 1 !dl
`6 .
`1) !dl
`because the total number of distribution cases is M". There
`are three requirements for a successful repair: 1) the number
`of defective normal lines in a subarray must be less than or
`equal to L ; 2) spare lines which replace defective lines must
`be free from defects; and 3) the total number of defective
`
`(7)
`
`3
`
`

`
`HORIGUCHI et al.: FLEXIBLE REDUNDANCY TECHNIQUE FOR DRAM’S
`
`15
`
`lines must be less than or equal to R. Let us consider a
`subarray with exactly 1 defects. The probability of a success-
`ful repair of this subarray is
`
`L - l exp( - / A ) . ( / A ) j
`
`.exp ( - ( I + J)mAS,D,)
`
`.
`
`4 1 ) = c
`
`j = O
`
`I
`J !
`
`Q( d ) =
`/ = 1
`
`(8)
`The first factor is the probability that this subarray has 1 + j
`defective lines, and the second is the probability that 1 + J
`spare lines are not defective. The probability that require-
`ments 1) and 2) are satisfied is
`n S( /) ‘‘ = exp ( - i h )
`L
`L - l lJ.exp( - ( I + j)mAS,D,)
`. h [ C
`, = o
`J !
`1 = 1
`= exp ( - i A ) . q ( A )
`(9)
`where q ( A ) is a polynomial in A. To meet requirement 3),
`terms of higher degree than ARp‘ must be eliminated from
`q ( A ) , giving
`
`dl
`. A J ]
`
`(10)
`Q ’ ( d ) =exp(-zh).q’(A).
`By calculating P ( d ) and Q ’ ( d ) for every defect distribution
`d , the probability (T is given by
`
`a ( i , M ‘ , L , R ) = C P ( d ) Q ’ ( d ) .
`d
`Finally, the yield Y is given by the summation of P,:
`R
`Y = C P ; .
`i = O
`
`(11)
`
`B. Yield Trend
`The DRAM-yield trend from 4 Mb to 1 Gb is estimated
`through the calculation method described above. The second
`conventional approach (Fig. 2(b)) is unsuitable for ultrahigh-
`density DRAM’s because of the large area penalty of spare
`decoders. Therefore the first conventional approach (Fig.
`2(a)) and FRT are compared based on the following assump-
`tions: 1) the chip area increases 1.5 times every generation
`[8], while the ratio between array area and peripheral area is
`unchanged; 2) the number M doubles every generation ac-
`cording to the trend,’ while the number m is unchanged
`( = 4); and 3) the numbers L and R are L = R = 8 for the
`conventional technique and L = 4, R = 16 for FRT to equal-
`ize area penalty. These numbers are unchanged due to the
`restriction of the number of lines in a subarray (the number
`of word lines in a subarray is almost unchanged).’
`The calculation results are shown in Fig. 4(a)-(c). The
`yield improvement factor of a 4-Mb DRAM through FRT is
`almost the same as that through the conventional technique.
`This is because the number of logically independent subar-
`rays is as small as 4. The advantage of FRT becomes appar-
`ent in 64-Mb and 1-Gb DRAM’S, especially for a large
`defect density D , that is, in the early stages of production.
`For example, the yield improvement factor of a 64-Mb
`DRAM through FRT is more than twice that through the
`conventional technique when D is more than 5 cmp2. For a
`
`80
`60
`
`40
`
`20 z
`0 d 10
`F 8
`6
`
`4
`
`2
`
`’
`
`0
`
`2
`4
`6
`8
`DEFECT DENSITY (cm”)
`(a)
`
`
`
`100
`80
`60
`
`40
`
`20 -
`c
`d 10
`0
`5
`8
`6
`
`4
`
`2
`
`
`
`’
`
`0
`
`8
`6
`4
`2
`DEFECT DENSITY ( em2)
`(b)
`
`
`
`100
`80
`
`lGbh
`
`Proposed
`IL 4, R I 16)
`Conventlonal
`(L = R 8)
`
`I
`
`DEFECT DENSITY (em*)
`(C)
`
`Calculated yield with conventional and proposed redundancy
`Fig. 4.
`techniques: (a) 4-Mb DRAM, (b) 64-Mb DRAM, and (c) 1-Gb DRAM.
`
`4
`
`

`
`16
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 1, JANUARY 1991
`
`Sensa AITID.
`
`Stored
`address
`
`FO
`
`F ,
`
`a ,
`
`-
`a1
`
`C l
`
`Fig. 5. Defect modes in memory array using shared amplifier, shared
`1 / 0 scheme, and multidivided data-line structure.
`
`X
`
`unblown
`
`unblown
`
`0
`1
`
`1
`0
`
`1
`1
`
`
`
`1
`
`1
`
`
`
`TABLE I
`NUMBER OF SPARE DECODERS REQUIRED
`TO REPAIR DEFECTS
`
`d
`
`rci
`I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___________________
`from
`circuits other q:.enabie
`
`Spare Decoder
`output
`
`Fig. 6. Address comparison circuit with “don’t care.”
`
`defect can be repaired with a spare decoder in both the
`original and the advanced FRT. However, in the original
`FRT a global defect requires two or more spare decoders,
`while in the advanced FRT it requires only one spare de-
`coder. Therefore fewer spare decoders are reuqired in the
`advanced FRT to repair the same number of defects and to
`achieve the same yield.
`An address-comparison circuit [ 11, [2] in which the “don’t-
`care” value X can be programmed is shown in Fig. 6. This
`circuit has two fuses, F,, and F,. Table I1 shows the program-
`ming method: ZERO or ONE is programmed when one of the
`fuses is blown, and X is programmed when neither fuse is
`blown.
`
`VI. CONCLUSION
`It was pointed out that conventional redundancy tech-
`niques suffer from both area-penalty increase and yield
`degradation with increase in DRAM density. This is caused
`by the increasing numbers of both spare lines and array
`divisions.
`A novel redundancy technique (FRT) featuring a flexible
`relationship between spare lines and spare decoders was
`proposed to solve these problems. This technique provides a
`higher usage efficiency of both spare lines and spare de-
`coders as well as a lower probability of unsuccessful repair
`due to spare-line defects. The yield improvement factor for
`DRAM’S of 64 Mb and beyond with this technique was
`estimated to be more than twice that through conventional
`techniques in the early stages of production. A revised FRT
`that can effectively repair global defects was also proposed.
`
`Data line
`Sense amp
`
`(with “don’t care”)
`1
`1
`
`(without “don’t care”)
`1
`2
`n*
`*n: number of subarrays connected to a YS line.
`
`I
`
`I-Gb DRAM, however, the yield is determined mainly by
`fatal defects, such as those causing excessive standby current.
`Therefore some alternative technique will be required for
`repairing such defects.
`
`V. ADVANCED FLEXIBLE REDUNDANCY TECHNIQUE
`Although word-line redundancy has been mainly described
`so far, FRT can also be applied to data-line redundancy.
`However, in this case the problem of a “global” defect, i.e., a
`defect over two or more subarrays, arises. Fig. 5 shows
`various defect modes in a DRAM using the shared amplifier
`and shared 1 / 0 schemes, and the multidivided data-line
`structure [71. A data-line defect is “local” and produces no
`effect on the other subarrays. However, a sense-amplifier
`defect causes two data lines connected to the amplifier to
`fail simultaneously. A YS-line defect causes all the data lines
`connected to the YS line to fail simultaneously. Thus these
`types of defects are “global.” Since only one defective nor-
`mal line is replaced by a spare line in FRT, more than one
`spare decoder is needed to repair a global defect. This may
`result in a deficiency of spare decoders.
`To solve this problem, a revision of the FRT is proposed.
`This revised technique features not only ZERO and ONE, but
`also a “don’t-care’’ value X , which can be programmed into
`a spare decoder. The “don’t-care’’ value X is assumed to
`coincide with both ZERO and ONE. Programming X
`in a
`spare decoder specifies that the address bit is not compared
`with the input address in the decision regarding the defective
`address. For example, one sense-amplifier defect can be
`repaired by programming X at the inter-subarray address bit
`that specifies a left/right subarray of the sense amplifier,
`and by programming ZERO or ONE at the other address bits.
`This is because the intra-subarray address is common to the
`two defective data lines.
`Table I shows the numbers of spare decoders required to
`repair the various defects shown in Fig. 5. A data-line (local)
`
`5
`
`

`
`HORIGUCHI et al.: FLEXIBLE REDUNDANCY TECHNIQUE FOR DRAM’S
`
`17
`
`ACKNOWLEDGMEN
`I
`The authors wish to thank H. Kawamoto, M. Ishihara, T.
`Shinoda, K. Kajigaya, and K. Ohshima for their helpful
`suggestions and discussions.
`
`REFERENCES
`
`as
`
`Masakazu Aoki (M’76-S’81 -M’82) received the
`B.S. degree in applied physics from Tokyo Uni-
`versity, Tokyo, Japan, in 1971, and the M.S.
`degree in electrical engineering from the Uni-
`versity of Michigan, Ann Arbor, in 1982.
`Since joining the Central Research Labora-
`tory, Hitachi Ltd , Tokyo, Japan, in 1971, he has
`been engaged in work on linear and area image
`sensors as well as CMOS memory circuits and
`devices. Currently he is working on high-density
`DRAM development.
`Mr. Aoki is a member of the Institute of Electronics, Information and
`Communication Engineers Of Japan
`
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`[4] K. Shimohigashi et al., “Redundancy techniques for dynamic
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`on January 5, 1941. He received the B S and
`Ph.D. degrees in electronics from Tohoku Uni-
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`In 1963 he joined the Central Research Labo-
`853-860, June 1979
`[6] R. T. Smith et al., “Laser programmable redundancy and yield
`ratory, Hitachi Ltd, Tokyo, Japan, where he
`improvement in a 64K DRAM,” IEEE J . Solid-State Circuits,
`was first involved in core memory design After
`that he was engaged in characterization of
`vol. SC-16, pp. 506-514, Oct. 1981.
`[7] K. Itoh, “Trends in megabit DRAM circuit design,” in 1989
`plated-wire memory element and design of
`Int. Symp. VLSI Technology, Syst. Applications, Proc. Tech.
`plated-wire memory system. Since 1972 he has
`Papers, May 1989, pp. 21-27.
`been working on DRAM developments from 4 kb to 64 Mb. In his long
`[SI R . Hori et a l , “An experimental 1 Mbit D R A M based on high
`DRAM experience he has proposed and developed leading technologies
`S/N design,” IEEE J. Solid-State Circuits, vol. SC-19, pp.
`such as a single 5-V NMOS DRAM, a single 5-V 64-kb NMOS DRAM
`using a folded data-line arrangement, CMOS DRAM’s, exploratory
`634-640, Oct. 1984.
`[9] S. E. Schuster, “Multiple word/bit line redundancy for semi-
`developments of on-chip voltage limiter DRAM’s, a proposal of a
`conductor memories,” IEEE J . Solid-State Circuits, vol. SC-13, multidivided data-line structure combined with shared I/O’s, a DRAM
`pp. 698-703, Oct. 1978.
`chip using a trench capacitor cell, systematic analysis and evaluation of
`[ 101 C. H. Stapper, “ O n yield, fault distributions, and clustering of
`soft-error mechanisms, data-line interference noise analysis and its
`particles,” IBM 1. Res DeLelop., vol 30, pp. 326-338, May
`reduction, BiCMOS DRAM’s, and a 15-V DRAM. He became a chief
`1986.
`researcher in Hitachi Central Research Laboratory in 1983. His respon-
`sibilities include developing the innovative CMOS and BiCMOS DRAM
`circuits suitable for deep-submicrometer devices, guiding and encourag-
`ing the fabrication process, and device and simulation technology devel-
`opment groups. He has published more than 50 articles in technical
`journals and conferences.-In addition, he has contributed to about 300
`patent applications including a folded data-line arrangement, an on-chip
`voltage limiter scheme, a multidivided data line, BiCMOS DRAM, and
`so on.
`Dr. Itoh is a Senior Member of the IEEE Electron Devices Society
`and a member of the Institute of Electronics, Information and Commu-
`nication Engineers of Japan. He won the IEEE Electron Devices Society
`1984 Paul Rappaport Award. He was awarded the prize of the governor
`of Tokyo Metropolitan for outstanding inventions and research in 1988,
`and received the National Invention Award, the prize of the president of
`the attorney’s association of Japan, for a DRAM invention (folded
`data-line arrangement) in 1989. In 1990 he received the Achievement
`Award of the Institute of Electronics, Information and Communication
`Engineers of Japan.
`
`Masashi Horiguchi (M’8h) was born in Hyogo,
`Japan, on March 18, 1955. He received the B.S.
`degree in electronic engineering and the M.S.
`degree in information engineering from the
`University of Tokyo, Tokyo, Japan, in 1977 and
`1979, respectively.
`He joined the Central Research Laboratory,
`Hitachi Ltd., Tokyo, Japan, in 1979. H e has
`been engaged in the research and development
`of MOS dynamic memories.
`Mr. Horiguchi is a member of the Institute of
`Electronics. Informatic
`In and Communication Engineers of Japan.
`
`Jun Etoh was born on August 20, 1950. He
`graduated from Ogata Technical High School,
`Oita, Japan, and Hitachi Technical College,
`Yokohama, Japan, in 1969 and 1972, respec-
`tively.
`In 1969 he joined the Central Research Labo-
`ratory, Hitachi Ltd., Tokyo, Japan. Since 1969
`he has been engaged in work on MOS-in-
`tegrated circuits, especially for dynamic memo-
`ries.
`Mr. Etoh is a member of the Institute of
`Electronics, Information and Communication Engineers of Japan.
`
`Tetsurou Matsumoto was born in Hiroshima,
`Japan, on April 26, 1950. He received the B.S.
`degree in electronics and communication
`in
`1973, and the M.S. degree in electronics in 1975,
`both from Waseda University, Tokyo, Japan.
`In 1975 he joined the Device Development
`Center, Hitachi Ltd., Tokyo, Japan, and has
`been engaged in the design of MOS dynamic
`RAM’S.
`
`6