UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`MICRON TECHNOLOGY, INC.
`
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`
`Patent Owner
`
`
`
`Patent No. 5,894,441
`Issue Date: Apr. 13, 1999
`Filed: Mar. 31, 1998
`Inventor: Shigeyuki Nakazawa
`Title: SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY
`CIRCUIT
`
`Inter Partes Review No. IPR2016-00094
`
`____________________________________________________________
`
`
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`
`
`
`
`Apple – Ex. 1010
`Apple Inc., Petitioner
`1
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`

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`IPR2016-00094: Patent Owner’s Preliminary Response
`
`Table of Contents
`
`Page
`
`I. 
`
`II. 
`
`INTRODUCTION ........................................................................................... 1 
`
`SUMMARY OF THE ‘441 PATENT ............................................................. 2 
`
`A. 
`
`B. 
`
`The Inventions Disclosed in the ‘441 Patent ..................................... 2 
`
`Level of Ordinary Skill in the Art ..................................................... 6 
`
`C.  Claim Interpretation ........................................................................... 7 
`
`1. 
`
`“transfer gate” ............................................................................. 8 
`
`III.  CLAIMS 1–3 AND 5 ARE NOT AT ISSUE IN THE RELATED
`DISTRICT COURT LITIGATION ................................................................. 9 
`
`IV.  THE PETITION FAILS TO ESTABLISH A REASONABLE
`LIKELIHOOD THAT MICRON WILL PREVAIL AS TO ANY OF
`THE GROUNDS ASSERTED AGAINST CLAIMS 6–15 OF THE
`‘441 PATENT ................................................................................................ 10 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`Legal Standard .................................................................................. 11 
`
`Summary of McAdams (U.S. Patent No. 5,270,975) ...................... 14 
`
`Summary of Minami (Japanese Unexamined Patent
`Application Publication H06-52696) ............................................... 22 
`
`The Petition Fails To Establish That Claims 6 Through 15
`Are Obvious Over McAdams In View Of Minami, Because
`The Petition Does Not Establish Reason To Combine
`McAdams And Minami .................................................................... 25 
`
`1. 
`
`The Petition Ignores Fundamental Differences Between
`McAdams And Minami: Adding Minami’s Structure to
`McAdams Unnecessarily Adds Structure to Duplicate
`Function Already Built Into McAdams .................................... 25 
`
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`IPR2016-00094: Patent Owner’s Preliminary Response
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`2. 
`
`The Petition’s Alleged Reasons to Modify McAdams
`with Minami Fail to Provide a Rational Unpinning for the
`Combination .............................................................................. 29 
`
`V. 
`
`THE PETITION FAILS TO ESTABLISH THAT CLAIMS 8 AND
`10 ARE OBVIOUS OVER MCADAMS IN VIEW OF MINAMI,
`BECAUSE THE PROPOSED COMBINATION WOULD RENDER
`MCADAMS INOPERATIVE ....................................................................... 33 
`
`VI.  CONCLUSION .............................................................................................. 35 
`
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`IPR2016-00094: Patent Owner’s Preliminary Response
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`Table of Authorities
`
`Cases
`Activevideo Networks, Inc. v. Verizon Commc’ns, Inc.,
`694 F.3d 1312 (Fed. Cir. 2012) ............................................................................ 13
`Am. Acad. of Sci. Tech. Ctr., In re,
`367 F.3d 1359 (Fed. Cir. 2004) .............................................................................. 7
`Bass, In re,
`314 F.3d 575 (Fed. Cir. 2002) ................................................................................ 7
`CCS Fitness, Inc. v. Brunswick Corp.,
`288 F.3d 1359 (Fed. Cir. 2002) .............................................................................. 7
`Cisco Sys., Inc. v. C-Cation Techs., LLC,
`IPR2014-00454, Paper 12 (Aug. 29, 2014) ............................................. 12, 13, 29
`Cuozzo Speed Techs., LLC, In re,
`778 F.3d 1271 (Fed. Cir. 2015) .............................................................................. 7
`Dow Chem. Co., In re,
`837 F.2d 469 (Fed. Cir. 1988) .............................................................................. 12
`FCA US LLC v. Jacobs Vehicle Sys.,
`IPR2015-01234, Paper 9 (Oct. 23, 2015) ............................................................. 10
`Gordon, In re,
`733 F.2d 900 (Fed. Cir. 1984) .............................................................................. 13
`Graham v. John Deere Co.,
`383 U.S. 1 (1966) ................................................................................................. 12
`ICON Health and Fitness, Inc., In re,
`496 F.3d 1374 (Fed. Cir. 2007) ............................................................................ 30
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 11, 13
`Microsoft Corp. v. Secure Web Conference Corp.,
`IPR2014-00745 Paper 12 (Sep. 29, 2014) ............................................................ 30
`NTP, Inc., In re,
`654 F.3d 1279 (Fed. Cir. 2011) ............................................................... 14, 32, 35
`Rambus, Inc., In re,
`753 F.3d 1253 (Fed. Cir. 2014) .............................................................................. 7
`Star Scientific, Inc. v. R.J. Reynolds Tobacco Co.,
`655 F.3d 1364 (Fed. Cir. 2011) ............................................................................ 14
`Translogic Tech., Inc., In re,
`504 F.3d 1249 (Fed. Cir. 2007) .............................................................................. 7
`Travelocity.com L.P. et al. v. Cronos Technologies, LLC,
`CBM2014-00082 paper 12 (Oct. 16, 2014) ......................................................... 11
`
`
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`Urbanski, In re,
`Case No. 2015-1272 (Fed. Cir. Jan. 8, 2016) ................................................ 13, 14
`Statutes
`35 U.S.C. § 103 ........................................................................................................ 11
`35 U.S.C. § 253 ........................................................................................................ 10
`35 U.S.C. § 313 .......................................................................................................... 1
`Regulations
`37 C.F.R. § 1.321 ..................................................................................................... 10
`37 C.F.R. § 42.100 ..................................................................................................... 7
`37 C.F.R. § 42.107 .............................................................................................. 1, 10
`37 C.F.R. § 42.108 .............................................................................................. 2, 11
`37 C.F.R. § 42.73 ..................................................................................................... 10
`Other Authorities
`Office Trial Practice Guide,
`77 Fed. Reg. 48,756 (Aug. 14, 2012) ..................................................................... 7
`
`
`
`
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`IPR2016-00094: Patent Owner’s Preliminary Response
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`I.
`
`INTRODUCTION
`
`Patent Owner Limestone Memory Systems LLC (“LMS”) respectfully
`
`submits this Preliminary Response in accord with 35 U.S.C. § 313 and 37 C.F.R.
`
`§ 42.107, responding to the Petition for Inter Partes Review (“the Petition”) filed
`
`by Micron Technology, Inc. (“Micron” or “Petitioner”) regarding claims 1-3, and
`
`5-15 of United States Patent No. 5,894,441 (“the ‘441 patent”)1.
`
`With respect to claims 6-15, the Petition fails to articulate a valid reason that
`
`would cause a person of ordinary skill in the art modify the primary McAdams
`
`reference using the teachings of the asserted secondary Minami reference. In
`
`particular, the Petition ignores evidence that the proposed combination would add
`
`1 Micron has also filed four other petitions for inter partes review of four other
`
`patents (5,805,504, 5,943,260, 6,233,181, and 6,697,296) at issue in the co-pending
`
`litigation between the parties, Limestone Memory Sys. LLC v. Micron Tech. Inc.,
`
`8:15-cv-00278 (C.D. Cal.) (“the co-pending litigation”). See IPR2016-00093-
`
`IPR2016-00097. The co-pending litigation, as well as 9 other consolidated suits
`
`against other defendants asserting one or more of the patents at issue in the co-
`
`pending litigation, have been stayed pending the outcome of the Board’s decisions
`
`on institution in these IPRs. See Limestone Memory Sys. LLC v. Micron Tech. Inc.
`
`et al., 8:15-cv-00278 (C.D. Cal.), Doc. 69, January 12, 2016 (Order Granting
`
`Motions to Stay Cases Pending Inter Partes Review).
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`IPR2016-00094: Patent Owner’s Preliminary Response
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`more unwanted extra structure
`
`to McAdams for no discernable benefit.
`
`Accordingly, the Petition does not demonstrate a reasonable likelihood that at least
`
`one of the claims challenged in the Petition is unpatentable. Micron has not met the
`
`high standard required for institution of an inter partes review of claims 6-15. 37
`
`C.F.R. § 42.108(c).
`
`As discussed further below, LMS has disclaimed claims 1-3 and 5 solely in
`
`the interest of efficiency. Those claims are not at issue in the related litigation
`
`between LMS and Micron. Accordingly, no issues remain for trial and the Board
`
`should deny the Petition in its entirety.
`
`II.
`
`SUMMARY OF THE ‘441 PATENT
`
`A.
`
`The Inventions Disclosed in the ‘441 Patent
`
`The ‘441 patent relates to semiconductor memory devices and discloses an
`
`improved redundancy circuit, designed to more efficiently replace defective
`
`bitlines within a memory device by means of a redundant bitline. (Ex. 1001 at 1:5–
`
`9.) The ‘441 patent explains that fine geometry, high integration, and large
`
`capacity of semiconductor memory devices has caused manufacturers of such
`
`devices to include redundancy circuits for correcting defective components in such
`
`devices. (Id. at 1:12–22.) According to the ‘441 patent, such defect correction
`
`circuits “contribute[] significantly to the enhancement of the yield of the
`
`semiconductor memory devices.” (Id. at 1:31–33.) The ‘441 patent further explains
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`IPR2016-00094: Patent Owner’s Preliminary Response
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`that “it is desirable to relieve as many defective word lines or defective bit lines as
`
`possible with a minimum number of redundant word lines or redundant bit lines.”
`
`(Id. at 1:42–45.)
`
`The ‘441 describes the prior art by reference to figure 1, which illustrates a
`
`semiconductor memory device with a normal cell array region 102 and a redundant
`
`cell array region 104. (Id. at 3: 1–5.)
`
`(Id. at FIG. 1.) The ‘441 patent specifically describes the known column
`
`
`
`redundancy circuit as follows.
`
`
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`On the other hand, the column redundancy decoder 116 detects the
`supply of the Y address corresponding to a defective bit line. The
`column redundancy decoder 116 also includes a plurality of fuse
`elements, and stores the Y address corresponding to a defective bit
`line according to whether or not these fuses are blown out. In other
`words, when the Y address corresponding to the defective bit line is
`supplied, the decoder 116 deactivates the column decoder 108 by
`supplying an inhibit signal 134 to the column decoder 108, and
`activates the redundant column selection driver 114 in order to
`activate a specified redundant column selection line 130. In this way,
`the defective bit line is replaced by a redundant bit line (not shown)
`corresponding to the redundant column selection line 130.
`
`(Id. at 3:47–60.) Thus, it was known to replace an entire column if one bitline on
`
`the column was defective. (Id. at 3:61–65.) This arrangement used the redundant
`
`circuits inefficiently because every bitline associated with the column selection
`
`line had to be replaced to correct a single defective bitline. (Id. at 3:61–4:5.)
`
`The ‘441 patent discloses and claims an improved memory device that is
`
`capable of more efficiently using the redundant column selection lines. (See, e.g.,
`
`id. at FIG. 2, 4:10–5:20.) An embodiment of the inventive device is illustrated in
`
`figure 2, in which the most significant bit of the X address (represented by
`
`complementary values XA0 and XA1) is supplied to the column redundancy
`
`decoder 216. (Id. at 4:20–30.) Fuse blocks within the column redundancy decoder
`
`are used to store the address of columns that need to be replaced. (Id. at 5:35–52.)
`
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`By supplying the X address bits to the column redundancy decoder, the column
`
`redundancy decoder can identify what part of the column select line includes the
`
`defective bitline. (Id. at 6:13–39.)
`
`(Id. at FIG. 2 (annotations added).) In short, normal bitlines in the portion of the
`
`normal memory array 202 highlighted in red are replaced by redundant bitlines in
`
`the portion of the redundant array 204 highlighted in red. (Id. at 6:5–26.) Similarly,
`
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`the normal bitlines in the portion of the normal memory array 202 highlighted in
`
`green are replaced by redundant bitlines in the portion of the redundant array 204
`
`highlighted in green. (Id. at 6:46–67.)
`
`The ‘441 patent explains that this arrangement is advantageous because it
`
`means that only half of the bitlines on a given column select line are replaced with
`
`redundant bitlines. (Id. at 6:40–45, 7:13–18.) This makes more efficient use of the
`
`redundant bitlines because fewer redundant bitlines are used to replace each
`
`defective normal bitline. (Id. at 2:23–28.)
`
`B.
`
`Level of Ordinary Skill in the Art
`
`Neither the Petition nor the supporting Baker Declaration offers any basis
`
`for arriving at any particular level of skill. At most, the Petition is supported by the
`
`conclusory statements of Dr. Baker. (See Pet. at 11; Ex. 1003 at ¶ 49.)
`
`Further, although Dr. Baker apparently has (and had) substantially more
`
`experience than the person of ordinary skill at the time of the invention, neither the
`
`Petition nor the supporting declaration offers any analysis of how the hypothetical
`
`person’s skill would differ from Dr. Baker’s own knowledge and skill. By 1997,
`
`the priority date of the ‘441 patent, Dr. Baker was already an assistant professor at
`
`the University of Idaho with at least six years of academic and ten years of industry
`
`experience. (See Ex. 1004 at .002–.004.) Thus, his personal experience even at the
`
`time of the invention greatly exceeded the level of skill advocated by the Petition.
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`Further, the passage of time and massive improvements in the technology make
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`hindsight bias a significant concern, particularly with respect to Dr. Baker’s
`
`reasons for combining prior art references.
`
`C. Claim Interpretation
`
`In an inter partes review, the Board construes claim terms in an unexpired
`
`patent using their broadest reasonable construction in light of the specification of
`
`the patent in which they appear. 37 C.F.R. § 42.100(b); Office Trial Practice
`
`Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012); In re Cuozzo Speed Techs.,
`
`LLC, 778 F.3d 1271, 1282-83 (Fed. Cir. 2015), cert. granted, 577 U.S. ___ (Jan.
`
`15, 2016) (No. 15-446). The claim language should be read in light of the
`
`specification as it would be interpreted by one of ordinary skill in the art. In re
`
`Rambus, Inc., 753 F.3d 1253, 1255 (Fed. Cir. 2014); In re Am. Acad. of Sci. Tech.
`
`Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (citing In re Bass, 314 F.3d 575, 577
`
`(Fed. Cir. 2002)). There is a “heavy presumption” that a claim term carries its
`
`ordinary and customary meaning. CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d
`
`1359, 1366 (Fed. Cir. 2002). The “ordinary and customary meaning” is that which
`
`the term would have to a person of ordinary skill in the art in question in the
`
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`
`(Fed. Cir. 2007).
`
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`1. “transfer gate”
`The phrase “transfer gate” is an element of dependent claims 3 and 13 of the
`
`‘441 patent. LMS does not agree with the Petition’s definition of this phrase. For
`
`the reasons explained below, the phrase is properly construed to be a “component
`
`or circuit that selectively transfers a signal in response to a control input.” The
`
`Petition improperly defines the phrase as “logic that transfers the logic value of a
`
`signal.”
`
`Claims 3 and 13 and the specification use the phrase “transfer gate” to
`
`indicate a device that is controlled by a first signal, and which selectively transfers
`
`a second signal. In relevant part, claim 3 recites “a transfer gate controlled by said
`
`part of said row address to transfer said detection signal.” Similarly, in relevant
`
`part, claim 13 recites
`
`first and second transfer gates, said first transfer gate being activated
`to transfer said first matching signal to said redundant column
`selection line responsive to said second word line being activated,
`said second transfer gate being activated to transfer said second
`matching signal to said redundant column selection line responsive to
`said first word line being activated.
`
`The specification is also consistent with this characterization. For example, the
`
`specification explains the function of the two transfer gates as follows.
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`IPR2016-00094: Patent Owner’s Preliminary Response
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`The transfer gate 310 outputs the matching signal 306 as the YRED
`when XA0 is at the high level, and the transfer gate 312 outputs the
`matching signal 308 as the YRED when XA1 is at the high level.
`
`(Ex. 1001 at 5:57-61; see also FIG. 3 (illustrating transfer gates 310 and 312 in the
`
`context of a column redundancy decoder circuit).)
`
`
`
`The construction proposed in the Petition imports several concepts that
`
`simply do not appear in the claims or the specification, making the construction
`
`improper in the overall context of the ‘441 patent. The specification and the claims
`
`consistently describe the transfer gate as a physical component of a circuit, not
`
`“logic” as proposed by the Petition. Similarly, the specification and the claims
`
`consistently describe a component outputting a “signal,” not a “logic value of a
`
`signal.”
`
`The differences in the respective claim constructions do not appear to affect
`
`the outcome of this matter. Nevertheless, for all of the reasons above “transfer
`
`gate” is properly construed to mean “component or circuit that selectively transfers
`
`a signal in response to a control input.”
`
`III. CLAIMS 1–3 AND 5 ARE NOT AT ISSUE IN THE RELATED
`DISTRICT COURT LITIGATION
`
`Initially, LMS notes that of the challenged claims 1-3 and 5-15, only claims
`
`6-12 and 14-15 are at issue in the co-pending litigation. Micron filed the Petition
`
`two days after LMS served its infringement contentions in the co-pending
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`litigation, but chose to argue that certain non-asserted claims were invalid. To
`
`reduce the issues for the Board to consider, LMS has disclaimed claims 1-3 and 5
`
`under 35 U.S.C. § 253(a) in compliance with 37 C.F.R. § 1.321(a). (See statutory
`
`disclaimer, Ex. 2001.) Accordingly, only the challenge of claims 6-15 as being
`
`obvious in view of U.S. Patent NO. 5,270,975 to McAdams (Ex. 1005) in view of
`
`Japanese Unexamined Patent Application Publication No. H06-52696 to Minami
`
`(Ex. 1006) (Ground #2 identified in the Pet. at page 4) need to be considered by the
`
`Board. See 37 C.F.R. § 42.107(e); see also FCA US LLC v. Jacobs Vehicle Sys.,
`
`IPR2015-01234, Paper 9 at 3 (Oct. 23, 2015) (denying institution of inter partes
`
`review of statutorily disclaimed claims and finding such disclaimer not a request
`
`for adverse judgement under 37 C.F.R. § 42.73(b)).
`
`IV. THE PETITION FAILS TO ESTABLISH A REASONABLE
`LIKELIHOOD THAT MICRON WILL PREVAIL AS TO ANY OF
`THE GROUNDS ASSERTED AGAINST CLAIMS 6–15 OF THE ‘441
`PATENT
`
`Inter partes review should not be granted with respect to claims 6–15
`
`because the Petition does not demonstrate a reasonable likelihood of success. With
`
`respect to the alleged ground of invalidity, the Petition presents snippets of the
`
`references out of context thereby ignoring the full disclosure of the references and
`
`fails to address contradictory evidence undermining its reasons to combine
`
`references. Absent any other reason to combine the references, the combination
`
`appears to be supported only by improper hindsight bias.
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`Moreover, the Petition does not adequately support its contentions regarding
`
`the person of ordinary skill in the art. (See Pet. at 11; Ex. 1003 at ¶¶ 49–50.) The
`
`level of skill in the art underpins every obviousness contention in the Petition, and
`
`therefore affects the likelihood of finding the differences between the art and the
`
`claims non-obvious. Absent factual support for its contention, the Petition fails to
`
`provide any proper basis for evaluating the person of ordinary skill in the art.
`
`For each of these reasons, claims 6–15 are not obvious over McAdams in
`
`view of Minami, and the Petition fails to demonstrate a reasonable likelihood of
`
`success on this ground.
`
`A.
`
`Legal Standard
`
`As the Petitioner, Micron bears the burden of demonstrating a reasonable
`
`likelihood that it would prevail in showing unpatentability on the grounds asserted
`
`in its Petition. 37 C.F.R. § 42.108(c); See Travelocity.com L.P. et al. v. Cronos
`
`Technologies, LLC, CBM2014-00082 paper 12 at 9-10 (Oct. 16, 2014) (denying
`
`request for rehearing after declining to institute trial, notwithstanding that the
`
`grounds had not been argued in Patent Owner’s Preliminary Response).
`
`Under 35 U.S.C. § 103, Petitioner must prove that the claimed subject matter
`
`would have been obvious to a person of ordinary skill in the art at the time of the
`
`invention. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). In considering
`
`obviousness, the Board must determine the scope and content of the prior art,
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`differences between the prior art and the claims and the level of ordinary skill in
`
`the pertinent art, as well as consider any objective indicia of nonobviousness.
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`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). A reference must be
`
`considered for all that it teaches, including disclosures that diverge and teach away
`
`from the invention at hand. In re Dow Chem. Co., 837 F.2d 469, 473 (Fed. Cir.
`
`1988).
`
`Obviousness requires more than simply pointing out that two references
`
`relate to the same field of endeavor. For example, in Cisco, the Petitioner asserted
`
`that the combination of prior art references Thompson and Cioffi disclosed each of
`
`the limitations of the claim at issue. The Petitioner argued that:
`
`The motivation to combine is in the prior art references: to implement
`different architectures that extend various services to users. The prior
`art references are in the same field of endeavor: multi-access
`communication protocols in multi-access communication systems and
`proposed
`solutions
`to
`common problems of multi-access
`communication protocols.
`
`Cisco Sys., Inc. v. C-Cation Techs., LLC, IPR2014-00454, Paper 12 at 14 (Aug. 29,
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`2014). The Board held this explanation did not provide “sufficient articulated
`
`reasoning with rational underpinning explaining which elements of Thompson
`
`would be combined with those of Cioffi, and why one with ordinary skill in the art
`
`would modify the teachings of Thompson in view of Cioffi’s teachings to arrive at
`
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`the claimed invention.” Id. To determine whether there was a reason to combine
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`known elements in the manner claimed, it is often necessary to “look to
`
`interrelated teachings of multiple patents; the effects of demands known to the
`
`design community or present in the marketplace; and the background knowledge
`
`possessed by a person having ordinary skill in the art.” KSR, 550 U.S. at 418.
`
`Petitioner must clearly explain why the invention would have been obvious
`
`with some articulated reasoning and rational underpinning to support the legal
`
`conclusion of obviousness; conclusory statements of obviousness will not suffice.
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`Id. Similarly, any expert testimony must explain in detail how specific references
`
`could be combined, which combinations of elements in specific references would
`
`yield a predictable result, and how any specific combination would operate or read
`
`on the asserted claims. See, e.g., Activevideo Networks, Inc. v. Verizon Commc’ns,
`
`Inc., 694 F.3d 1312, 1327 (Fed. Cir. 2012).
`
`If a proposed combination would render
`
`the prior art reference
`
`unsatisfactory for its intended purpose, then the reference teaches away from the
`
`combination. In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984). In Gordon, the
`
`prior art gasoline filter relied in part upon gravity, meaning that turning that filter
`
`upside down rendered it “inoperable for its intended purpose” and taught away
`
`from that modification. Id. The recent Urbanski case does not contradict this point
`
`of law. In re Urbanski, Case No. 2015-1272 at *9-10 (Fed. Cir. Jan. 8, 2016). The
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`combination at issue in Urbanski did not teach an inoperative method, because the
`
`individual references when taken together taught that “reaction time and degree of
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`hydrolysis are result-effective variables that can be varied in order to adjust the
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`properties of the hydrolyzed fiber in a predictable manner.” Id. at *8. Thus, in
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`Urbanski, the operability of the combined reference was not actually at issue.
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`Importantly, the obviousness inquiry must be taken without any “hint of
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`hindsight,” Star Scientific, Inc. v. R.J. Reynolds Tobacco Co., 655 F.3d 1364, 1375
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`(Fed. Cir. 2011), so as to avoid “reconstruction by using the patent in suit as a
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`guide through the maze of prior art references, combining the right references in
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`the right way so as to achieve the result of the claims in suit.” In re NTP, Inc., 654
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`F.3d 1279, 1299 (Fed. Cir. 2011) (internal citation omitted).
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`B.
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`Summary of McAdams (U.S. Patent No. 5,270,975)
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`The Petition cites U.S. Patent No. 5,270,975 to McAdams as the primary
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`reference in each of its grounds for invalidity. McAdams relates to semiconductor
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`memory devices that include repair circuitry for eliminating defects in memory
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`devices. (Ex. 1005 at 1:9–12.)
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`Although McAdams discloses certain features for efficiently using
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`redundant column select lines, it also emphasizes that decoder circuits should be
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`used efficiently. McAdams explains that it was known to include all support
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`circuitry for redundant memory cells within the individual data blocks with the
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`redundant cells. (Id. at 2:50–57.) Such support circuitry included address circuitry
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`used to activate redundant row and column lines within the blocks. (Id.) McAdams
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`teaches a different approach, explaining the benefits of optimizing this support
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`circuitry:
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`Now, due to cost constraints which limit the package size of higher
`density circuits, it is undesirable to repeat for each memory data block
`all of the support circuitry needed to replace defective cells. By way
`of example, redundant column select circuitry need not be repeated
`for each data block. In fact, it is more space efficient to generate the
`repair column select signals for all of the data blocks with one series
`or bank of decoder circuits.
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`(Id. at 2:58–65.) In alleged contrast to the known art, McAdams discloses “a
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`redundancy scheme which includes a predetermined number of decoder circuits
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`and is more space efficient or more effective than other redundancy schemes
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`having the same number of decoder circuits.” (Id. at 3:3–7.)
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`McAdams discloses three ways of optimizing the number of decoder
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`circuits. First, McAdams discloses “sharing of support circuitry among data
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`blocks.” (Id. at 2:66–67.)
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`(Id. at FIG. 5 (emphasis added to illustrate how one YRS enable logic block
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`connects to all four data blocks 12).) In the embodiment shown in figure 5,
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`McAdams illustrates shared comparator decoders 40 that are shared across each of
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`four memory blocks. (Id. at FIG. 5, 8:8–16 (“all of the decoders 40 in a particular
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`group SSi are wired to turn on the same redundant select line YRSi (i=1,N) in all of
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`the data blocks”) (emphasis added).) A second stage of fusible decoders provides
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`data block select logic 42 to identify the data block assigned to each decoder 40.
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`(Id. at 8:25–43.) The column repair circuitry can “incorporate a level of row
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`decoding in order to replace defective sections of columns.” (Id. at 7:11–13.)
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`Second, McAdams discloses “assigning multiple decoders to each of the
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`redundant select lines so that each line is capable of replacing multiple defective
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`column portions with multiple redundant column portions which are enabled by the
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`same redundant column select line.” (Id. at 3:12–16.)
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`Third, McAdams discloses using a “nonuniform distribution of decoder
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`circuits among the redundant select lines.” (Id. at 3:16–19.) According to
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`McAdams:
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`Based on random defect distributions and prediction analyses, it has
`been determined that by allocating decoder circuits to repair columns
`with a nonuniform distribution, the overall number of decoders can be
`reduced without significant loss in repairability.
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`(Id. at 11:50–54.) McAdams discloses an embodiment of this approach in figure 8,
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`which is nearly identical to figure 5 except that the number of segment selects in
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`each comparator decoder 40 is nonuniform. (Id. at 11:44–49 (“Z1, Z2 . . . ZN are
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`not all of the same value”).)
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`Each of the above three ways of optimizing the number of decoder circuits
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`requires flexibility in the memory array and in the circuitry that activates redundant
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`column select lines. McAdams discloses flexible circuitry within the memory array
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`itself that cuts off local data lines for memory cells if a redundant column select
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`line has been activated, which is needed because the McAdams redundant column
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`decoder may activate a redundant column at the same time as a normal column.
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`(Id. at FIG. 3 (relevant portions highlighted below) and FIG. 5 (illustrating
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`different “Enable Logic” for redundant column YRS and a “Decoder” for normal
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`column TS for each memory block 12A and 12B).)
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`Normal Column
`Select Line (YS)
`and Four Column
`Segments (SC1,
`SC2, SC3, and
`SC4)
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`Redundant Column
`Select Line (YRS1)
`and Two Column
`Segments (RSC1,
`RSC2)
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`Redundant Column
`Select Line (YRS2)
`and Two Column
`Segments (RSC3,
`RSC4)
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`Redundant Column
`Select Line (YRSN)
`and Two Column
`Segments
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`(Id. at FIG. 3 (highlighting and annotations added).) As illustrated above, each
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`redundant column select line in figure 3 includes an inverter and two transistors
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`that disable one pair of the local data lines (i.e., D1 and /D1, D2 and /D2, D3 and
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`/D3, or D4 and /D4) if the redundant column select line is active. (Id. at FIG. 3.)
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`McAdams explains that:
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`As schematically illustrated in FIG. 3, each redundant select line YRS
`enables data transfer between each of two constituent subcolumns
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`RSC in a sub-block and a pair of data lines Di, Di associated with
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`each of the paths CI/O1 and CI/O2. More specifically, a logic-high signal
`on redundant select line YRS1 connects each pair of folded bitline
`segments in the two selected redundant sub-columns RSC1 and RSC2
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`to the pairs of data lin