United States Patent c191
`McAdams
`
`[54] MEMORY DEVICE HAVING A
`NON-UNIFORM REDUNDANCY DECODER
`ARRANGEMENT
`
`Inventor:
`[75]
`[73] Assignee:
`
`Hugh McAdams, Houston, Tex.
`
`Texas Instruments Incorporated,
`Dallas, Tex.
`
`[21) Appl. No.: 928,634
`
`[22) Filed:
`
`Aug. 13, 1992
`
`[51]
`
`Related U.S. Application Data
`(63] Continuation of Ser. No. 714,321, Jun. 11, 1991, aban(cid:173)
`doned, which is a continuation of Ser. No. 501,064,
`Mar. 29, 1990, abandoned.
`Int. o.s ....................... GllC 7/00; GllC 29/00;
`G06F 11/20
`[52) U.S. Cl ................................ 365/200; 365/230.06;
`365/230.03; 371/10.1; 371/10.3
`[58) Field of Search .............. 365/200, 230.03, 230.06;
`371/10.1, 10.2, 10.3
`
`[56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,471,472 9/1984 Young ................................. 365/200
`4,653,050 3/1987 Vaillancourt ....................... 365/200
`4,672,581 6/1987 Waller ................................. 365/200
`4,691,301 9/1987 Anderson ............................ 365/200
`4,807,191 2/1989 Flannagan ........................... 365/200
`4,847,810 7/1989 Tagami ................................ 365/200
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll lllll lllll lllll llllll Ill lllll llll
`US005270975A
`5,270,975
`(11] Patent Number:
`[45) Date of Patent: Dec. 14, 1993
`
`FOREIGN PA TENT DOCUMENTS
`0040700 2/1987 Japan .................................. 371/10.2
`
`Primary Examiner-Glenn Gossage
`Attorney, Agent, or Firm-Robby T. Holland; Lawrence
`J. Bassuk; Richard B. Havill
`ABSTRACT
`[57)
`A memory device including a non-uniform redundancy
`decoder has one or more data blocks with each data
`block having an array of memory cells arranged in
`addressable rows and columns along row lines and col(cid:173)
`umn lines. Each array is configured into sub-blocks
`with each sub-block comprising a plurality of the mem(cid:173)
`ory cells. A given number of repair columns is allocated
`to a data block. A plurality of column repair decoder
`circuits are each connected to a repair column. These
`column repair decoder circuits are programmable with
`column and row address information corresponding to
`a section of an array column contianing a defective
`memory cell to replace the defective cell with a mem(cid:173)
`ory cell in one of the repair columns. Different numbers
`of column repair decoder circuits are connected to the
`first and second column repair circuits, thereby creating
`a nonuniform distribution of column repair circuits. A
`method of assigning the nonuniform redundancy decod(cid:173)
`ers is also disclosed.
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`Dec. 14, 1993
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 8 of 16
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 9 of 16
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`5,270,975
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 10 of 16
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`5,270,975
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 11 of 16
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 12 of 16
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`
`(m·y)=2
`i oo..,.._~....._.;:::--,---r----,---~--,
`90+--+-~~~~~-+-~~~
`
`~ 70-+----+--+--~lli.-~-+-__...;~~
`
`1 ::+---1--4---4--~~----i.-~r--m m tW11
`
`Q.. 40+---T--+--+--+--~-~~
`f! 30
`~
`u-
`20-+----+--+----+--~-+--~~
`
`10-+----+--------4--~-+--i--~
`
`[2] [2] [2] [2]
`
`0+---+--+----4--1---+--1---~
`6
`8
`10
`12
`14
`16
`2
`defects per die
`FIG.9A
`
`(m-y)=2
`i oo,....lliiiiiC'.'"-i----.-.----,.-----,r---..,
`90+--~~~-+--4-~-+----+----l
`
`80· ...... -+--~~--+---+---1--~
`.. ·a so-+----+--+----+---..a.-~_.._~1--~
`~ 70-+----+--+-~~~-+--I--~
`i
`60-+----+---+--+-l~~~--i--~
`fr 40..J.---+------+-~-~~--+. ....... -[3][2}[11
`~ 2011----r----r-~~~-l~U2J l!1c11
`r..
`30
`
`10-+---+-___,~-r--+~+---f3'~
`
`0-+----+--+----4---+---+-~~~
`2
`4
`6
`8
`10
`12
`14 16
`F/G.98
`defects ·per die
`
`MICRON-1005.013
`
`13
`
`

`
`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 13 of 16
`
`5,270,975
`
`100
`90
`80
`~ 70
`..Q e 60
`·-!. so
`t 40
`~ 30
`20
`10
`0
`2
`
`--....... "-
`
`(m-y)=3
`
`" ' "" ~
`,........, ' "
`.._"""
`"' -
`~~
`"'-
`I"-
`
`.....
`
`~
`
`~
`
`[5] [3]
`
`""'io...
`
`~
`
`4
`
`12
`10
`8
`6
`defects per die
`
`16
`14
`FIG. 9C
`
`(m-y)=3
`100~~:::::::-i----r--r----r~-r----,
`901--~~-+-"l''"'r-+---t---t---+-~
`80._--+-__ ....,..~--+-..--1--t----+-~
`
`~ 70+----+----+-"-'l'lr--i-.~t----+-~
`
`-..Q 60+---+--+-~--.llllkt---...;;lir---+---I
`e ·- S0-1---+--+----+~~~~_.___.
`
`cc
`~ 40.!.----l---+.-~~~~e=r-[3][2][1]
`a.. 30·r---r--r----t-~=---r~~~~
`
`~ ~:
`
`tillllc21
`
`0-4---_._-----+--l-~----i-~
`4
`6
`8
`10
`12
`14
`16
`2
`FIG.90
`defects per die
`
`MICRON-1005.014
`
`14
`
`

`
`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 14 of 16
`
`5,270,975
`
`100
`90
`80
`
`QJ 70 --e 60
`·- so
`('G e- 40
`30
`'-
`~ 20
`10
`0
`2
`
`(m-y)=4
`......-...., ~ ..:---... ......
`--~ '-...._,,, ~
`~ ~ ~
`~ '-"'
`- - -
`
`~
`
`4
`
`12
`10
`8
`6
`defects per die
`
`14
`
`16
`FIG.9E
`
`(m-y)=4
`lOO,-;;;;,;::s::;::r1-1111--i
`90+---+-~~a...c+--+--t---+-----l
`
`80+---t--"'t-----il~~-t---+---i
`
`QJ 70+---+--~~~~i:---t---+----I
`
`-..c
`e 60
`·~ ~~1--r----t----t-'lic--i-~-..------1i1 ljl [ 1]
`
`~
`
`2 2 [2]
`
`20+----+---+----+--+-~t--~~
`10+---t---;------r--;--f""Oilc--+----t
`0-4---_.__...____,.. _ _._ ____ - 1 - -= -
`6
`8
`10
`12
`2
`14
`16
`4
`FIG9F
`defects per die
`
`MICRON-1005.015
`
`15
`
`

`
`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 15 of 16
`
`5,270,975
`
`% Repairable vs Nun1ber of defects per die
`vs Number of Row Addresses per redundant
`decoder for [4][3][1] redundancy scheme
`100
`........ -..........
`~ .................. --......._
`90
`~ -
`' ""-. -. ....
`"'
`' ' "
`.... ""
`'
`
`~
`
`~ ~
`
`4 Row Addresses (m-y)=4
`3 Row Addresses (m-y)=3
`
`l Row Addresses (m-y)=2
`
`4
`
`10 12
`8
`6
`defects per die
`
`14 16
`FIG. IOA
`
`~
`
`Q)
`
`80 -
`-e 70
`.... 60 = fr so
`
`40
`s-
`~ 30
`20
`10
`0
`2
`
`~ 70 e 60
`..... 50 = Q.. 40
`CJ
`s- 30
`~ 20
`10
`0
`2
`
`o/o Repairable vs Number of defects per die
`vs Number of Row Addresses per redundant
`decoder for [5][2][1] redundancy scheme
`100
`90
`80
`
`4 Row Addresses
`3 Row Addresses
`
`r~ ~ ""' -
`
`...............
`~ ...
`~ .........
`
`"'
`
`'
`
`4
`
`12
`10
`8
`6
`defects per die
`
`14
`16
`FIG. IOC
`
`MICRON-1005.016
`
`16
`
`

`
`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 16 of 16
`
`5,270,975
`
`-.;;;;;::: --..-- ...
`
`CV -..c
`E ·-=
`
`o/o Repairable vs Nu1nber of defects per die
`vs Nu1nber of Row Addresses per redundant
`decoder for [4][2][2] redundancy scheme
`100
`90
`80
`70
`60
`50
`~ 40
`'-
`30
`20
`10
`0
`2
`
`""" ~ ~ ' ~""" ~ "' ~ ~
`'' -' "
`
`4 Row Addresses
`3 Row Addresses
`2 Row Addresses
`
`'
`
`"'
`
`4
`
`12
`10
`8
`6
`defects per die
`
`16
`14
`FIG.108
`
`MICRON-1005.017
`
`17
`
`

`
`1
`
`5,270,975
`
`MEMORY DEVICE HAVING A NON-UNIFORM
`REDUNDANCY DECODER ARRANGEME!\'T
`
`2
`time. As a result memory architectures, which have
`already become relatively complex, are likely to be(cid:173)
`come even more elaborate as device densities increase.
`In order to improve performance, it is now common(cid:173)
`This application is a continuation of application Ser.
`place to partition higher density memory arrays into
`No. 07/714,321 filed Jun. 11, 1991, now abandoned;
`logical data blocks wherein all cells associated with a
`is a continuation of application Ser. No.
`which
`particular block have common I/O paths. With this
`arrangement, data blocks in an array can be individually
`07/501,064 filed Mar. 29, 1990, also now abandoned.
`accessed. Accordingly, each data word, e.g., possibly
`The present invention relates to semiconductor mem(cid:173)
`10 16 or 32 bits wide in a 64 Megabit device, could be
`ory devices and, more particularly, to devices which
`stored entirely within one of the blocks so that the
`include repair circuitry for eliminating defects in mem(cid:173)
`entire word can be retrieved from the memory at a
`ory devices.
`given time. Thus, there is no loss in availability of data.
`BACKGROUND OF THE INVENTION
`Advantageously, the blocks in a partitioned array have
`In the fabrication of semiconductor memory devices, 15 shorter signal paths, smaller propagation delays and
`hence faster access times. Further, since only one of
`it is common for an array of memory cells to include
`one or more defects which prevent the proper perfor-
`many blocks is accessed at a time, the overall device
`mance of the memory circuit. If a type of defect occurs
`power consumption is also reduced.
`Such partitioning requires that at least some of the
`systematically it can often be causally analyzed and
`designed out. Other defects which are generally not 20 support circuitry, which functions to select desired
`systematic include short circuits between adjacent col-
`memory locations as well as to sense and maintain data
`umns and open circuits within individual columns of
`states, be repeated for each data block. When the con-
`memory cells. For analysis purposes, the distribution of
`cept of internally partitioning a memory array into
`such defects in a memory device, as well as the distribu-
`smaller logical data blocks was introduced, the memory
`tion of the number of defects among a given production 25 densities were lower than now achievable and repeti-
`tion of support circuitry for each data block was an
`lot, may be considered random so that the yield of good
`devices in a lot can be modelled according to a Poisson
`acceptable cost in view of the above-noted performance
`distribution function. Typically, over the period of time
`benefits. That is, the resulting increase in chip size over
`that a particular device or family of devices is being
`that required for a slower, more power consuming
`produced in a given manufacturing facility, the product 30 array design was not critical.
`Now, with the development of even denser memory
`yield can be improved by removing causes, e.g., partic-
`ulate matter, of the above-mentioned random defects.
`devices, the requisite reduction in feature sizes renders
`In many fabrication processes, the causes of random
`these circuits susceptible to defects caused by particu-
`defects cannot be completely eliminated and it is desir-
`late matter which previously caused no problems in the
`able to further improve the yield of memory devices 35 fabrication process. Thus, with further improvements in
`with redundant circuitry. During testing of a chip, de-
`circuit density, there will be a greater challenge to elim-
`fective memory cells can be identified and replaced.
`inate random-type defects. Accordingly, greater reli-
`ance may be placed on redundant circuit repair
`Such redundancy techniques are especially suited for
`semiconductor memories because large numbers of
`schemes.
`repeating elements are arranged in columns and rows. 40
`In theory, by providing a sufficient number ofredun-
`This array format lends itself to replacement of a defec-
`dant circuits on a device, all column defects of the type
`tive column or row with any of multiple identical re-
`described above would be repairable in order to maxi-
`dundant columns or rows.
`mize the yield of a production lot. Practically, however,
`A redundant circuit scheme may be implemented
`cost effectiveness usually dictates that space constraints
`with a plurality of universal decode circuits connected 45 will limit the quantity of redundant circuits to be placed
`on each integrated circuit. It is undesirable to increase
`to the redundant columns. To activate the redundant
`circuitry, appropriate fuses ar included for program-
`repair circuitry in proportion to memory density.
`ming individual decoder circuits to be responsive to the
`addresses of defective memory cells. For example, in
`dynamic random access memory devices (DRAM's), so
`address integrity can be maintained by simply program(cid:173)
`ming redundant column circuits to respond to defective
`column addresses. Thus, the address of each defective
`column is assigned to a redundant column circuit. In
`video and frame memory circuits, the replacement pro- 55
`cedure may require greater complexity in order to
`maintain the sequential nature of memory output. See
`U.S. Pat. No. 4,598,388 assigned to the assignee of the
`present invention.
`Semiconductor memories of all types are being made 60
`with progressively higher bit densities and smaller cell
`sizes as the density of integrated memory circuits in(cid:173)
`creases. In 1972, 4K bit DRAMs were being designed,
`while in 1982; one megabit devices were planned. Six(cid:173)
`teen megabit device densities will become mass pro- 65
`duced during the 1990's. As memory capacity continues
`to progress, there must be further improvement in asso-.
`ciated performance parameters such as memory access
`
`SUMMARY OF THE INVENTION
`In the past, redundancy schemes have consisted of
`only a few extra rows and columns in order to replace
`up to a predetermined maximum number of defective
`elements. As long as each logical data block of an inter(cid:173)
`nally partitioned memory device included separate ad(cid:173)
`dress circuitry, the inclusion of sufficient redundant
`row and column lines within these data blocks did not
`present difficulties.
`Now, due to cost constraints which limit the package
`size of higher density circuits, it is undesirable to repeat
`for each memory data block all of the support circuitry
`needed to replace defective cells. By way of example,
`redundant column select circuitry need not be repeated
`for each data block. In fact, it is more space efficient to
`generate the repair column select signals for all of the
`data blocks with one series or bank of decoder circuits.
`Although sharing of support circuitry among data
`blocks results in significant saving of space for a circuit
`layout, it is now recognized that such schemes both
`
`MICRON-1005.018
`
`18
`
`

`
`5,270,975
`
`SO
`
`3
`4
`of memory cells and column address circuitry for SC·
`complicate and reduce the efficiency of prior art repair
`lecting a memory cell in a column which intersects a
`techniques.
`It is an object of the invention to provide a rcdun·
`selected row. A second group of memory cells is ar-
`ranged in a plurality of repair columns. Each repair
`dancy scheme which includes a predetermined number
`column includes a repair subcolumn for each sub-block
`of decoder circuits and is more space efficient or more
`effective than other redundancy schemes having the
`of memory cells in the logical data block. Address rc-
`samc number of decoder circuits.
`pair circuitry is provided for replacing subcolumns in
`the array with repair subcolumns. The repair circuitry
`According to the invention, a method is provided for
`maximizing the repair efficiency of a redundancy
`includes a plurality of programmable repair column
`scheme wherein a given number of redundant or repair 10 decoders for selecting a repair subcolumn or a segment
`columns arc allocated to a data block of memory cells.
`of multiple repair subcolumns based on row and column
`The method involves assigning multiple decoders to
`address information. The number of decoders allocated
`each of the redundant select lines so Jhat each line is
`to different repair columns is nonuniform.
`capable of replacing multiple defective column portions
`With this scheme, incorporating a level of row de-
`with multiple redundant column portions which are IS coding in the repair column decoders, portions of re·
`enabled by the same redundant column select line. A
`dundant columns can be allocated to replace portions of
`nonuniform distribution of decoder circuits among the
`array columns containing defective memory cells.
`redundant select lines improves the efficiency of repair
`Thus, with multiple decoders, a single redundant col·
`and leads to space saving economics.
`umn can be utilized to replace multiple defects occur·
`There is also provided a method for eliminating a 20 ring in different array columns.
`defect in a memory device having a logical data block
`formed with an array of addressable memory cells
`formed in rows and columns. A defect associated with
`a first of the columns of cells is eliminated by program(cid:173)
`ming a portion of·a first repair (redundant) column of 2S
`cells or a portion of a second repair column of cells to
`be responsive to the addresses of a portion of the cells in
`the first column. The number of portions of the first
`repair column of cells which can be allocated to effect
`multiple repairs among the array columns differs from JO
`the number of portions of the second repair column of
`cells which can be allocated to effect multiple repairs
`among the array columns.
`In a preferred embodiment of the invention, there is
`provided a redundancy scheme, as well as a method for 3S
`developing a redundancy scheme, resulting in improved
`device repairability for given space constraints. A mem(cid:173)
`ory device is formed with a plurality of data blocks
`having individual input/output paths. Each block com(cid:173)
`prises an array of memory cells arranged in addressable 4-0
`rows and columns along row lines and column lines.
`The array is configured in sub-blocks each comprising a
`plurality of the memory cells. A second group of mem(cid:173)
`ory cells is arranged along the row and column lines of
`a data block array to provide at least first and second 4S
`repair columns for the array columns. The device in·
`cludes row address circuitry for selecting a row of the
`memory cells, column address circuitry for selecting a
`column of the memory cells and address repair cir-
`cuitry.
`The address repair circuitry includes a plurality of
`DETAILED DESCRIPTION OF THE
`column repair decoder circuits each connected to a
`INVENTION
`repair column and each programmable with column
`The block diagram of FIG. 1 illustrates a semi-con(cid:173)
`and row address information corresponding to a section
`of an array column containing a defective memory cell. SS ductor memory device with which the invention may
`With this programming, memory cells in a segment of a
`be practiced. This exemplary device 10 is a DRAM of
`repair column can replace memory cells in a segment of
`the so-called 16 Megabit size, having 224 or 16,777,216
`an array column containing a defective memory cell.
`one-transistor storage cells arranged in rows and col-
`The number of decoder circuits allocated to different
`umns. According to a preferred architecture, the device
`repair columns is nonuniform.
`60 is partitioned into four identical logical data blocks 12,
`According to one example of the preferred cmbodi-
`individually designated lla, llb, llc and lld. Each
`ment a memory device is formed with a plurality of
`block 12 is of the four megabit size, comprising
`logical data blocks each having individual input/output
`4, 194,304 memory cells arranged in an array of 4,096
`paths. One of the blocks comprises an array of memory
`rows and 1,024 columns C. The row address strobe
`cells arranged in rows and columns and configured in 65 signal RAS, the column address strobe signal CAS, the
`write enable signal W, and the output enable signal G
`sub-blocks. Each sub-block includes a plurality ofmem·
`ory cells arranged in rows and subcolumns. The block
`control operations within DRAM 10. These signals are
`also contains row address circuitry for selecting a row
`received by the timing and control circuits of the mem-
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention may be best understood by reference
`to the following detailed description of a preferred
`embodiment when read in conjunction with the accom(cid:173)
`panying drawings, wherein:
`FIG. 1 is a plan view of a memory device which may
`incorporate the invention;
`FIG. 2 illustrates the general layout of a logical data
`block in the device of FIG. 1;
`FIG. 3 is a partial view of a sub-block of one of the
`data blocks;
`FIG. 4 schematically illustrates a fusible comparator
`decoder according to the invention;
`FIG. 5 illustrates, in block diagram form, a column
`repair scheme according to the invention;
`FIGS. 6A through 6E portray an analysis and meth(cid:173)
`odology for improving the achievable level of column
`repair for a logical data block; and
`FIGS. 7A through 7F illustrate statistical trends re(cid:173)
`lating to device repairability according to the invention.
`FIG. 8 illustrates a second column repair scheme
`according to the invention;
`FIGS. 9A-9F illustrate improvements in probability
`of defect repair based on nonuniform distributions of
`decoder circuits; and
`.
`FIGS. lOA-lOC illustrate improvements in the prob(cid:173)
`ability of defect repair based on nonuniform distribu(cid:173)
`tions of decoder circuits and as a function of the level of
`row decoding incorporated in the decoder circuitry.
`
`MICRON-1005.019
`
`19
`
`

`
`5,270,975
`
`6
`5
`within two adjacent pairs of sub-columns SC and the
`ory device. The read or write mode of the device is
`1/0 buffers 21.
`selected through the write enable signal W. A logic
`For this exemplary DRAM embodiment, the row
`high on W selects the read mode while a logic low on W
`decoding arrangement enables simultaneous transfer of
`selects the write mode. The impedance of the output
`buffers is controlled by the output enable signal G. S data to or from one sub-block 14 in each of the four data
`When G is high, the buffers will remain in the high-
`blocks 12 at a given time. The column select arrange-
`impedance state. Bringing G low during a normal cycle
`ment provides X 4 output from each data block 12.
`Thus, the 1/0 buffers 21 could provide 16 bit parallel
`will activate the output buffers putting them in the
`1/0.
`low-impedance state.
`Circuit details of the device 10 which are helpful to 10 During a data transfer operation, row address signals
`understanding the invention are illustrated in FIGS. 2, 3
`RAO through RAU and column address signals CAO
`and 4. As indicated in FIG. 2, each data block 12 is
`through CA11 are input in conventional time-multi-
`partitioned into sixteen sub-blocks 14. The portion of a
`plexed manner. They are latched into row and column
`column C within each sub-block 14 is formed as a pair
`address buffers 22 and 24 according to timing signals
`ofinterdigitated subcolumns SC. See FIG. 3. Thus 1024 15 RAS and CAS. See FIG. 1. Based on 4 bits of row
`pairs of subcolumns are in each sub-block. Banks of
`address information RAO through RA3, the first row
`sense amplifiers SA border upper and lower opposing
`decoder stage 16 selects one of the 16 sub-blocks in each
`of the data blocks 12. The seco~d :ow decoder stage 18
`sides of each sub-block.
`selects one of the 256 ro~s. within .each selected sub-
`The partial view of FIG. 3 illustrates two adjacent
`pairs of interdigitated subcolumns SC. The first pair 20 ?lock b~ed on the remammg 8 bits of row !1'1d:ess
`mforma~ion ~4 thr~ugh RAU. The decoder circuitry
`comprises subcolumns SC1 and SC2 and the second pair
`20 receives eight ~its of ~olu':11n ~ddress data, AO
`comprises subcolumns SC3 and SC4. Each of the pairs
`through A7, to ~rovide ":logic-high signal alon~ one ~f
`of subcolumns is associated with one of two ad'acent
`the 256 select Imes Y s m a data block 12. With this
`.
`.
`.
`.
`J
`.
`columns m t~e sub-block. As is common m high de~sity 25 selection, the data block provides four bits of data on a
`th c
`· t d
`DRAM devices, the subcolumns are arranged m a
`·
`'th th
`d
`f 2 b't
`fl
`·
`· l'
`Th
`SC
`pair o
`• 1 pa s
`110 assoc1a e w1
`e accesse
`h b 1
`ti l
`o ded .bit me coi: 1~urat1on.
`us, eac s~co ~mn
`sub-block. The next two bits of column address data,
`comp:i~es two b1tlme segments BL and BL with each
`CA8 and CA9, can be applied in any of several well
`contammg .memory cells and connected to :he. same
`known decoder circuit arrangements to vary the output
`sense amplifier SA. The t~o sub7olumns w1thm the 30 of the data block from X 1 to x 4.
`sub-block 14, that a~e associated with t~e same column
`The memory array of each data block 12 includes, in
`C, ~re c?upled to different sense amphfiers SA on op-
`addition to the 4,194,304 cells arranged along 1024 col-
`umns c, a predetermined number of redundant columns
`posmg sides of the sub-b~ock ~4. Except for the ou~er-
`most b~nks of sense amplifiers i~ the data block 12, (i.e.,
`RC. Data I/O of the memory cells in each column RC
`those s1~uated along the outer sides of the first an~ last 35 is controlled by a redundant column select line. One
`~f the sixteen sub-blocks), e:ich bank. of sense ~mphfiers
`redundant column select line y RS is illustrated in FIG.
`is shared by sub-columns m an adJacent pair of sub-
`2. In principle, the number of redundant columns RC
`bloc~s. .
`provided in each data block can be sufficient to maxi-
`. Within each sub-block 14, t~ere are 256 r~w o~ ~ord mize the yield• of a production lot. On the other hand,
`~tnes R ~nd 256 column sel~ct Imes Y s. For s1mphc1ty of 4-0 given typical space constraints, it is desirable that indi-
`~lustrat1on, only on~ row lme R and 01'.e c~lumn select
`victual data blocks in the device 10 comprise less than
`hne Y