ISSUECLASSIFICATION
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`PATENT NUMBER ‘
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`53934-fui 1
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`CONTENTS
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`INITIALS
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`Date Mailed
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`INI11ALS
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`FEE DETERMINATION
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`INDEX OF CLAIMS
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`ORFGINEL CLASSIFICATION
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`PATENT APPLICATION SERIAL NO.
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`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
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`PTO-1556
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`SERIAL NUMBER
`
`09/050,354
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`FILING DATE
`
`03/31/93
`
`SHIGEYUKI NAKAZAWR, TOKYO,
`
`JAPAN.
`
`(249706
`APPLICANT
`
`CLASS
`
`'
`
`GROUP ART UNIT
`
`' ATTORNEY DOCKET NO.
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`365
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`2815
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`**FOREIGN APPLIC1-LTIONS************
`VERIFIED
`JAPAN
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`B1203/1997
`
`03/31/97
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`___\3_‘L
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`'
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`STATE on
`same
`TOTAL
`INDEPENDENT
`~_-.
`:1 Priority claimed
`Forei
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`DRAWING -
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`SUG-I-IRUE MION ZINN MACPEAK S: SEAS
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`ADDRESS
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`SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT
`
`age-.‘-:,:%:
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`$790
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`N°‘
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`Other
`Credit
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`

`
`LAW on-1:55
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`M31131 31: 1993‘
`'
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`Re:
`
`Dear Sir:
`
`Shigcyuki NAKAZAWA
`Application of
`"SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT"
`Our Ref: Q-‘-‘£9706
`
`Attached hereto is the application identified above including the specification and claims, 8 sheets of formal
`drawings, an infon-nation Disclosure Statement with Form PTO—l449 and references, an executed Assignment and
`PTO4595 form, and an executed Declaration and Power of Attorney.
`
`The Government filing fee is calculated as follows:
`
`20
`3
`
`Q. —
`_2*, -
`
`Total claims
`Independent claims
`.
`Base Fee
`Multiple Dependent Claim Fee $270.00
`TOTAL FILING FEE
`Recorclation of Assignment
`TOTAL FEES
`
`x $22 =
`= ___
`= M x $82 =
`,
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`_'
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`-
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`'
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`_
`
`S 790.00
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`3 790.00
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`3 830.00
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`Deposit Account No. 19-4830. A duplicate copy of this transmittal letter is attaciied.
`
`Priority is claimcdfrorn .iapanesePatent _A.pplicationNo. 081203197 filed March 31, 1997. A certified copy
`I
`of the priority document is enclosed herewith.
`):r
`
`Res-pectfnlly subrnitted,
`
`SUGHZRUE, MION, ZJNN,
`MACPEAK & SEAS, PLLC
`Attorneys for Applicant
`
`By:
`
`I E . Frank Osha
`Reg. No. 24,625
`
`

`
`mwomens
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`]APAN OFHCE,
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`MlNATO—Kl.[. TOKYO [D5, IAPAN
`TELEPHONE {O5} 3503—37fiD
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`~
`
`,
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`
`Re:
`
`Dear Sir:
`
`Shigeyulci NAKAZAWA
`Application of
`"SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT"
`Our Ref: Q49706
`
`Attached hereto is the applicationidentified above including the specification and claims, 8 sheets of formal
`drawings, an Information Disclosure Statement with Form PTO-1449 and references, an executed Assignment and
`PTO—]S95 form, and an executed Declaration and Power of Attorney.
`
`The Government filing fee is calculated as follows:
`
`20
`3
`
`Q -
`_g_ -
`
`Totai claims
`Independent claims
`Base Fee
`Multiple Dependent Claim Fee $270.00
`TOTAL FILING FEE
`'
`Recordation of Assignment
`TOTAL FEES
`
`= __ x $22 =
`= _ x $32 =
`
`.
`
`'
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`'
`
`$ 790.00
`
`'5 790.00
`$ 40.00
`S 830.00
`
`Checks for the statutory filing fee of $790.00 and Assignment recotdatinn fee of $40.00 are attached. You
`are also directed and antboiizedto charge or credit any ditference or overpayrnenrto Deposit Account No. 19-4880.
`The Commissioner is hereby authorized to charge any fees under 3'? C.F.R. §§ 1.16 and 1.17 and any petitions for
`extension of time under 37 C.F.R. § 1.136 which may be required during the entire pendency of the application to
`Deposit Account No. 19-4880. A duplicate copy of this transmittal letter is attached.
`
`Priority is claimed from Sapanese Patent Application No. 081203197’ filed March 31, 1997. A certified copy
`of the priority document is enclosed herewith.
`
`Respectfnlly submitted,
`
`SUGI-IRUE, MION, ZINN,
`_ MACPEAK & SEAS, PLLC
`Attorneys for Applicant
`
`By:
`
`.Fmnk Osha
`Reg. No. 24,625
`
`

`
`
`
`ssimconnocron MEMORY DEVICE
`
`WITH REDUNDANCY CIRCUIT
`
`Eield of the Invention
`The present invention relates to a semiconductor memory device equipped .
`
`with a redundancy circuit, and more particularly, to a semiconductor memory device
`
`having an enhanced relief efficiency of a defective bit line by means of a redundant
`bit line.
`
`Backggund of the In ventign
`
`Accompanying fine geometry, high integration, and large capacity of the
`semiconductor memory devices in recent years, it is becoming extremely difficult
`to obtain perfect products which are absolutely free from defects. In other words,
`almost all of the produced semiconductor memory devices include defective
`
`memory‘ cells, defective work lines, or defective bit lines.
`
`In order to make it
`
`possible to deliver semiconductor memory devices that include such defects as
`acceptable products, it is a general practice to provide the semiconductor memory
`device with a redundancy circuit.
`I
`I
`The redundancy circuit is for disablingthe use of a defective word or bit line
`when there exists one, and replacing the defective word or bit line with a redundant
`word or bit line. By designing a circuit configuration such that a defective word
`line or a defective bit line can be replaced by a redundant word line or a redundant
`bit line, as in the above, it is possible to deliver a semiconductor memory device as
`if it is absolutely free from defectiveness. Accordingly,‘ -a redundancy circuit
`contributes significantly to the enhancement of the yield of the semiconductor
`
`memory devices.
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`10
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`In order to relieve as many defective word lines or defective word lines or
`
`defective bit lines as possibie, it is most elfective to incorporate as many redundant
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`word lines or redundant bit lines as its practicable. However, since the redundancy
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`circuit is a superfluous circuit in the sense that it is uselessunless thereexists
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`defectivenessi in the manufactured semiconductor memory device,
`it
`is not
`recommended to provide a large scale redundancy circuit within the semiconductor
`
`memory device. For this reason, it is desirable to relieve as many defective word
`lines or defective bit lines as possible with a minimum number of redundant word
`
`lines or redundant bit lines.
`
`Under those circumstances, a variety of methods for improving the relief
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`efficiency of defective word iines or defective bit lines by means of a redundant
`
`circuit have been proposed. As examples, there may be mentioned methods
`
`disclosed in USP 5,349,556, USP 5,355,339, USP 5,359,560, and USP 5,414,660.
`
`The method described in these patents is what is called the row flexible redundancy
`
`method. The row flexible redundancy method is a technique for efficiently
`
`relieving the word line defects, which has a feature in that the range of replacement
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`covered by one redundant word line is broad.
`However, according to the row, flexible. redundancy method, the reiief
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`efficiency for defective bit lines remains unchanged, although the relief efficiency
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`for defective word lines can be improved. Because ofthis, a method which can also
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`improve the relief efficiency for defective bit lines is in demand.
`
`Snmrnagr of the Invention
`
`it is an object of the present invention to provide a semiconductor memory
`
`device equipped with a redundancy circuit having a high relief efficiency.
`
`It is another object of this invention to provide a semiconductor memory _
`.__2_
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`11
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`device by which defective bit lines can be relieved by a smaller number of
`
`redundant bit lines.
`It is still another object ofthis invention to provide a semiconductor memory
`
`device which is capable of relieving a larger number of defective bit lines ‘while
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`minimizing the increase in the chip area
`
`It is still another object of this invention to provide a semiconductor memory
`
`device equipped with a redundant circuit which is capable of improving the relief
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`efficiency for defective bit lines while employing a row flexible redundancy circuit.
`The semiconductor memory device according to this invention comprises a
`
`plurality of column selection iines, at least one redundant column selection line, a
`
`column decoder which activates one iine out ofthe plurality of column selection
`
`lines in response to a column address, a first circuit which generates a detection
`signal when the column address of a defect-pre_lated column selection line is
`supplied, and a second circuit which receives at least a part of a row address, and
`
`activates the redundant column selection line in response to at least a part of the row
`
`address and the detection signal. With this arrangement, when defect occurs in one '
`
`bit line, instead of replacing all of the many bit lines included in the column
`selection iine to which the defective bit line belongs, it is possibie to relieve a larger
`
`number of defective bit lines using a single redundant column selection line by
`
`
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`replacing only a part of these bit lines.
`
`
`
`ti nBrief De cri the Drawin
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`
`
`2-"
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`t/
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`The above and other objects, advantages and features ofthe present invention
`
`wiil be apparent from the following description taken in conjunction with the
`
`accompanying drawings, in which:
`
`Fig. 1 is a block diagram showing a semiconductor memory device 100 with _
`_..3_
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`12
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`

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`
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`divided bit lines, which is an object of this invention;
`Fig. 2 is a block diagram sh_owing a semiconductor memory device 200
`
`according to a first embodiment of this invention;
`Fig. 3 is a circuit diagram showing a part of a column redundancy decoder
`
`216 in Fig. 2;
`
`_
`
`Fig. 4 shows a fuse blocks 302 and 304 shown in Fig. 3;
`
`Fig. 5 isia timing chart showing the timings for bit line replacement by the‘
`semiconductor memory device 200;
`M
`Fig. 6 is a block diagram showing a semiconductor memory device 600
`
`according _to a second embodiment of this invention;
`
`Fig. 7 is a block diagram showing a ‘semiconductor memory device 700
`
`' according to a third embodiment of this invention;
`
`Fig. 8 is a circuit diagram of a control circuit 750 in Fig. 7;
`Fig. A9 is a circuit diagram showing a part of a column redundancy decoder
`
`716 iniFig. 7; and
`
`Fig. 10 is a timing chart showing the timings for bit line replacement
`
`according to the semiconductor memory device 700.
`
`Detailed [Description of the preferred Embodiments
`
`First, referring to Fig. 1, the semiconductor memory device 100 which is the
`
`object of application ofthis invention will be described prior to detailed description
`
`of the semiconductor memory device of this invention.
`
`A semiconductor memory device 100 shown in Fig. 1 is a semiconductor
`memory device with divided bit lines. The cell array region of the semiconductor
`
`memory device 100 consists of a normal cell array region 102 and a redundant cell
`
`array region 104.
`
`

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`
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`An X address (row address) is supplied to a row decoder 106 and a row
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`redundancy decoder 112, and a Y address (column address} is supplied to a column
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`decoder 108 and a column redundancy decoder 116. Upon receipt of the X address
`
`the row decoder 106 activates one word line corresponding to the X address out of
`
`a plurality of word lines. In Fig. 1, only word lines 118 and 120 are indicated for
`
`convenience. On the other hand, upon receipt of a Y address, the column decoder
`
`108 activates one column selection line corresponding to the Y address out of a
`
`plurality of column selection lines. In Fig. I, only the column selection line 122 is
`
`indicated for convenience.
`
`Many memory .cells MC are connected to each of the Word lines 118 and .120,
`
`and respective [memory cells MC are connected to sense amplifiers 124, 126, and
`
`the like.
`
`M
`
`Here, it is to be noted that the column selection line 122 activates the plurality
`of sense amplifiers 124, 126, and the like. That is, in the same column, a bit line is
`divided into plural parts, and the column decoder 108 selects all the sense amplifiers
`connected to the plurality of divided bit lines,
`in response to the Y address.
`
`Although only two bit lines are indicated in Fig.
`
`l for convenience,
`
`it will be
`
`assumed that the number of divided bit lines is actually 16. In other words, when
`
`the column selection line 122 is activated
`
`response to a Y address, 16 sense
`
`amplifiers are selected simultaneously. However, only the data corresponding to an
`activated word line is selected finally out of the 16 selected sense amplifiers, and
`is readout.’
`
`The row redundancy decoder 112 detects the supply of the X address
`
`corresponding to a defective word line. The row redundancy decoder 112 includes
`
`a plurality of fuse elements, and stores the X address corresponding to a defective
`
`14
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`

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`
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`word line according to whether or not these fuses are blown out. Nameiy, when the
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`X address corresponding to a defective word line issupplied, the row redundancy
`
`decoder 112 supplies an inhibit signal 132 to the row decoder 106 to deactivate the
`
`row decoder 106, and activates a redundant word line driver 110 to activate a
`
`specified redundant word line 128. In this way, the defective word line isreplacecl
`
`by the redundant word line 128.
`
`'
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`On the other hand, the column redundancy decoder 116 detects the supply of
`
`the Y address corresponding to a defective bit line. The column redundancy
`decoder 116 also includes a plurality of fuse elements, and stores the Y address
`
`corresponding to a defective bit line according to whether or not these fuses are
`
`
`
`blown out. In other words, when the Y addressocorresponding to the defective bit
`line is supplied, the decoder 116 deactivates the column decoder 108 by supplying I
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`an inhibit signal 134 tothe column decoder 108, and activates the redundant column
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`selection driver 114 in order to activate a specified redundant column selection line
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`130.
`
`In this way, the defective bit line is replaced by a redundant bit line (not
`
`shown) corresponding to the redundant column selection line 130.
`
`However, such a semiconductor memory device 100 has the following
`
`problem. Namely, if one bit line is defective, not only the defective bit line but also T
`
`other bit lines that share the column selection line are replaced to the redundant bit
`
`__
`
`lines. More specifically, as aresult of defect in a bit line, for example, the bit line
`
`corresponding to the sense amplifier 124, all ofthe 16 bit lines selected by the same
`' column selection line l22‘are disabled, and all of the 16 bit lines are replaced to the -
`
`redundant bit lines. Thus, many redundant bit lin_es wiil be wasted for a small
`
`number of bit line defects. In effect, it leads to the problem of deterioration of the
`
`relief efficiency of the defective bit lines.
`
`15
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`

`
`
`
`
`
`In the semiconductor memory devices according to each of the embodiments
`
`that wiil be described in the following, the above problem is resolved to realize a
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`high relief efficiency.
`Thepsemiconductor memory device according to a first embodiment of this
`invention 200 has a feature in that a column redundancy decoder 216 receives not
`
`only a Y addressbut also a part of an X address, as shown in Fig. 2. The remaining
`portions are basically the same as that ofthe semiconductor memory device 100
`shown in Fig. l. g
`I
`I
`Namely, the semiconductor memory device 200 shown in Fig. 2 is a
`semiconductor memory device with dividedbit lines, and the cell array region
`consists of a normal cell array region 202 and a redundant cell array region 204.
`In addition to an X address being supplied to a row decoder 206 and a row
`redundancy decoder 212, XAO and
`which show the logical level ofthe most
`
`significant bit ofthe X address are supplied also to the column redundancy decoder
`
`216. As mentioned above, XAO and XA1 are signals showing the logical level of
`the most significant bit ofthe X address, in which XAO is "1" and XAI is "0" when
`
`the most significant bit of the X address is 0, and on the contrary, XAO is "0" and
`XA1 is "1" when the most significant bit ofthe X address is 1. In short, XAO and
`XA1 are mutually complementary signals.
`1
`
`On the other hand, a Y address is supplied to a column decoder 208 and the
`
`column redundancy decoder 216.
`2 Upon receipt ofthe X address, the row decoder 206 activates one word line
`
`corresponding to the X address out of a pluraiity ofword lines. In Fig. 2, only word
`-line 218 and word line 220 are indicated for convenience. On the other hand, upon
`receipt of the Y address, the column decoder 208 activates one column selection
`
`16
`
`

`
`
`
`line corresponding to the Y address out of a plurality of column selection lines. In
`
`Fig. 2, column selection lines 222 and 290 alone are indicated for convenience.
`
`Each of the word lines 218, 220, and the likeis connected to a memory cell
`
`MC, and each memory cell MC is connected to a corresponding one of sense
`amplifiers 224, 226, and the like.
`'
`ln the semiconductor memory device 200 shown in Fig. 2, the column
`
`selection line 222 activates, as before,_a plurality of sense amplifiers 224, 226, and
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`the like. That is, analogous to the semiconductor memory device 100, a bit line is
`
`divided into plural pans in the same column, and the column decoder 208 selects
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`"all the sense amplifiers connected to a plurality of divided bit lines in response to
`
`the Y address. Although only two bit lines are indicated in Fig. 2 for convenience,
`it will be assumed that a bit line is actually divided into 16 parts as before. ‘Namely,
`
`when the column selection line 222, 290, or the like is activated in response to a Y
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`address, 16 sense amplifiers are selected simultaneously. Data corresponding only
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`to the activated word line is selected finally out of the 16 sense amplifiers, and is
`
`read out.
`
`The row redundancy decoder 212 detects the supply of the X address
`
`corresponding to a defective word line. The row redundancy decoder 212 contains
`
`a plurality of fuse elements, and stores the X address corresponding to defective
`
`word lines depending upon whether or not these fuses are blown out. Typically,
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`polysilicon is used for these fuses, but the present invention is not limited to this
`
`choice, and permits the use of any kind of material for the fuses.
`
`In addition,
`
`although laser irradiation is employed typically as the method of fuse bow~ouL this
`
`invention is not limited to this case, and permits the use of any type of blow—out
`
`method. For example, the fuse may be blown out by the passing of a large current
`
`
`
`17'
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`

`
`
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`in the fuse.
`
`
`
`When an X address corresponding to a defective word line is received, the
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`rowredundancy decoder 212 deactivates the row decoder 206 by supplying an
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`inhibit signal 232 to the row decoder 206, and activates a redundant word line
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`driver 210_in order to activate a specified redundant word line 228. As a result, the
`defective word line is replaged to the redundant word line 228. Accordingly, it will
`look as if thereexists no defect when seen from the outside.
`
`In the meantime, the column redundancy decoder 216 detects that a Y address
`
`corresponding to a defective bit line is supplied. Referring to Fig. 3, a specific
`circuit diagram and the operation of the column redundancy decoder 216 will be
`described.
`I
`
`Fig. 3 shows a specific circuit configuration of the column redundancy
`
`decoder 216, but it does not show the all circuit parts that are included in the
`
`column redundancy decoder 216. Namely, the column redundancy decoder 216‘
`
`shown in Fig. 3 illustrates only the circuit part corresponding to one redundant
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`column selection line YRED ofthe column redundancy decoder 216. Accordingly,
`in the decoder 216, there actuaily exist as many column redundancy decoders 216‘
`
`as equals to the number of the redundant column selection iines YRED. For
`
`example, if there exist 8 redundant column selection lines YRED, 8 column
`redundancy decoders 216' are needed, and if there exist 16 redundant column
`
`selection lines YRED, then 16 column redundancy decoders 216' are needed.
`
`As shown in Fig. 3, two fuse blocks 302 and 304 are included in the column
`
`redundancy decoder 216', and the Y address is supplied in common to these fuse
`blocks 302 and 304. A specific circuit configuration ofthese fiise blocks 302 and
`
`304 is as shown in Fig. 4. As shown in Fig. 4, in the fuse blocks 302 and 304 are
`
`18
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`

`
`
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`included a plurality of fuses 402, and the Y address of a defective bit line is stored
`by programming the Y address ofthe defective bit line in these fuses 402. Namely,
`
`when the Y address of a defective bit line is supplied to the fuse blocks 302 and 304
`
`where the Y address of the defective bit line is programmed, a wiring 404 goes to
`
`the ground potential, and matching signals 306 and 308 go to a high level (active
`
`level). In contrast, when an address different from the Y address of the defective
`
`bit line is supplied to the fuse blocks 302 and 304, the wiring 404 is held at a
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`potential Vcc, and the matching signals 306 and 308 are held at a low Eevel (inactive
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`level).
`
`A
`_
`That the material and the blow~out'method to be employed by the fuse.402
`
`are not limited is similar to the case of the row redundancy decoder 212.
`As shown in Fig. 3, the column redundancy decoder 216’ further includes two
`
`transfer gates 310 and 312. The transfer gate 310 outputs the matching signal 306
`
`as the YRED when XAO is at the high level, and the transfer gate 312 outputs the
`— matching signal 308 as the YRED when XA1 is at the high level. As mentioned
`
`above, XAO and XA1 are complementary signals showing the logical level of the
`
`most significant bit of the X address, so that either one of the transfer gates 310 or
`
`312 is necessarily in the energized stateand the other is in the ldeenergized state.
`Although it is not explicitly indicated in Fig. 3, when a YRBD goes to the
`
`high level (active level), the inhibit signal 234 goes to the active level, and inhibits
`
`the operation of the column decoder 208.
`
`Next, the replacement operation of a defective bit l.ine is the semiconductor
`
`memory device 200 will be described.
`
`As an example, the case in which a bit line corresponding to the sense
`
`amplifier 224 is defective will be described. In this case, the bit line corresponding
`
`_-10 _
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`19
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`

`
`
`
`to the column seiection iine 22?. is defective, so the Y address corresponding to the
`
`column selection line 222 is programrnedin the column redundancy decoder 216.
`
`What is important at this time is to program this Y address in the fuse block 302
`
`within the column redundancy decoder 216.
`
`After programming in this manner, when the memory cell MC corresponding
`
`to the defective bit line is accessed, the fuse block 302 brings the matching signal
`
`306 to the high level by detecting the matching of the Y signals. Further, since the
`
`defective bit line belongs to the cell array region where the most significant bit of
`the X address is O, XAO is "1", and the transfer gate 310 goes to the energized state.
`
`Accordingly, the YRED goes to the active level, and corresponding to this, the
`
`redundant column selection line drive 214 activates the specifics redundant column
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`selection line 230. On the other hand, the operation of the column decoder 208 is
`
`inhibited by the inhibit signal 234.
`- As a result, the defective bit line is replafied to 21 redundant bit line belonging
`to the redundant column selection line.
`
`On the other hand, when a memory cell connected to a bit line belonging to
`a cell array region where the most significant bit of the X address is "1", among the
`
`other bit lines corresponding to the column selection line 222, is accessed, the
`
`repiacement of the bit line is not carried out. The reason for this is that, although
`
`the fuse block 302 activates the matching signal 306 as a result of matching of the
`
`Y addresses, the transfer gate 310 is deenergized in this case, and the YRED is not
`activated. As a result of the nonactivation of the YRED, the inhibit signal 234 is
`
`‘carries out the normally operation.
`not activated either, and the column decoder
`In this connection, it should be noted that the above fact means that only half
`
`of the bit lines, namely, only those bit lines belonging to the cell array region where
`
`._11fi
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`20
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`

`
`
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`21
`
`the most significant bit of the X address is "1", out of the bit lines Corresponding to
`
`the column selection line 222, are replased to the redundant bit tines.
`
`I
`
`Here, the case in which another bit line, for example, a bit line belonging to
`
`the cell array region where the most significant bit of the X address is "1" among the
`
`bit lines belonging to the column selection line 290, is defective, will be described.
`
`In this case, since a bit line corresponding to the column selection line 290 is
`
`defective,
`
`the Y address corresponding to the column seiection line 290 is
`
`programmed in the column redundancy decoder 216. What is important at this time
`
`is to program the Y address in the fuse biock 304 in the column redundancy decoder
`2 1 6.
`
`After programming as in the above, when the memory cell corresponding to
`
`the defective bit line is accessed, the fuse block 304 brings the matching signal 308
`
`to the high level by detecting the matching of the Y addresses. Since the defective
`
`bit line belongs to the cell array region where the most significant bit of the X
`
`address is "1" as mentioned above, XAI is "1" so that the transfer gate 312 is
`
`energized. As a result, the YRED is activated, and in response to this, the redundant
`
`column selection line driver 214 activates the specified redundant column selection
`
`iirie 230. On the other hand, the operation of‘thelcolumn decoder 208 is inhibited
`by the inhibit signal 234.
`'
`
`In contrast to the above, when a -memory _ cell connected to a bit line
`
`belonging to the cell array region Where the most significant bit of the X address is
`
`0, among the other bit tines corresponding to the column selection line 290, is
`
`accessed, the replacement of the bit line does not take place. The reason for this is
`
`that, although the fuse block 304 activates the matching signai 308 because of the
`
`matching of the Y addresses, the transfer gate 312 is deenergized in this case, so
`
`_12_
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`
`
`

`
`
`
`that the YRED is not activated. Because of thenonactivation of the YRED, the
`
`inhibit signal 234 is not activated either, and the column decoder'208 carries out the
`
`normal operation.
`Attention is to be drawn again to the fact that this means that only half‘of bit.
`
`lines, namely, bit lines belonging to the cell array regionwhere the most significant
`
`bit of the X address is "l", among the bit lines corresponding to the column
`
`selection line 290, can be replased to the redundant bit lines.
`
`The above operation will be understood more clearly by examining the timing
`
`chart shown in Fig. 5. From Fig. 5 it can be seen that the matching signal 306 is
`
`generated only during the time when XAO is active, whereas the matching signal
`308 is generated only during the time when XAI is active.
`I
`In other "words, half of the single redundant column selection line 230
`
`replaces half of the column selection line 222, and the remaining half of the same _
`
`redundant column selection line 230 replaces half of the column selection line 290.
`
`In this manner, by replacing only half, rather than all, of the column selection lines
`
`that include a" defective bit line, in response to the X address to which the defective
`
`bit line belongs, two bit line defects with mutually different column selection lines
`
`can be replased to means of a single redundant column selection line.
`
`Consequently, the relief efficiency of the defective bit lines can be doubled.
`More specifically, when the redundant column selection lines equal in
`
`number to the redundant column selection lines contained in the semiconductor
`
`memory device 100 are installed in the semiconductor memory device 200, it is
`
`possible to relieve twice as many defective bit lines as the semiconductor memory
`
`device 100 can. Accordingly, the relief efficiency can be enhanced accompanied
`
`by little increase in the chip area. Further, even‘ when half as many redundant
`
`22
`
`

`
`
`
`23
`
`column selection lines as contained in the semiconductor memory device 100 are
`
`installed in the semiconductor memory device 200, it is possible to reiieve the same
`
`number of defective bit lines as is done by the semiconductor memory device 100.
`
`Accordingly, it is possibie to reduce the chip area without deteriorating the re