UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01561
`U.S. Patent No. 6,233,181
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`Submitted Electronically via the Patent Review Processing System
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
`
`
`
`
`I. 
`
`TABLE OF CONTENTS
`MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1) .......................... 1 
`A. 
`Real Party-In-Interest under 37 C.F.R. § 42.8(b)(1) ............................. 1 
`B. 
`Related Matters under 37 C.F.R. § 42.8(b)(2) ...................................... 1 
`C. 
`Counsel and Service Information .......................................................... 3 
`PAYMENT OF FEES — 37 C.F.R. § 42.103 ................................................... 3 
`II. 
`III.  REQUIREMENTS FOR IPR UNDER 37 C.F.R. §§ 42.104 ............................ 3 
`A.  Grounds for Standing Under 37 C.F.R. § 42.104(a) ............................. 3 
`B. 
`Identification of Challenge Under 37 C.F.R. § 42.104(b) .................... 3 
`C. 
`Level of Ordinary Skill in the Art ......................................................... 5 
`D. 
`Claim Construction under 37 C.F.R. §§ 42.104(b)(3) .......................... 6 
`IV.  TECHNOLOGY BACKGROUND ................................................................... 7 
`State of the Art as of 1997: DRAM and Shared Sense
`A. 
`Amplifiers .............................................................................................. 7 
`State of the Art as of 1997: Using Spare Memory Cells to
`Replace Defective Cells ...................................................................... 13 
`V.  DESCRIPTION OF THE PRIOR ART ........................................................... 18 
`A.  Disclosure of Sukegawa ...................................................................... 18 
`B.  Disclosure of Fujishima ...................................................................... 21 
`C.  Disclosure of Walck ............................................................................ 26 
`VI.  SUMMARY OF THE ’181 PATENT ............................................................. 28 
`VII.  THE CHALLENGED CLAIMS ...................................................................... 33 
`VIII.  PRIOR PROSECUTION .................................................................................. 35 
`A.  Original Prosecution ............................................................................ 35 
`Inter Partes Review............................................................................. 37 
`B. 
`IX.  HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE ................ 39 
`A.  Ground 1: Claim 3 is Obvious under § 103(a) over
`Sukegawa in view of Fujishima .......................................................... 39 
`
`B. 
`
`i
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
`
`
`
`
`1. 
`
`2. 
`
`Sukegawa and Fujishima disclose and render
`obvious every limitation of dependent claim 3 ......................... 39 
`A person of ordinary skill in the art would have
`been motivated to combine the teachings of
`Sukegawa and Fujishima, thereby rendering claim
`3 obvious ................................................................................... 59 
`B.  Ground 2: Claim 5 is Obvious under § 103(a) over
`Sukegawa in view of Fujishima and Walck ........................................ 64 
`Sukegawa, Fujishima, and Walck disclose and
`1. 
`render obvious every limitation of dependent claim
`5 ................................................................................................. 64 
`A person of ordinary skill in the art would have
`been motivated to combine the teachings of
`Sukegawa, Fujishima, and Walck, thereby
`rendering claim 5 obvious ......................................................... 70 
`CONCLUSION ................................................................................................. 72 
`
`
`
`ii
`
`2. 
`
`X. 
`
`
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181
`
`
`
`
`Exhibit #
`
`TABLE OF EXHIBITS
`
`Exhibit Description
`
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`
`
`Declaration of Dr. Pinaki Mazumder
`
`Curriculum Vitae of Dr. Pinaki Mazumder
`
`U.S. Patent No. 6,233,181
`
`File History for U.S. Patent No. 6,233,181
`
`U.S. Patent No. 5,487,040 to Sukegawa
`
`U.S. Patent No. 5,267,214 to Fujishima
`
`U.S. Patent No. 4,967,397 to Walck
`
`U.S. Patent No. 5,956,285 to Watanabe
`
`Masashi Horiguchi et al., A Flexible Redundancy Technique for High-
`Density DRAM’s, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.
`26, NO. 1, Jan. 1991, at 12-17
`
`Kazutami Arimoto et al., A 60-ns 3.3-V-Only 16 Mbit DRAM with
`Multipurpose Register, IEEE JOURNAL OF SOLID-STATE CIRCUITS,
`VOL. 24, NO. 5, Oct. 1989, at 1184-90
`
`U.S. Patent No. 5,687,123 to Hidaka
`
`U.S. Patent No. 5,726,946 to Yamagata
`
`U.S. Patent No. 6,003,148 to Yamauchi
`
`U.S. Patent No. 6,075,743 to Barth
`
`Inter Partes Review No. IPR2016-00096, Decision Granting
`Institution filed April 21, 2016
`
`Inter Partes Review No. IPR2016-00096, Judgment Granting
`Request for Adverse Judgment filed August 3, 2016
`
`iii
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Apple, Inc. (“Apple”) hereby petitions under 35 U.S.C. §§ 311-319 and 37
`
`C.F.R., Part 42 for Inter Partes Review (“IPR”) of claims 3 and 5 (“the Challenged
`
`Claims”) of U.S. Patent No. 6,233,181 (the “’181 patent”) (Ex. 1003), filed on
`
`February 17, 1999. The ’181 patent issued on May 15, 2001, to Hideto Hidaka,
`
`and is assigned to Limestone Memory Systems LLC (“LMS” or “Patent Owner”),
`
`according to USPTO assignment records. There is a reasonable likelihood that
`
`Petitioner will prevail with respect to at least one Challenged Claim.
`
`I. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1)
`A. Real Party-In-Interest under 37 C.F.R. § 42.8(b)(1)
`Petitioner Apple is the real party-in-interest. No other party exercised or
`
`could have exercised control over this petition; no other parties funded or directed
`
`this petition. (See Office Patent Practice Trial Guide, 77 Fed. Reg. 48750-60.)
`
`B. Related Matters under 37 C.F.R. § 42.8(b)(2)
`The ’181 patent and U.S. Patent Nos. 5,805,804, 5,894,441, and 6,697,296
`
`(collectively, “the asserted patents”) are being asserted by Limestone against Apple
`
`in the pending litigation (currently stayed), Limestone Memory Sys. LLC v. Apple
`
`Inc., 8:15-cv-01274, filed on August 10, 2015, in the U.S. District Court for the
`
`Central District of California (“C.D. Cal”). In addition to the foregoing litigation,
`
`LMS has also asserted one or more of the asserted patents in the following actions:
`
`Limestone Memory Sys. LLC v. Micron Tech. Inc., 8:15-cv-00278; Limestone
`
`1
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`Memory Sys. LLC v. OCZ Storage Solutions, Inc., 8:15-cv-00658 (C.D. Cal.);
`
`Limestone Memory Sys. LLC v. PNY Techs., Inc., 8:15-cv-00656 (C.D. Cal.);
`
`Limestone Memory Sys. LLC v. Lenovo (US) Inc., 8:15-cv-00650 (C.D. Cal.);
`
`Limestone Memory Sys. LLC v. Kingston Tech. Co. Inc., 8:15-cv-00654 (C.D.
`
`Cal.); Limestone Memory Sys. LLC v. Transcend Info., Inc. (California), 8:15-cv-
`
`00657 (C.D. Cal.); Limestone Memory Sys. LLC v. Acer America Corp., 8:15-cv-
`
`00653 (C.D. Cal.); Limestone Memory Sys. LLC v. Dell Inc., 8:15-cv-00648 (C.D.
`
`Cal.); and Limestone Memory Sys. LLC v. Hewlett-Packard Co., 8:15-cv-00652
`
`(C.D. Cal.).
`
`The following administrative matters may affect, or be affected by, a
`
`decision in this IPR: IPR2016-01567 (filed by Apple simultaneously with this
`
`petition).
`
`Also, the ’181 patent was the subject of IPR2016-00096, recently terminated
`
`after LMS disclaimed claims 1, 2, 4, 6, and 7 of the ’181 patent, which may affect
`
`a decision in this IPR.
`
`
`
`
`
`2
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`C. Counsel and Service Information
`
`Lead Counsel
`
`Back-Up Counsel
`
`John R. Hutchins (Reg. No. 43,686)
`jhutchins@kenyon.com
`Kenyon & Kenyon LLP
`1500 K Street NW
`Washington, DC 20005
`T: 202.220.4200
`F: 202.220.4201
`
`Rose Cordero Prey
`(rcordero@kenyon.com)
`Kenyon & Kenyon LLP
`One Broadway
`New York, NY 10004
`T: 212.425.7200; F: 212.425.5288
`
`Michael Zachary
`(mzachary@kenyon.com)
`1801 Page Mill Road, Suite 210
`Palo Alto, CA 94304
`T: 650.384.4700; F: 650.384.4701
`
`
`
`Petitioner consents to email service. Back-Up Counsel will seek
`
`authorization to submit motions to appear pro hac vice before the Board on behalf
`
`of Petitioner.
`
`II.
`
`PAYMENT OF FEES — 37 C.F.R. § 42.103
`
`The U.S. Patent and Trademark Office is authorized to charge the filing fee,
`
`and any other required fees, to Deposit Account 11-0600 (Kenyon & Kenyon
`
`LLP).
`
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. §§ 42.104
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a)
`Petitioner certifies that the ’181 patent is available for IPR and that
`
`Petitioner is not barred or estopped from requesting IPR.
`
`B.
`
`Identification of Challenge Under 37 C.F.R. § 42.104(b)
`
`3
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Petitioner requests cancellation of the Challenged Claims (i.e., claims 3 and
`
`5), based on the following references and the Declaration of Dr. Pinaki Mazumder
`
`(“Mazumder Declaration” or “Mazumder Decl.”) (Ex. 1001):
`
`1) U.S. Patent No. 5,487,040 (“Sukegawa”) (Ex. 1005), filed July 12,
`
`1993, and claiming priority to Japanese Patent Application No. 4-
`
`207332, filed July 10, 1992, issued on January 23, 1996 and qualifies
`
`as prior art under pre-AIA 35 U.S.C. § 102(b); and
`
`2) U.S. Patent No. 5,267,214 (“Fujishima”) (Ex. 1006), filed November
`
`20, 1990, and claiming priority to Japanese Patent Application No. 2-
`
`36666, filed February 16, 1990, issued on November 30, 1993 and
`
`qualifies as prior art under pre-AIA 35 U.S.C. § 102(b).
`
`3) U.S. Patent No. 4,967,397 (“Walck”) (Ex. 1007), filed on May 15,
`
`1989, issued on October 30, 1990 and qualifies as prior art under pre-
`
`AIA 35 U.S.C. § 102(b).
`
`The specific statutory grounds of unpatentability are as follows:
`
`4
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`Ground ’181 Patent Claims
`
`Basis for Challenge
`
`1
`
`2
`
`3
`
`5
`
`Obvious under §103(a) over Sukegawa and
`
`Fujishima
`
`Obvious under §103(a) over Sukegawa,
`
`Fujishima, and Walck
`
`The grounds of unpatentability are explained below and supported by the
`
`Mazumder Declaration and the other exhibits. The Mazumder Declaration
`
`explains how a person of ordinary skill in the art would have understood the scope
`
`and content of the prior art as well as the motivation to combine the prior art
`
`teachings.
`
`C. Level of Ordinary Skill in the Art
`As set forth in the Mazumder Declaration (Ex. 1001), a person of ordinary
`
`skill in the art with respect to the technology described in the ’181 patent [1998]
`
`would be a person with a Bachelor of Science and Master’s degree in electrical
`
`engineering or computer engineering (or an equivalent subject) and three to four
`
`years of post-graduate experience working with dynamic random access memory
`
`systems, or a PhD in electrical engineering or computer engineering (or an
`
`equivalent subject) and at least 1-2 years of post-graduate experience working with
`
`such dynamic random access memory systems, or an equivalent amount of work
`
`5
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`experience.1 Ex. 1001, ¶¶ 28-30.
`
`D. Claim Construction under 37 C.F.R. §§ 42.104(b)(3)
`A claim subject to IPR is given its “broadest reasonable construction in light
`
`of the specification.” 37 C.F.R. § 42.100(b). Its terms are to be given their plain
`
`meaning unless inconsistent with the specification. See In re Zletz, 893 F.2d 319,
`
`321 (Fed. Cir. 1989). Petitioner submits, for this IPR, that the ’181 patent terms
`
`may be construed to have their plain and ordinary meaning in view of the
`
`specification.2
`
`
`1
`As set forth in the Mazumder declaration, Dr. Mazumder’s patentability
`
`analysis regarding claims 3 and 5 of the ’181 patent would not change even if a
`
`lower level of skill were applied, such as if the person of ordinary skill had a
`
`Bachelor of Science in electrical engineering (or an equivalent subject) and two to
`
`three few years of pertinent work experience. Ex. 1001, at p. 17, n.4.
`
`2
`
`Petitioner notes that various constructions of claim terms in claim 3 of the
`
`’181 patent were proposed by the Petitioner MTI during the previous IPR of the
`
`’181 patent, i.e., IPR2016-00096. Ex. 1015, at pp. 4-5. While Petitioner does not
`
`disagree with those claim constructions, the Board in that IPR determined that the
`
`IPR could be resolved by applying the ordinary meaning of the terms in claim 3,
`
`without adopting any particular claim constructions. Id. Similarly, here, no claim
`
`6
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`IV. TECHNOLOGY BACKGROUND
`A.
`State of the Art as of 1997: DRAM and Shared Sense Amplifiers
`The ’181 patent is generally directed to the field of semiconductor memory
`
`devices, in particular dynamic random access memories (“DRAM”). Ex. 1003,
`
`1:6-27, 5:65-6:1, and 27:40-46. DRAM devices are comprised of memory cells
`
`laid out in rectangular arrays of rows and columns. Ex. 1001, ¶ 33. A chain of
`
`memory cells, called words, are arranged in each row and are addressable by a
`
`word line. Id. at ¶¶ 33-34. Columns of memory cells spanning multiple rows are
`
`addressable by a column select line. Id. at ¶¶ 34-35. The contents of each
`
`memory cell are propagated via bit lines to a plurality of sense amplifiers, each cell
`
`typically connected to two bit lines running in the column direction denoting
`
`polarity. Id. at Fig. 4, ¶¶ 35 and 41. The sense amplifiers are able to read and
`
`restore (i.e., write) the contents of each of the memory cells. Id. at ¶¶ 35, 38, and
`
`40-46. Each memory cell, thus, is located at the intersection of a word line and a
`
`bit line, allowing a central processing unit (such as a microprocessor) to access
`
`data for READ or WRITE operations at any memory location by providing a
`
`unique address which identifies a particular row and column in the memory array.
`
`Id. at ¶¶ 34-35. The memory device includes row and column decoders that
`
`
`constructions beyond the ordinary meaning of the claim terms are required to
`
`resolve this Petition. Ex. 1001, ¶ 27.
`
`7
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`decode different combinations of signals at an address input to the memory circuit.
`
`Id.
`
`For example, Figure 13, from a patent claiming priority to 1996, provides
`
`schematics of the overall architecture of a multi-bank DRAM chip that comprises
`
`N+1 Memory Blocks (MB#0-MB#N), each having a plurality of memory cells
`
`arranged in a matrix of rows and columns, and N+2 Sense Amplifier Bands (SA#0-
`
`SA#N+1), of which SA#0 and SA#N+1 are located at the extreme edge of the
`
`memory blocks, MB#0 and MB#N, while N other Sense Amplifier Bands are
`
`shared by two adjacent memory blocks for READ and WRITE operations. Ex.
`
`1001, ¶ 37; Ex. 1008, 6:64-7:12. There are N+1 Array Driving Circuits (DR#0-
`
`DR#N) that comprises Row Address Decoders for each Memory Block (MB),
`
`while the Column Decoder is common to all memory blocks and a single Column
`
`Select Line runs orthogonally (upward) from Column Decoder through all memory
`
`blocks. Ex. 1001, ¶ 37; Ex. 1008, 7:13-25; and Fig. 1.
`
`
`3
`An exemplary design of a large DRAM chip having shared sense amplifier
`
`bands, from U.S. Patent No. 5,956,285, “Synchronous Semiconductor Memory
`
`Device with Multi-Bank Configuration” (priority date of April 22, 1996) (the
`
`“’285 patent”). Ex. 1008, Fig. 1.
`
`8
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Figure 1
`
`The sense amplifier bands (SA#1-SA#N) are shared by adjacent pairs of
`
`memory blocks. Ex. 1001, ¶ 38; Ex. 1008, 7:6-8. During a READ or WRITE
`
`operation, a selected memory block is connected to its corresponding adjacent
`
`sense amplifier bands, which are isolated from any non-selected memory blocks.
`
`Ex. 1001, ¶ 38; Ex. 1008, 7:8-12.
`
`9
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Figure 2
`
`Figure 24, above, is a more detailed example of how sense amplifiers may be
`
`shared between memory blocks. Ex. 1001, ¶¶ 41-46; Ex. 1008, 9:41-10:18. It
`
`shows the structure of two sense amplifier bands, SA#N and SA#N+1 that are
`
`located between and share adjacent memory blocks MB#N-1and MB#N (in the case
`
`of SA#N) and MB#N and MB#N+1 (in the case of SA#N+1). Ex. 1001, ¶ 41; Ex.
`
`
`4
`Exemplary shared sense amplifier bands between memory blocks from the
`
`’285 patent. Ex. 1008, Fig. 4.
`
`10
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`1008, 9:41-45 and 10:10-13. When signals for odd bit-lines (e.g., BLn1 and
`
`/BLn1) and BLI2n+1 are asserted, memory cells on the selected word-line and the
`
`odd bit-lines are connected (via, e.g., the pass gate BTGn1) to the lower sense
`
`amplifier band (SA#N+1) and the corresponding sense amplifiers store the contents
`
`of the selected odd memory cells. Ex. 1001, ¶ 42; Ex. 1008, 9:47-10:4.
`
`Similarly, memory cells connected to even bit-lines (e.g., BLn2 and /BLn2)
`
`in the memory block MB#N may be connected to the upper sense amplifier band,
`
`SA#N through the pass gates, BTGn2, BTGn4, etc. Ex. 1001, ¶ 43; Ex. 1008, 9:47-
`
`65 and 10:4-9. When signals for even bit-lines (e.g., BLn2 and /BLn2) and BLI2
`
`are asserted, memory cells on the selected word-line and the even bit-lines are
`
`connected to the upper sense amplifier band (SA#N) and the corresponding sense
`
`amplifiers store the contents of the selected even memory cells. Ex. 1001, ¶ 44;
`
`Ex. 1008, 9:47-65 and 10:4-9.
`
`Therefore, a shared sense amplifier band deploys its sense amplifiers to
`
`determine the states of memory cells in one adjacent memory block, say MB#k,
`
`located on its even bit-lines, BL2m and /BL2m, for m = 0, 1, 2, …, as well as to
`
`determine the states of memory cells in the other adjacent memory block, say
`
`MB#k+1, located on its odd bit-lines, BL2m+1 and /BL2m+1, for m = 0, 1, 2, ….
`
`Ex. 1001, ¶ 45. Also, a specific memory block shares the sense amplifier bands
`
`located on its upper and lower periphery areas. (See Figure 2). Id.
`
`11
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`While the images above are from an exemplary patent claiming priority to
`
`1996, comparable shared sense amplifier bands shared between adjacent memory
`
`blocks are shown in the Fujishima prior art (Ex. 1006) (discussed below) as well as
`
`various journal articles, e.g., Horiguchi et al., A Flexible Redundancy Technique
`
`for High-Density DRAM’s, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26,
`
`NO. 1, Jan. 1991, at 12-17 (“Horiguchi”) (Ex. 1009), and Arimoto et al., A 60-ns
`
`3.3-V-Only 16 Mbit DRAM with Multipurpose Register, IEEE JOURNAL OF SOLID-
`
`STATE CIRCUITS, VOL. 24, NO. 5, Oct. 1989, at 1184-90 (Ex. 1010); and patents,
`
`e.g., U.S. Patent No. 5,687,1235 (Ex. 1011), at Fig. 91; 40:15-21; U.S. Patent No.
`
`5,726,9466 (Ex. 1012), at Fig. 31; 44:15-24; U.S. Patent No. 6,003,1487 (Ex. 1013),
`
`at Figs. 2 to 4; 6:53-8:47; and U.S. Patent No. 6,075,7438 (Ex. 1014), at Figs. 1 to
`
`4; 1:48-60, 3:54-4:30, and 5:18-6:21.
`
`5
`Filed on September 30, 1994, with a priority date of October 14, 1993;
`
`assigned to Mitsubishi.
`
`6
`
`Filed on March 19, 1997, with a priority date of June 2, 1994; also assigned
`
`to Mitsubishi.
`
`7
`
`Filed on January 13, 1997, with a priority date of May 30, 1996; also
`
`assigned to Mitsubishi.
`
`8
`
`Filed on May 23, 1997, with a priority date of December 26, 1996; assigned
`
`to Rambus, Inc.
`
`12
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`As further explained below, having shared sense amps between memory
`
`blocks has certain known benefits, including accurate sensing of ever-smaller
`
`memory cells (e.g., Ex. 1006, at 1:27-42 and 2:4-5), reducing parasitic capacitance
`
`of the bit lines associated with memory cells (e.g., Id. at 1:47-50), reducing power
`
`consumption (e.g., Id. at 2:4-9); and increasing production yield. Id. at 13:24-26
`
`These shared amplifier band structures, and their benefits, were well known
`
`prior to 1997. Ex. 1001, ¶¶ 37-46. As such, an ordinarily skilled artisan would
`
`have been aware that sense amplifier bands could be located between and shared
`
`among adjacent memory blocks, would be aware of the design implications and
`
`advantages of such an arrangement, and would have been able to implement such
`
`an arrangement. Id. at ¶¶ 29-30 and 46.
`
`B.
`
`State of the Art as of 1997: Using Spare Memory Cells to Replace
`Defective Cells
`
`Semiconductor memory devices are prone to defects during manufacturing.
`
`Id. at ¶¶ 47 and 50. If one or more memory cells are defective, RAM
`
`manufacturers generally include redundancy circuits that allow disabling the use of
`
`defective cells and replacing them with spare (“redundant”) cells, thereby
`
`increasing the manufacturing yield of the products. Id. at ¶¶ 49 and 51. Memory
`
`circuits provide for redundancy by including on the same circuit several duplicate
`
`rows and/or columns of memory cells, with their associated word lines and bit
`
`13
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`lines, to replace any row or column having defective memory cells. Id. at ¶ 51.
`
`Separate row and/or column decoders are provided for the redundant rows or
`
`columns that are programmable using programming elements such as fusible links.
`
`Id. at ¶¶ 58-59 and 69-70. Once the integrated circuit is tested and the locations of
`
`the defective memory cells are determined, the programmable redundancy
`
`decoders are programmed to decode those addresses that correspond to the rows or
`
`columns with defective cells. Id. at ¶¶ 52, 59, and 70. The defective rows or
`
`columns, and their associated decoders, are subsequently disabled. Id. at ¶¶ 54 and
`
`70-71. This way every time a defective row or column is addressed, a redundant
`
`equivalent is selected instead. Id.
`
`In the last three decades, there has been a trend toward dividing a DRAM
`
`into multiple sub-arrays, and having divided bit lines, to ensure a high signal-to-
`
`noise ratio (S/N) and to minimize bit line charging and discharging currents,
`
`thereby reducing power dissipation. Id. at ¶ 61. To circumvent these problems,
`
`mega-bit DRAM arrays are divided into multiple sub-arrays where each sub-array
`
`has its own sense amplifiers connected to the bit lines. Id.
`
`The increase in both the number of spare lines needed and the number of
`
`sub-arrays led to various approaches (e.g., conventional and flexible) to managing
`
`spare word lines in DRAMs with memory-array division. Id. at ¶ 62.
`
`In a first conventional technique, the number of spare decoders is equal to
`
`14
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`the number of spare word lines (L) in each sub-array, where each spare decoder is
`
`shared by all the M sub-arrays. (See Figure 39 below). Ex. 1001, ¶ 63; Ex. 1009,
`
`p. 2.
`
`Figure 3
`
`In a second conventional technique, every spare line in each sub-array has its
`
`own spare decoder, as shown in Figure 410 (see below). Ex. 1001, ¶ 64; Ex. 1009,
`
`p. 2.
`
`
`9
`Ex. 1009, Fig. 2(a).
`
`10
`
`Id. at Fig. 2(b).
`
`Figure 4
`
`15
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`In both of the above techniques, spare lines and spare decoders are
`
`connected directly. Ex. 1001, ¶ 66; Ex. 1009, p. 2. In one case, the spare-line
`
`usage is inefficient, and in the other case, the spare-decoder utilization is
`
`inefficient. Ex. 1001, ¶ 66; Ex. 1009, p. 2. A Flexible Redundancy Technique
`
`(FRT) overcomes the above issues by connecting the spare decoders indirectly
`
`through OR gates, as shown in Figure 511 (see below). Ex. 1001, ¶ 66; Ex. 1009, p.
`
`2. Each spare decoder compares both intra-sub-array and inter-sub-array address
`
`signals. Ex. 1001, ¶ 66; Ex. 1009, p. 2. Each logical-OR of the outputs of the
`
`spare decoders is applied to all the sub-arrays instead of to one, as in the second
`
`conventional technique. Ex. 1001, ¶ 66; Ex. 1009, p. 2. The FRT thereby causes a
`
`flexible relationship between spare lines and spare decoders, and improves both
`
`spare-line usage efficiency and spare-decoder usage efficiency. Ex. 1001, ¶ 66;
`
`Ex. 1009, pp. 2-3. Hence, there is smaller chip-area penalty due to redundancy.
`
`Ex. 1001, ¶ 66; Ex. 1009, p. 3.
`
`
`11
`Id. at Fig. 3.
`
`16
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Figure 5
`
`As such, in 1997, an ordinarily skilled artisan would have been aware of
`
`various redundancy techniques by which spare memory cells may be arranged in
`
`memory sub-arrays to replace defective word lines, would be aware of the design
`
`implications and advantages of such an arrangement, and would have been able to
`
`implement such an arrangement. Ex. 1001, ¶¶ 29-30, 49, and 60-67.
`
`
`
`
`
`17
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`V. DESCRIPTION OF THE PRIOR ART
`A. Disclosure of Sukegawa
`The Sukegawa patent issued on January 23, 1996 and qualifies as prior art
`
`under pre-AIA 35 U.S.C. § 102(b). Sukegawa is related to the design of
`
`semiconductor memory devices and the repair of defective memory cells. Ex.
`
`1005, 1:13-37. Sukegawa discloses a semiconductor device including a plurality
`
`of memory arrays. Id. at Fig. 1. For example, as depicted in Figure 1 (see below),
`
`Sukegawa discloses eight memory quadrants (“arrays”). Id. at 1:41-42; Ex. 1001,
`
`¶ 72.
`
`18
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Each of the memory arrays includes eight memory blocks aligned in the
`
`column direction. Id. at Fig. 1; 1:42-43. Further, each of the memory blocks is
`
`comprised of memory cells arranged in a matrix configuration. Id. at 4:45-47.
`
`Figures 2 and 3 depict the plane and oblique views, respectively, of each of the
`
`memory cells. As depicted in Figures 2 and 3, the word lines 19 and the bit lines
`
`17 intersect to form the matrix of the memory cells. Id. at 1:55-2:14; Ex. 1001, ¶
`
`73.
`
`Sukegawa also discloses a redundancy mechanism for compensating for
`
`defective memory cells. Id. at Fig. 8; 5:50-6:40; claim 1. In particular, Sukegawa
`
`discloses that at least some of the memory blocks include redundant memory
`
`arrays. Id. at Fig. 8; claims 1and 5; Ex. 1001, ¶ 74.
`
`19
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`For instance, as depicted in Figure 8, the memory array includes eight
`
`memory blocks aligned vertically (e.g., in the column direction). Id. at 5:50-53.
`
`Further, the memory blocks may include four-row redundant memories (“spare
`
`word lines”). Id. at 5:53-54. For example, Figure 8 depicts that memory block 100
`
`includes spare word lines 70, memory block 104 includes spare word lines 74,
`
`memory block 108 includes spare word lines 76, and memory block 112 includes
`
`spare word lines 78. Sukegawa further discloses an “ANY TO ANY” redundancy
`
`mechanism in which spare word lines in one memory block can be used to replace
`
`the defective memory in any other memory block, including memory blocks in the
`
`same or different memory arrays. Id. at 2:21-59, 3:34-43, 4:45-48, and 4:64-5:2;
`
`and Fig. 5; Ex. 1001, ¶ 75.
`
`20
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`
`Further, Sukegawa also discloses a plurality of sense amplifier bands. See
`
`id. at Fig. 1.
`
`Figure 1 discloses a heavy line labeled “S/A” (“sense amplifier”) in memory
`
`quadrant (“array”) 6. Id. Each memory quadrant includes eight such heavy lines
`
`and, thus, includes eight sense amplifier bands. Id.; Ex. 1001, ¶¶ 76-77.
`
`B. Disclosure of Fujishima
`The Fujishima patent issued on November 30, 1993 and qualifies as prior art
`
`under pre-AIA 35 U.S.C. § 102(b). Like Sukegawa, Fujishima is directed to the
`
`design of semiconductor memory devices, “particularly to a semiconductor
`
`memory device having a shared sense amplifier arrangement wherein one sense
`
`amplifier is shared between the columns in two different memory blocks.” Ex.
`
`21
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`1006, 1:10-14. Fujishima explains that memory, such as DRAM, requires sense
`
`amplifiers to sense and amplify the signals or charge stored on particular memory
`
`cells. Id. at 1:18-26. Fujishima also notes that, as memory cells become ever-
`
`more integrated (and thus smaller), it becomes more difficult to accurately sense
`
`the charges stored in the cells. Id. at 1:27-34. Fujishima notes that one
`
`“conventional” way to arrange these sense amplifiers to accurately read data from
`
`the memory cells is to have them located between, and shared by, two different
`
`memory blocks: “One of such conventional countermeasures . . . employs the
`
`shared sense amplifier arrangement wherein a memory cell array is divided into
`
`two blocks and sense amplifiers are disposed and shared between the two blocks.”
`
`Id. at 1:35-42. Further, because the sense amplifiers are shared, “during the
`
`sensing operation, only the columns in one block are connected to the sense
`
`amplifiers and the columns of the other block are subsequently connected to the
`
`sense amplifiers after the sensing operation.” Id. at 1:42-46; Ex. 1001, ¶ 78.12
`
`Fujishima describes various known benefits to such a shared sense amplifier
`
`arrangement, including reducing the parasitic capacitance of a bit line associated
`
`with memory cells (thus increasing the ability to correctly sense the data in the
`
`12
`This basic concept of having sense amplifiers located between and shared by
`
`adjacent memory blocks is similarly admitted to be prior art in the ’181 patent
`
`itself. Ex. 1003, at Fig. 54; 3:18-50.
`
`22
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,233,181 IPR2016-01561
`
`memory cells). Id. at 1:47-56. Fujishima also describes that there are known
`
`benefits to having memory arrays divided into multiple memory blocks, wherein
`
`the sense amplifiers are shared between particular bit line pairs in different
`
`memory blocks, and only sense amplifiers connected to selected memory cells are
`
`selectively activated. Id. at 1:57-2:11. This arrangement has the added benefit of
`
`reducing power consumption. Id. at 2:4-9; Ex. 1001, ¶¶ 79-80.
`
`Fujishima also discloses “an alternate arrangement type shared sense
`
`amplifier scheme” (e.g., at 15:24-29) in which a series of memory blocks are
`
`aligned in the column direction and arranged such that sense amplifier bands are
`
`located adjacent to, and on either side of, each memory block. Id. at 24:26-47.
`
`Fujishima cites to an IEEE article (i.e., Arimoto et al., A 60-ns 3.3-V-Only 16 Mbit
`
`DRAM with Multipurpose Register, IEEE JOURNAL OF SOLID-STATE CIRCUITS,
`
`VOL. 24, NO. 5, Oct. 1989, at 1184-90 (“Arimoto”) (Ex. 1010)) from 1989 as also
`
`disclosing this shared sense amplifier arrangement. Ex. 1006, 24:26-34; Ex. 1001,
`
`¶ 81.13
`
`
`13 Mr. Fujish