|||||| |l|||||| Ill ||||||l|l| lllll lllll ||||| Illll |||||lllll III! IIII I
`
`US005726946A
`
`United States Patent
`
`[191
`
`[11] Patent Number:
`
`5,726,946
`
`Mar. 10, 1998
`[45] Date of Patent:
`Yamagata et al.
`
`
`“Switched-Source-Impedance CMOS Circuit For Low
`Standby Subthreshold Current Giga—Scale LSI‘s”. Masashi
`Horiguchi et al.. 1993 Symposium on VLSI Circuit. Digest
`of Technical Papers. pp. 47-48.
`
`“Stand—By/Active Mode Logic For Sub—1 VlG/4Gb
`DRAMS”. Takashima et a1.. 1993 Symposium on VLSI
`Circuit. Digest of Technical papers. pp. 83-84.
`
`“A Testing Technique For ULSI Memory With On-Chip
`Voltage Down Converter". Masaki Tsukude et a1.. Interna-
`tional Test Conference l992. pp. 615-622.
`
`Primary Examiner—Vu A. Le
`Attorney, Agent, or Firm—Lowe. Price. LeBlanc & Becker
`
`[57]
`
`ABSTRACT
`
`A variable impedance power supply line and a variable
`impedance ground line supplying voltages VCL1 and VSL1.
`respectively. are set to a low impedance state in a stand-by
`cycle and in a row related signal set period. and to a high
`impedance state in a column circuitry valid time period.
`Variable impedance power supply line and variable imped-
`ance ground line supplying voltages VCL2 and VSL2.
`respectively. are set to a high impedance state in the stand-by
`cycle. and low impedance state in the active cycle and in the
`row related signal reset time period. Inverters operate as
`operating power supply voltage of voltages VCL1 and VSL2
`or voltages VCL2 and VSL1. in accordance with a logic
`level of an output signal in the stand-by cycle and in the
`active cycle. Thus a semiconductor memory device is pro-
`vided in which subthreshold current in the stand-by cycle
`and active DC current in the active cycle can be reduced.
`
`22 Claims, 52 Drawing Sheets
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE HAVING HIERARCHICAL POWER
`SOURCE ARRANGEMENT
`
`[75]
`
`Inventors: Tadato Yamagata; Kazutami Arimoto;
`Masaki Tsuknde. all of Hyogo. Japan
`
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha.
`Tokyo. Japan
`
`[21] Appl. No.2 820,545
`
`[22] Filed:
`
`Mar. 19, 1997
`
`Related U.S. Application Data
`
`[63] Continuation of Ser. No. 458.583, Jun. 2, 1995, abandoned.
`
`[30]
`
`Foreign Application Priority Data
`
`
`
`...... ... .. 6-121299
`Japan .. ...
`.. 6—320lO2
`Japan ..
`Japan .................................... 7-023590
`
`Jun. 2, 1994
`Dec. 22, 1994
`Feb. 13, 1995
`
`[JP]
`[JP]
`[JP]
`
`Int. Cl.‘ ..................................................... .. G11C 7/00
`[51]
`
`[52] U.S. Cl. ............
`365/226; 365/227; 365/228
`[58] Field of Search ..................................... 365/226. 227.
`365/228. 229. 189.09. 189.11; 327/530.
`535
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,270,581
`5,347,492
`5,541,885
`
`12/1993 Nakamura ............................... 325/530
`
`9/1994 Hoiiguchi et al.
`.
`365/226
`7/1996 Takashima .............................. 365/227
`
`U1‘HER PUBLICATIONS
`
`“IV High-Speed Digital Circuit Technology With 0.5 UM
`Mnlti—Threshold CMOS”. Mutoh et al. 1993. IEEE pp.
`186-189.
`
`
`
`Apple — Ex. 1012
`Apple Inc., Petitioner
`1
`
`Apple – Ex. 1012
`Apple Inc., Petitioner
`1
`
`

`

`U.S. Patent
`
`Mar. 10, 1993
`
`Sheet 1 of 52
`
`5,726,946
`
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`U.S. Patent
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`Mar. 10, 1998
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 5 of 52
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`5,726,946
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`U.S.
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`Patent
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`Mar. 10, 1993
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`Sheet 12 of 52
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`5,726,946
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 15 of 52
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`5,726,946
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`

`U.S. Patent
`
`Mar. 10, 1998
`
`Sheet 16 of 52
`
`5,726,946
`
`FIG. 17
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`

`U.S. Patent
`
`Mar. 10, 1993
`
`Sheet 17 of 52
`
`5,726,946
`
`FIG. 19
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 13 of 52
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`5,726,946
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`U.S. Patent
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`Mar. 10, 1993
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`Sheet 19 of 52
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`5,726,946
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 20 of 52
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`Sheet 21 of 52
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`Mar. 10, 1998Mar. 10, 1998
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`Mar. 10, 1998
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`Mar. 10, 1998Mar. 10, 1998
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`Mar. 10, 1998
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`Sheet 31 of 52
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`
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`Mar. 10, 1998Mar. 10, 1998
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`U.S. PatentU.S. Patent
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`Mar. 10, 1998Mar. 10, 1998
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`Mar. 10, 1993
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`Sheet 34 of 52
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`5,726,946
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 35 of 52
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`5,726,946
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 36 of 52
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`Mar. 10, 1998
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`Sheet 39 of 52
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 42 of 52
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`Mar. 10, 1998Mar. 10, 1998
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`Mar. 10, 1998
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`Mar. 10, 1998Mar. 10, 1998
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 48 of 52
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`U.S. Patent
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`Mar. 10, 1998
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`Sheet 49 of 52
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`U.S. Patent
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`Mar. 10, 1998
`
`Sheet 50 of 52
`
`5,726,946
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`FIG_ 60
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`PRIOR ART
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`
`
`U.S. PatentU.S. Patent
`
`
`
`Mar. 10,1998Mar. 10,1998
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`
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`Sheet 51 of 52Sheet 51 of 52
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`

`U.S. Patent
`
`Mar. 10, 1998
`
`Sheet 52 of 52
`
`5,726,946
`
`F I G. 53
`
`PRIORART
`
`OPERATING
`CURRENT
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`
`53
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`
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`53
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`

`

`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE HAVING HIERARCHICAL POWER
`SOURCE ARRANGEMENT
`
`This application is a continuation of application Ser. No.
`08/458583 filed Jun. 2. 1995. abandoned.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a semiconductor device.
`and. specifically to a structure for reducing current consump-
`tion in a semiconductor device including a logic gate con-
`sisting of CMOS transistors (complementary insulated gate
`type field effect transistors) without affecting operating
`characteristics thereof. More specifically. the present inven-
`tion relates to a structure for reducing subthreshold current
`of a semiconductor memory device such as a DRAM
`(Dynamic Random Access Memory).
`2. Description of the Background Art
`A CMOS circuit has been well known as a semiconductor
`circuit of which power consumption is extremely small.
`FIG. 60 shows a structure of a general CMOS inverter.
`Referring to FIG. 60.
`the CMOS inverter includes a p
`channel MOS transistor (insulated gate type field effect
`transistor) FT provided between a power supply node 1900
`receiving one operating power supply voltage Vcc and an
`output node 1901 and receiving at its gate an input signal IN;
`and an 11 channel MOS transistor NT provided between the
`other power supply node 1902 receiving the other operating
`power supply voltage Vss (generally. ground potential) and
`output node 1901 and receiving at its gate the input signal
`IN. There is a load capacitance C at output node 1901. When
`input signal IN is at a low level. p channel MOS transistor
`PT turns on. n channel MOS transistor NT turns off. load
`capacitance C is charged through p channel MOS transistor
`PI‘. and an output signal OUT attains to the power supply
`voltage level Vcc. When charging of the load capacitance C
`is completed. source and drain of p channel MOS transistor
`PI‘ come to have the same potential. and thus the transistor
`PT turns off. Therefore. at this time. current does not flow.
`and power consumption is negligible.
`When input signal IN is at a high level. p channel MOS
`transistor PI‘ turns oil“. 11 channel MOS transistor NT turns
`on. and load capacitance C is discharged to the level of the
`other power supply potential Vss through 11 channel MOS
`transistor NT. When the discharge is completed. the source
`and drain of 11 channel MOS transistor NT come to have the
`same potential. and thus the transistor NT turns off.
`Therefore. in this state also. power consumption is negli-
`gible.
`A drain current IL flowing through a MOS transistor can
`be represented by a function of a gate-source voltage of the
`MOS transistor. When the absolute value of the gate-source
`voltage becomes larger than the absolute value of the
`threshold voltage of an MOS transistor. a large drain current
`flows. Even when the absolute value of the gate-source
`voltage becomes not higher than that of absolute value of the
`threshold voltage.
`the drain current
`is not completely
`reduced to O. This drain current flowing under such a voltage
`is referred to as subthreshold current which is exponentially
`proportional to the gate-source voltage.
`FIG. 61 shows subthreshold current characteristic of an 11
`channel MOS transistor. Referring to FIG. 61. the abscissa
`represents gate-source voltage VGS. and the ordinate rep-
`resents logarithmic value of drain current IL. In FIG. 61.
`
`5 ,726.946
`
`2
`
`linear regions of lines I and 11 each represent the subthresh-
`old current. The threshold voltage is defined as the gate-
`source voltage providing a prescribed current in this sub-
`threshold current region. For example. in MOS transistor
`having the gate width (channel width) of 10 pm. the gate-
`source voltage causing a drain current flow of 10 mA is
`defined as the threshold voltage. FIG. 61 represents the
`prescribed current 10 and the threshold voltages VTO and
`VT1.
`As the MOS transistor has been made smaller and smaller.
`the power supply voltage Vcc decreases in accordance with
`the scaling rule. Therefore. the absolute value Vth of the
`threshold voltage of the MOS transistor must be decreased
`similarly in accordance with the scaling rule in order to
`improve performance of the MOS transistor. In the CMOS
`inverter shown in FIG. 60. for example. assume that the
`power supply voltage Vcc is 5 V and the threshold voltage
`Vth of n channel MOS transistor NT is 1 V. When input
`signal IN changes from 0 V to a value larger than 1 V. a large
`drain current flow is generated. starting discharging of load
`capacitance C. On the other hand. when the power supply
`voltage Vcc is lowered to 3 V. for example. while maintain-
`ing the threshold voltage Vth at the same value. the load
`capacitance C can be discharged with large current only
`when the input signal IN exceeds 1 V to turn on the n
`channel MOS transistor NT. More specifically. when the
`power supply voltage Vcc is 5 V. discharge of capacitive
`load starts at 1/5 of the amplitude of the input signal IN.
`Meanwhile. when the power supply voltage Vcc is 3 V.
`discharge of capacitive load C starts at '/it of the amplitude
`of input signal IN. Namely. input/output response charac-
`teristic is degraded. and hence high speed operation cannot
`be ensured. Therefore. the absolute value Vth of the thresh-
`old voltage needs to be scaled similarly down as the power
`supply voltage. However. as shown in FIG. 61. when the
`threshold voltage VT1 is lowered to the threshold voltage
`VTO. the subthreshold current characteristic changes from
`that represented by the line I to that of the line 11.
`Accordingly. the subthreshold current when the gate voltage
`is 0 V (Vss level) rises from IL1 to ILO. increasing current
`consumption. Thus. difficulty is encountered in scaling
`down the absolute value Vth of the threshold voltage in the
`similar manner as the power supply voltage and in realizing
`superior operating characteristics. especially high speed
`operation.
`Structures for suppressing subthreshold current without
`degrading high speed operation characteristic have been
`disclosed in pages 47 and 48. and in pages 83 and 84 of 1993
`Symposium on VLSI Circuit, Digest of Technical Papers, by
`Horiguchi et al. and Takashima et al.. respectively.
`FIG. 62 shows a structure of a power supply line disclosed
`by Horiguchi et al. in the above described article. FIG. 62
`shows. as an example of a CMOS circuit. n cascade con-
`nected CMOS inverters fl to fn. Each of inverters fl to f4
`has the same structure as that shown in FIG. 60.
`
`In a path for supplying one operating power supply
`voltage. a first power supply line 1911 is connected to the
`first power supply node 1910 receiving power supply volt-
`age Vcc. and a second power supply line 1912 is arranged
`parallel to the first power supply line 1911. First power
`supply line 1911 is connected to second power supply line
`1912 by means of a high resistance Ra. Parallel to the
`resistance Ra. a p channel MOS transistor Q1 for selectively
`connecting first power supply line 1911 and second power
`supply line 1912 in response to a control signal
`the is
`provided. Between the first and second power supply lines
`1911 and 1912. a capacitor Ca having a relatively large
`
`5
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`

`5,726,946
`
`3
`
`capacitance for stabilizing the potential of second power
`supply line 1912 is provided.
`A transmission path of the other power supply voltage Vss
`(ground potential:0 V) includes a third power supply line
`1921 connected to a second power supply node 1920 receiv-
`ing the other power supply voltage (hereinafter simply
`referred to as the ground voltage) Vss. and a fourth power
`supply line 1922 arranged parallel to the third power supply
`line 1921. Between the third and fourth power supply lines
`1921 and 1922. a high resistance Rb is provided. and parallel
`to the resistance Rb. there is provided an n channel MOS
`transistor Q2 for selectively connecting the third power
`supply line 1921 and the fourth power supply line 1922 in
`response to a control signal (115. Between the third and fourth
`power supply lines 1921 and 1922. a capacitor Cb having
`large capacitance for stabilizing the potential of the fourth
`power supply line 1922 is provided.
`Inverters fl. f3. .
`.
`. of odd-numbered stages have one
`operating power supply node (power supply node receiving
`a high potential) connected to first power supply line 1911
`and the other power supply node (power supply node
`receiving a low potential) connected to fourth power supply
`line 1922. Inverters f2. .
`.
`. of even-numbered stages have
`one operating power supply node connected to second
`power supply line 1912 and the other power supply node
`connected to third power supply line 1921. The operation
`will be described
`
`In a DRAM. a signal state at a stand-by state can be
`predicted in advance. The state of an output signal is also
`predictable. In the structure shown in FIG. 62. input signal
`IN attains to the low level at the stand-by state and attains
`to the high level in an active cycle. In a stand-by cycle.
`control signal the is set to the high level. control signal tbs is
`set to the low level and MOS transistors Q1 and Q2 are both
`turned off. At this state. power supply lines 1911 and 1912
`are connected through high resistance Ra. while power
`supply lines 1921 and 1922 are connected through high
`resistance Rb. The potential VCL of power supply line 1912
`is
`
`VCL=Vcc—l'a-Ra
`
`while the voltage VSL of power supply line 1922 is
`VSL=Vs.H-Ib~Rb
`
`where Ia and lb represent currents flowing through resis-
`tances Ra and Rb. respectively. It is assumed that input
`signal IN is at the ground potential level Vss. In inverter fl.
`p channel MOS transistor FF is on. charging the output node
`to the power supply potential Vcc level on power supply line
`1911. Meanwhile. source potential (potential of power sup-
`ply node 1920) of n channel MOS transistor NT is the
`intermediate potential VSL. and set at a potential level
`higher than the ground potential Vss. Therefore. the gate-
`source voltage of :1 channel MOS transistor NT becomes
`negative. the subthreshold current corresponds to the sub-
`threshold current IL2 when the gate-source voltage is -VSL.
`and is smaller than the subthreshold current 11.] flowing
`when the potential at power supply node 1902 is at the
`ground potential Vss. as shown in FIG. 61.
`The operating characteristics of the MOS transistor will
`be described in accordance with the line I shown in FIG. 61.
`As for the on/oif state of n channel MOS transistor. the state
`where the gate-source voltage is higher than the threshold
`voltage is referred to as the on state. and the state where the
`gate-source voltage is smaller than the threshold voltage is
`
`4
`referred to as the off state. The relation is reversed in a p
`channel MOS transistor.
`In inverter f2. the input signal/IN (output signal from
`inverter fl) is at the high level of the power supply potential
`Vcc. Therefore. in inverter f2. p channel MOS transistor is
`off and 11 channel MOS transistor is on. The p channel MOS
`transistor has its source connected to power supply line 1912
`receiving the voltage VCL. Therefore. in inverter f2. the gate
`potential of p channel MOS transistor is higher than the
`source potential. and as in the n channel MOS transistor. the
`subthreshold current is also suppressed. This also applies to
`inverters f3 to fn of the succeeding stages. ‘Therefore. in the
`stand-by state. subthreshold current in inverters fl to fn is
`suppressed. and the stand-by current can be reduced.
`When an active cycle starts. control signal the is set to the
`low level and control signal ¢s is set to the high level. MOS
`transistors Q1 and Q2 are both turned on. MOS transistors
`Q1 and Q2 have large channel width W. and are capable of
`supplying suflicient charging/discharging current to invert-
`ers fl to fn. At this state. potentials of power supply lines
`1912 and 1922 are at the levels of the power supply potential
`Vcc and the ground potential Vss. respectively. Therefore. in
`the active cycle. the output signal OUT is set to the estab-
`lished state in accordance with the input signal IN.
`FIG. 63 shows signal waveforms of the circuit shown in
`FIG. 62 and current flowing through the power supply lines.
`Referring to FIG. 63. in the stand-by cycle. MOS transistors
`Q1 and Q2 are both off in response to signals tbs and «DC. and
`the voltage VCL on power supply line 1912 and the voltage
`VSL of power supply line 1922 are at intermediate potentials
`between power supply voltage Vcc and ground potential Vcc
`(0 V). respectively. At this stage. MOS transistors in the
`subthreshold region (MOS transistors which are off) of
`inverters fl to f4 are set more strongly off. thus reducing
`subthreshold current.
`However. in the active cycle. control signals cps and the are
`set to the high level and low level. respectively. MOS
`transistors Q1 and Q2 are turned on. the voltage VCL on
`power supply line 1912 becomes equal to the power supply
`potential Vcc and voltage VSL on power supply line 1922
`becomes equal to the ground potential Vss. At the start of an
`active cycle. the power supply current Icc (VCL charging
`current) flows for charging power supply line 1912 and
`when input signal IN changes subsequently. inverters fl to
`fn operate in response. charging/discharging current is gen-
`erated for changing the respective signal levels. and thus a
`relatively large operating current flows.
`In the active cycle. the voltage VCL is set to be equal to
`power supply potential Vcc. while the power supply voltage
`VSL is set equal to the ground potential Vss. Therefore. in
`inverters fl to f4. the gate potential and the source potential
`of a transistor which is off are equal to each other. Therefore.
`when an MOS transistor having small absolute value Vth of
`the threshold voltage is used. considerably large subthresh-
`old current flows. Namely. in the active cycle. before and
`after the change of the input signal IN. a large subthreshold
`current (active DC current) flows. causing a problem of a
`large current consumption in the active cycle. Especially in
`a semiconductor memory device having large storage capac-
`ity such as a 1 giga bit DRAM. when the number of MOS
`transistors which are the components of the device is
`increased. total sum of the active DC current is too large to
`be negligible.
`In transistors Q1 and Q2 (see FIG. 62) which are turned
`off in the standby cycle. subthreshold current flows in the
`stand-by cycle. When the absolute values of the threshold
`voltages of transistors Q1 and Q2 are increased so as to
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`reduce the subthreshold current flowing through transistors
`Q1 and Q2 in the stand-by cycle. the time necessary for
`recovering the potentials of power supply lines 1912 and
`1922 at the transition into the active cycle becomes longer
`from the reason which will be described in the following.
`causing the problem that the access time of the sernicon-
`ductor memory device becomes longer.
`More specifically. at the transition from the stand-by cycle
`to the active cycle. it takes long period of time for the
`transistors Q1 and Q2 to operate in the saturated region as
`the absolute value of the threshold voltage of the transistors
`Q1 and Q2 is high. Thus. the transistors operate in the
`nonsaturated region for a long period of time. Therefore. as
`compared with an example in which the threshold value of
`the MOS transistor is small. current drivability of transistors
`Q1 and Q2 at the transition from the stand-by cycle to the
`active cycle becomes smaller. retarding recovery of poten-
`tials on power supply lines 1921 and 1922. It is necessary
`that internal circuitry is activated after the potentials on
`power supply lines 1921 and 1922 becomes stable. This
`means that the start of operation of the internal circuitry is
`delayed. and in the case of a semiconductor memory device.
`the access time becomes longer.
`
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide an
`integrated semiconductor device which operates at high
`speed with low current consumption.
`Another object of the present invention is to provide a
`semiconductor device in which current consumption in an
`active cycle can be reduced.
`A further object of the present invention is to provide a
`semiconductor memory device which operates at high speed
`with low current consumption.
`Briefly stated. in the semiconductor device in accordance
`with the present invention. impedance of a subpower supply
`line to which current is supplied from the main power supply
`line is minimized only when the current on the subpower
`supply line is consumed. in accordance with the operation
`mode of the semiconductor device. When any component
`does not consume the current on the subpower supply line.
`voltage level of the subpower line is maintained at a pre-
`scribed value.
`
`Since the impedance of the subpower supply line is
`changed as needed. unnecessary consumption of current can
`be prevented. Further. when the configuration for maintain-
`ing the voltage level of the subpower supply line at a
`prescribed venue is utilized. transition from a high imped-
`ance state to a low impedance state of the subpower line can
`be performed at higher speed.
`The foregoing and other objects. features. aspects and
`advantages of the present
`invention will become more
`apparent from the following detailed description of the
`present
`invention when taken in conjunction with the
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 schematically shows a whole structure of a semi-
`conductor memory device in accordance with one embodi-
`ment of the present invention.
`FIG. 2 is a diagram of waveforms showing a memory cell
`selecting operation of the semiconductor memory device
`shown in FIG. 1.
`
`FIG. 3 is a block diagram schematically showing struc-
`tures of a buffer and a control circuit of the semiconductor
`memory device shown in FIG. 1.
`
`FIG. 4 shows a memory array and an input/output circuit
`shown in FIG. 1.
`
`FIG. 5 is a diagram of waveforms showing the operation
`of the circuits shown in FIGS. 3 and 4.
`
`FIG. 6 shows a structure of a power supply circuit in
`accordance with the first embodiment of the present inven-
`tion.
`
`FIG. 7 is a diagram of signal waveforms showing the
`operation of the power supply circuit shown in FIG. 6.
`FIGS. 8A and 8B are illustrations facilitating understand-
`ing of the operation of the power supply circuit shown in
`FIG. 6.
`
`FIGS. 9A and 9B are illustrations facilitating understand-
`ing of the operation of the power supply circuit shown in
`FIG. 6.
`
`FIG. 10 shows a structure of a power supply circuit for a
`column related circuit in acc