1184
`
`A 60-11s 3.3-V-Only 16-Mbit DRAM with
`Multipurpose Register
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 24, NO 5, OCTOBER 1989
`
`KAZUTAMI ARIMOTO, MEMBER, IEEE, KAZUYASU FUJISHIMA, YOSHIO MATSUDA,
`MASAKI TSUKUDE, TUKASA OISHI, WATARU WAKAMIYA, SHIN-ICHI SATOH,
`MICHIHIRO YAMADA, AND TAKA0 NAKANO, SENIOR MEMBER, IEEE
`
`Abstract -A single 3.3-V 16-Mbit DRAM with a 135-md chip size has
`been fabricated using a 0.5-pm twin-well process with doublemetal wiring.
`The array architecture, based on the twisted-bit-line (TBL) array, includes
`suitable dummy and spare word-line configurations which suppress the
`inter-bit-line noise and bring yield improvement. The multipurpose register
`(MPR) designed for the hierarchical data bus structure provides a line-mode
`test (LMT), copy write, and cache access capability. The LMT with
`on-chip test circuits using the MPR and a comparator creates a random
`test pattern and reduces the test time to l/lOOO. A field shield isolation
`and a T-shaped stacked capacitor allow the layout of a 4.8-pd cell size
`with a storage capacitance of 35 fF. These techniques enable the 3.3-V
`16-Mbit DRAM to achieve a 60-ns RAS access time and 300-mW power
`dissipation at 120-11s cycle time.
`
`I.
`
`INTRODUCTION
`
`P design considerations for scaling down ULSI’s. There
`
`OWER SUPPLY voltage is one of the most important
`
`are two possible arrangements. One is an external power
`supply voltage of 3.3 V, and the other is that of 5.0 V with
`an on-chip voltage converter. Although almost all 16-Mbit
`dynamic RAM’S [1]-[3] use the second arrangement, the
`first arrangement [4] has the advantage of lower power
`dissipation in operation and standby than the 5-V scheme
`with the on-chip limiter. At the 16-Mbit level, even if the
`internal voltage limiter is provided to maintain reliability
`[5], the power dissipation cannot be reduced adequately.
`Therefore, the 3.3-V power supply is the best choice in
`meeting an acceptable power dissipation. Also, the 3.3 V
`enables ideal scaling down to a 0.5-pm level transistor,
`which brings improved performance while maintaining re-
`liability [6], [7].
`This paper describes a single 3.3-V 16-Mbit DRAM
`which follows the ideal scaling rule. An improved array
`architecture is required to overcome the small signal and
`the large coupling noise in a scaled-down DRAM cell
`array. To solve this problem, an array architecture based
`on the twisted-bit-line (TBL) [SI, [9] technique, and includ-
`ing suitable dummy and spare arrangements, is proposed
`in Section 11. Although a 16-Mbit DRAM has very fast
`
`Manuscript received Apnl 7, 1989; revised June 5, 1989
`The authors are with the LSI Research and Development Laboratory,
`Mitsubish Electric Corporakon, 4-1 Ivhzuhara, Itami 664, Japan
`IEEE Log Number 8929847
`
`access, testability must be considered from a cost basis.
`The multipurpose register (MPR) [lo] provides high per-
`formance and many other useful functions. The main use
`of the MPR is in a line-mode test (LMT), wbch is an
`important new feature for high-density ULSI DRAMs
`[ll] and will be explained in Section 111. In Section IV, the
`memory cell structure and a scaled-down isolation tech-
`nique are discussed. Finally, the performance and other
`features of the RAM are summarized.
`
`11. ARRAY ARCHITECTURE
`
`A Twisted-Bit-Line Technique
`
`A reasonable c h p size containing 16-Mbit memory cells
`drives the memory cell to a 4-5 pm2 size, and the gate
`length and the isolation wdth to 0.6 pm. The key features
`for an array architecture using scaled-down memory cells
`are: 1) an array noise reduction technique, and 2) a multi-
`divided bit-line structure whch produces sufficient signal
`voltage and allows a wide operating margin at a 3.3-V
`power supply. Although the folded bit-line structure offers
`some array noise reduction, the inter-bit-line couplmg noise
`[9], [12], which is a serious problem in 16-Mbit DRAMs,
`cannot be cancelled with the folded bit-line structure
`By measurement and simulation, the inter-bit-line cou-
`pling capacitance amounts to 21 percent of the total bit-line
`capacitance, even with a thin tungsten bit line. The signal
`loss in the worst-case data pattern is more than 30 percent
`of the total signal amplitude in the folded bit-line struc-
`ture [9].
`In order to suppress the inter-bit-lme coupling noise, a
`TBL array structure is used. Each scaled-down bit line has
`128 cells and realizes a small C,/C, ratio of six. The signal
`loss is reduced by 16 percent of the total signal amplitude
`Fig. 1 shows part of a 2-Mbit block along with the sense
`amplifiers associated wth the sub 1/0 bus lines. Ths
`2-Mbit block is divided into eight subarrays by the place-
`ment of mne alternate shared (ALS) sense amplifier bands.
`The RAM operates with a partial activation technique.
`Only one subarray and a single double-sided ALS sense
`amplifier of that subarray are activated in a 2-Mbit block.
`
`001S-9200/89/1000-1184$01,00 01989 IEEE
`
`Apple – Ex. 1010
`Apple Inc., Petitioner
`1
`
`

`
`ARIMOTO et U[.: 16-MBIT DRAM WITH MULTIPURPOSE REGISTER
`
`1185
`
`SUB ARRAYS 1 SUB ARRAY# 2
`_h_
`
`MAIN
`SUB ARRAY# 8 TR MATCH I/o PAIR'S
`
`rr
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`
`Ir $1
`P
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`3
`0
`
`MULTI PURPOSE REGISTER
`SHARED SENSE AMP.
`Fig. 1. Part of 2-Mbit block with sense amplifiers associated with sub I/O lines.
`
`SPARE WL's D,UMMY WL's
`
`DUMMY WL'S SPARE WL's
`
`ROW DECODER-.
`
`,
`
`Fig. 2. Physical cell arrangement with dummy and spare elements in a basic subarray.
`
`TABLE I
`COMBINATION OF WORD LINE AND DUMMY WORD LINE IN TBL
`
`Word-Line
`
`Dummy Word-Line
`
`A Block 0 , 2
`
`A Block 1 , 3
`C Block 1 , 3
`B Block 0 , 2
`D Block 0 , 2
`B Block I , 3
`D Block I , 3
`
`D2
`
`D3
`
`M
`
`I
`
`NED
`
`ROW DEC.
`4 WAY
`
`ROW DEC.
`
`-
`1 !-WORD DRIVER
`Di
`
`00
`Di -=-
`
`Di
`
`Only one of the four bit-line pairs is connected to the sub
`1 / 0 pair. The array charging current is reduced by 1/8.
`This ALS sense amplifier gives two benefits with little area
`increase: 1) faster sensing by halving the load capacitance
`of the sense drive-line, and 2) relaxed layout pitch.
`The hierarchical data bus consists of sub and main 1/0
`lines, and second-aluminum sub 1/0 bus lines, which are
`arranged so as to connect every four bit-line pairs. The
`load capacitance value of the sub 1/0 line is estimated to
`be less than 0.6 pF. In addition to the reduction and
`distribution of the load capacitance, an intermediate buffer
`called the multipurpose register (MPR) is inserted between
`the sub and main I/O lines to realize high-speed array
`operation.
`
`RA0
`Fig. 3. Block diagram of spare row scheme.
`
`Fig. 2 shows the physical arrangement of cells with
`dummy and spare word lines in a basic subarray. In this
`case, the situation fits the dummy reversal technique [13].
`The TBL array causes the chip area increase and the
`complex dummy decoding scheme. To solve these prob-
`lems, the dummy cells are located at the bit-line twisting
`intersection and the partly twisted word-line interconnec-
`
`2
`
`

`
`1186
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 24, NO 5, OCTOBER 1989
`
`I-
`
`1
`
`tion techniques are introduced. Four sets of dummy cells
`located at the bit-line twisting intersection
`larity of cell arrangement except for the ce
`subarray. Only the center twist wastes area in the basic
`subarray. Therefore, the chip size increase caused by the
`additional dummy and twisting areas is only 0.1 percent.
`The partly twisted word-line interconnection simplifies
`the dummy word-line decoding. The word-line decoding
`scheme adopts the four-way configuration which consists
`of a row decoder and four word drivers. One of four
`word-line drivers is selected by the lower two bits row
`addresses RA, and RA,. A four-way dummy decoding as
`well as the row decoding scheme can be realized by the
`partly twisted word-hne scheme (C block and D block).
`Table I shows the combination of the word line and
`dummy word line in TBL. It means that the dummy word
`line in A block and C block ( B block and D block) is
`decoded by the same decoding sqheme. For example,
`whether in A block or C block, when the even word line is
`activated the dummy word line D, is selected. If the partly
`twisted word-line layout is not adopted, the dummy word-
`line decoding would be eight-way decoding.
`To obtain a reasonable production yield of 16-Mbit
`DRAMS with very small physical dimensions and a large
`chip size, a flexible spare row scheme is introduced. In
`adopting additional two-way spare word-line driving clocks
`decoded by only row A, (RA,) address input, one set of
`four spare word lines is divided into two sets of two spare
`word lines and each pair of spare word lines can replace
`any pair of neighboring word lines in a basic subarray as
`shown in Fig. 3. A consistent dummy word-line selection
`signal is generated in collaboration with word-line replace-
`ment. Therefore, a comparatively large defect, such as two
`to four word-lines' short circuit, can be
`nothing of 1-bit failure and word-line sn
`
`B. Multipurpose Register (MPR)
`
`Fig. 4 shows an MPR and a comparator circuit. The
`comparator is provided to perform the LMT. It is an
`addressable
`EXCLUSIVE-OR circuit simlar to a CO
`memory (CAM) cell, and is comprised of a coincidence
`detector with a wired-OR match line. The MPR consisting
`of a full CMOS latch is inserted between the main and sub
`1/0 pairs and is located at both sides of the column
`
`2 5
`
`3.3v
`
`NODE B
`
`jiL Wkf E A
`
`10
`
`30
`20
`TIM E(ns)
`Fig 5 Simulated waveforms of readout operation
`
`50
`
`40
`
`decoder as explaned previously. The functions of the
`MPR are: 1) intermediate amplifier in a normal cycle;
`2) hgh-speed data register in fast page and static column
`mode; 3) cache register independent of DRAM array
`operation; 4) buffer register in copy write mode; and 5)
`expected test data latch utilized for parallel comparison in
`LMT.
`The MPR operation as an intermediate amplifier in a
`normal cycle is explained by using the simulated wave-
`forms shown in Fig. 5. At first, the bit-line isolate signal
`switches the bit lines connected to the ALS sense ampli-
`fier. When the word line rises, the information stored in
`the memory cells is read out on the bit-line pairs. Then, the
`activated ALS sense amplifiers, which are placed at both
`edges of the selected subarray, detect and amplify the
`bit-line voltage level. After sensing the cell data, the read-
`out data are transferred from the ALS sense amplifier to
`the sub and main 1/0 bus lines by SACz (sense amplifier
`connecting signal generated from column addresses) and
`Y, (column decoder
`output), sequentially. The driving
`clocks CRE and CRE activate the MPR. The activation of
`the MPR accelerates the amplification of the main 1/0
`bus lines because the drivability of the MPR is hgher than
`that of the sense amplifier. Moreover, the driving of the
`MPR starts automatically
`via the ALS sense amplifier
`__
`before CRE and CRE axe activated. Therefore, the over-
`head caused by the MPR control __ sequence is negligible. At
`the same time as CRE and CRE, the MPR is isolated from
`
`~
`
`3
`
`

`
`ARIMOTO et al. 16-MBIT DRAM WITH MULTIPURPOSE REGISTER
`
`1187
`
`WL WL
`
`Match
`
`WL WL
`
`Match
`
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`Q
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`c
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`W
`
`I
`
`r
`
`l
`
`.
`
`
`
`-
`
`1
`
`
`
`Memory Cell
`Fig. 7. Principle of parallel compare called line read.
`
`WRITE
`
`K = l
`
`1/4 ROW=1024 b
`
`1/4ROW LINE READ
`(PARALLEL COMPARE)
`
`
`
`1
`
`-
`
`Fig. 8. Flowchart of LMT.
`
`FLAG) is sent via the match line to output DQ. Thus any
`fails on a line can be detected in one READ cycle.
`Fig. 8 indicates a flowchart of the LMT in the case of
`16-Mbit DRAM. First, random test data are set in the
`MPR. Then, they are simultaneously written in a fourth of
`the cells (1024 bits) on a selected word line in one cycle
`(COPY write). 1/4 row means that the number of MPR’s is
`one fourth the bit-line pairs, as shown in Fig. 1. Writing of
`the random test data in all cells is accomplished in 16K
`cycles. After that, testing of all memory cells (line read
`operation) is completed in 16K READ cycles and 16K
`WRITE cycles, Contrary to the prior-art LMT with only
`limited test patterns (all 0 or 1 patterns only), this test
`using the MPR allows the flexible test pattern. It can test
`with better characterization patterns such as row stripe,
`column stripe, and checker patterns. These LMT patterns
`can reduce the conventional chip test time to about 1/1000.
`An efficient layout of the MPR and the comparator, which
`is made possible by using a hierarchical data-bus structure,
`makes a chip overhead of no more than 0.5 percent.
`
`Memo& Cell Comparator
`MPR
`Fig. 6. Principle of copy write in LMT.
`
`the sub 1/0 bus lines by TR, and the sub 1/0 lines are
`isolated from the ALS sense amplifier by SACi, sequen-
`tially. ’Ths isolation sequence improves the data transfer
`speed because of the reduced load capacitance of the data
`bus, and also contributes to the reduction of the charging
`current of sub 1/0 lines.
`
`111. LINE-MODE TEST (LMT)
`
`A serious problem with VLSI memory manufacturing is
`the longer test times required which result in higher chip
`costs. In order to reduce the test time, the multibit test
`mode was first implemented in 1-Mbit DRAM [14] and
`mode reduces the test time to 1/4 - 1/8 by testing four to
`was standardized in 4-Mbit DRAM. The multibit test
`
`eight bits simultaneously, but t h s multibit test method is
`limited to no more than 16 bits because of the larger area
`penalty caused by the additional circuit elements. To over-
`come this limitation, the concept of parallel testing is
`expanded to the LMT which simultaneously tests memory
`cells connected to a word line. The LMT reduces the test
`time drastically and the MPR enables a random pattern
`test along the word line.
`Fig. 6 shows the principle of a copy write in the LMT.
`Proceeding the copy write, test data should be written into
`the MPR utilizing the cache register function which is
`independent of the DRAM array operation. The MPR
`permits a random test pattern on a line. This random data
`pattern in the MPR is written into the memory cells on the
`selected word-line simultaneously. In the circuit diagram
`of Fig. 4, these operations are controlled by raising TR
`and selecting SACi “high” with COMP (LMT compare
`trigger signal) remaining “low.”
`Fig. 7 shows the principlc of the parallcl compare called
`a “line read.” the readout cell data on a word line are
`transferred through the sub 1/0 lines. The expected data
`pattern latched in the MPR is transferred as well. When
`the test-compare-trigger signal COMP goes “high” and
`TR remains “low,” parallel-compare is carried out by the
`comparator, which detects the coincidence between the
`readout data and the expected data. Then a merged test
`result appears on the match line. If there exists at least one
`comparator with disagreement, a fault signal (ERROR
`
`4
`
`

`
`I
`
`I
`
`L0.7pm
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO. 5 , OCTOBER 1989
`
`1 4 LOCOS
`Isolation
`
`1 2 -
`Field
`Shield
`Isolation
`
`1 1 -
`
`1 0
`
`c E,
`0
`3
`c
`5
`? 6 >
`
`1
`
`1188
`
`Storage Node W-Bit line CC
`fll Plate W-Local Interconnect
`'lug /
`/ W-F
`/
`/
`
`/
`
`/
`
`,
`Field Shield Isol-"--
`allull
`
`Offset Gate
`Fig 9. Cross sectional view of T-shaped stacked capacitor cell
`
`ea
`Storage Node
`w Local Interconnect
`0 W Bitline
`
`Cell Plate
`Contact
`r--, ; ; ActlVe Area
`
`0 6 0 6 1 0 1 2
`1 4 1 6
`Channel Width W (pm)
`Narrow channel characteristic of NMOSFET's
`
`Fig. 11.
`
`16M wards x 1 Ut I' 4M wtk?dB x4 bits
`
`Fig 10 Top view of stacked capacitor cells at bit-line twistmg part.
`
`IV. DEVICE TECHNOLOGY
`
`-sectional view of the memory cells, called T-
`shaped stacked capacitor cells [15], is shown in Fig. 9. The
`contact hole connecting the storage node to the N + region
`is formed by a fully self-aligned technique utilizing the
`sidewall spacer with a word line and field shield plate. The
`thick CVD oxide film is formed before the storage node
`process. Using this thick film, a T-shaped storage capaci-
`5 fF was obtained with a 6-nm oxide equivalent
`layer. Moreover, the thick CVD oxide f i h re-
`sults in a planarized structure and makes the patterning of
`the storage node easier. The selectively formed CVD tung-
`in the deep contact hole, and the tungsten local
`ect layer, connect the bit line to the N + area.
`e areas are isolated by the field shield plate of
`polysilicon. The field shield isolation transistor has the
`self-aligned sidewall of an LDD transistor, but it has no
`N- region. Thus the field shield transistor has an offset
`gate structure. Ths structure reduces the parasitic capaci-
`tance between the field shield plate and the source/drain,
`and has a high threshold voltage of 4.0 V. Fig. 10 shows a
`top view of the stacked capacitor cells at the bit-line
`twisting section. This local interconnect wiring is used for
`TBL's as shown, and minimizes the additional area penalty
`inherent in the TBL array. Fig. 11 compares the narrow
`channel characteristic of the NMOSFET's isolated by the
`field shield with that of those isolated by LOCOS. The
`horizontal axis is the designed channel width, and the
`vertical axis is the variation of the threshold voltage whch
`is normalized at a 1.6-pm channel width. The threshold
`
`Chip Size 7.7 mm X 17.5 mm
`Cell Size 1.5 pm X 3.2 pm
`Fig. 12 Photomicrograph of 16 Mbit DRAM
`
`voltage of the LOCOS isolation FET increases rapidly at a
`channel width under 1 pm because of the severe narrow
`channel effect. In the case of the field shield isolation FET,
`the threshold voltage has been controlled to within 10
`percent, even for a8.6-pm channel width device. This is
`because the field shield isolation is free from the bird's
`beak and does not need a'boron implantation channel
`stop. Therefore, the field sheld isolation has the advantage
`of eliminating the narrow channel effect, and can be
`applied to a scaled-down 16-Mbit DRAM memory cell
`with 0.8-pm dimensions. The gate length of the memory
`cell transistor is 0.7 i m and the oxide thckness of the
`active transistor is 15 nm.
`In peripheral circuits, the gate lengths of 0.6-pm NMOS
`and 0.8-pm PMOS transistors with fully self-aligned source
`and drain contacts [15] provide the same current drivabil-
`ity as that of 0.8-pm (NMOS)/l.O-pm (PMOS) conven-
`tional LDD transistors at 5-V operation, respectively.
`Therefore, these transistor performances and the scaled-
`down load capacitance give a faster operating speed at
`3.3 V than at 5.0 V with an on-chip limiter.
`
`V. RAM CHARACTERISTICS
`
`A 16-Mbit CMOS DRAM was designed and evaluated.
`The RAM has been fabricated using a 0.6-pm twin-well
`CMOS process and double-level aluminum wiring.
`shows a photomicrograph of the RAM. The memory array
`is divided into eight 2-Mbit blocks by the row decoders
`
`5
`
`

`
`ARIMOTO et d. : 16-MBIT DRAM WITH MULTIPURPOSE REGISTER
`
`TABLE I1
`SUMMARY OF 16-MBIT DRAM CHARACTERISTICS
`
`O r g a n i z a t i o n
`
`i6H w o r d s X 1 bit / 4 M k o r d s X 4 b i t s
`( netal mask o p t i o n )
`
`P r o c e s s t e c h n o l o g y
`
`
`
`0 . 5 ~ ~ t w i n - u e l l C M O S
`
`Chip s i z e
`
`Cell s i z e
`
`O p e r a t i o n mode
`
`A c c e s s t i m e
`
`D o u b l e level AI w i r i n g
`
`F i e l d s h i e l d isolation
`
`7.7 X 17.5 mm‘
`
`1.5 x 3 . 2 “ U 2
`
`F a s t page / S t a t i c c o l u m n / N i b b l e / Serial
`( b o n d i n g o p t i o n )
`
`T R A C
`
`T C A A
`
`60 ns ( V c c = 3.3V )
`2 0 n s ( V c c = 3 3V , f r o m s e n s e a m p . )
`15 n s ( V c c = 3 3V , from MPR )
`
`Supply c u r r e n t
`
`O p e r a t i n g 90 mA ( V c c = 3.3V , T c = 1 2 0 n s )
`0.2 m A ( C M O S level V c c = 3.3V )
`S t a n d b y
`
`Refresh c y c l e
`
`2 0 4 8 / 3 2 m s
`
`R e d u n d a n c y
`
`1 2 8 r o w s
`
`1 6 c o l u m n s by laser b l o w
`
`O t h e r f u n c t i o n s
`
`L i n e mode t e s t (1024b) / Multi-bit-test ( 1 6 b )
`Copy w r i t e / C a c h e / Burn-in
`( b o n d i n g o p t i o n , logic c o n t r o l )
`
`P a c k a g e
`
`400-mil S O J
`
`Fig. 13. Output waveforms.
`
`and column decoders. The main control circuits are placed
`at the center of the chip, and the local array control
`circuits are located at both edges of the chip to minimize
`the array access time. The centrally placed row decoder
`and the polycide word line shunted by first aluminum at
`five points reduce the word-line delay. The RAM has four
`MPR bands, consisting of 2 kbits each, and these are
`located at both sides of the column decoders. The 36 ALS
`sense-amplifier bands divide the array into subarrays. The
`features and characteristics of the RAM are summarized in
`Table 11. It is organized as 16M words by 1 bit or 4M
`words by 4 bits (second metal option). The RAM has a die
`area of 135 mm2. The memory cell size is 4.8 pm2. The
`operating waveforms of the RAM are shown in Fig. 13. An
`RAS access time of 60 ns has been obtained under typical
`conditions at 3.3 V. Dual column address access times are
`20 ns (from the sense amplifier) and 15 ns (from the
`
`1189
`
`MPR). The active power dissipation is 300 mW at a cycle
`time of 120 ns. The 3.3-V power supply reduces the power
`dissipation. Throughout the entire chip, 128-row and 16-
`column redundancies are employed by using the laser
`programmable redundancy technique.
`
`VI. CONCLUSION
`
`A high-performance 16-Mbit DRAM design point has
`been proposed which includes several features. A single
`3.3-V power supply achieves lower power dissipation of
`300 mW than a 5-V power supply scheme with an on-chip
`limiter. The twisted-bit-line array architecture gives a wide
`operating margin and yield improvement. The MPR real-
`izes a faster access and enables an effective line-mode test,
`copy write, and high-speed cache access capability. The
`LMT reduces the test time to 1/1000. Good isolation of
`the field shield plate and the T-shaped stacked capacitor
`contributed to satisfactory device characteristics and a
`storage capacitance of 35 fF. This 3.3-V 16-
`design can therefore meet the needs of high-
`CPU’s.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank H. H
`Asakura for their helpful discussions, and
`Ozaki, Y. Tanaka, Y. Watakabe, A. Shigeto
`and K. Moriizumi for the preparing samples
`tions. They also wish to thank K. Shibayama,
`T. Kato, and T. Yoshihara for their encouragement and
`support.
`
`REFERENCES
`
`M. Aoki et ul., “Aft experimental 16Mb DRAM with transposed
`in ISSCC Dig. Tech Papers, Feb. 1988,
`data-line structure,
`pp. 252-253.
`M. Inoue et al., “A 16 Mb DRAM with an open bit-line architec-
`ture,’’ in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 246-241.
`S. Watanabe et al., “An experimental 16Mb CMOS DRAM chip
`with a 100 MHz serial read/write operation,” in ISSCC Dig. Tech.
`Paners. Feb 1988. DD 246-241.
`T.=Mano et al., “tircuit technologies for 16Mb DRAMs,” in
`ISSCC Dig. Tech. Papers, Feb. 1987, pp. 22-23.
`M Horig&i et al., ‘‘Dual-operating:<oltage scheme for a single
`5-V 16-Mbit DRAM,” IEEE J. Solid-State Circuits, vol. 23,
`pp 1120-1127, Oct 1988
`G. Baccaram, M R Wordeman, and R. H. Dennard, “Generaked
`scaling theory and its application to a 1/4 micrometer MOSFET
`- _
`design.” IEEE Trans. Electron Devices, vol. ED-31, DD. 452-462,
`Aprr1984.
`M. Kakumu et al., “Power supply voltage for future CMOS VLSIs
`in half and lower submicrometer,” in IEDM Tech. Dig., Dec. 1986,
`nn 399-402.
`“r: YoshihGa er al., “A twisted bit line technique for multi-Mb
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 24, NO 5, OCTOBER 1989
`
`In 1987 he joined the LSI Research and Devel-
`opment Laboratory, Mitsubishi Electric Corpo-
`ration, Itami, Japan Since then he has been
`engaged in the development of ULSI dynamic
`RAM’s He is currently involved in the develop-
`ment of CMOS 16-Mbit dynamic RAM
`
`Kazutami Arimoto (M88) was born in Waka-
`yama, Japan, on March 9, 1957 He received the
`B S and M S degrees in electncal engineering
`from Osaka University, Osaka, Japan, in 1979
`and 1981, respectively
`He joined the LSI Research and Development
`Electric Corporation,
`1981 Since then he has
`been engaged in the design of VLSI MOS dy-
`namic RAMs
`Mr Arimoto is a member of the Institute of
`Electronics, Information and Communication Engineers of Japan
`
`Kazuyasu Fujishima was bom in Itami, Japan, on
`May 22, 1950 He received the B.S, M S., and
`Dr degrees in electrical engineering from Osaka
`University, Suita, Japan, in 1973,1975, and 1987,
`respectively
`In 1975 he joined the Central Research Labo-
`ratories, Mitsubishi Electric Corporation,
`Amagasaki, Japan In 1976 he transferred to
`Mitsubishi‘s LSI Research and Development
`Laboratory, Itami, Japan From 1975 to 1978 he
`worked on high-density CCD memory Since
`1978 he has been engaged in the development of 64K through 16-Mbit
`MOS dynamic RAM’s He is currently working on the design of DRAM-
`based VLSI memones.
`Dr Fujishima is a member of the Insbtute of Electromcs, Informahon
`and Communication Engineers of Japan
`
`Yoshio Matsuda was born in Ehime, Japan, on
`October 26, 1954 He received the B S degree in
`physics and the M S and Dr degrees in applied
`physics from Osaka Umversity, Osaka, Japan, in
`1977, 1979, and 1983, respectively
`In 1985 he joined the LSI Research and Devel-
`opment Laboratory, Mitsubish Electric Corpo-
`ration, Itami-shi, Japan Since then he has been
`engaged in the development of 4-Mbit DRAM
`and cache DRAM, whch is DRAM with on-chp
`SRAM cache He is currently worlung on the
`design of 16-Mbit DRAM
`Dr Matsuda is a member of the Physical Society of Japan
`
`Masaki Tsukude was bom in Hiroslnma, Japan.
`on December 29, 1961 He received the B S and
`M S degrees in electromc engineering from Hi
`roshima University, Hiroshuna, Japan, in 1985
`and 1987, respectwely
`He joined the LSI Research and Development
`Laboratory, Mtsubish Electric Corporation
`Itami, Hyogo, Japan, in 1987 Since then he has
`been engaged in the design of VLSI MOS dy-
`namic RAMs
`
`Tukasa O‘ishi was born in Koch, Japan, on August 31,1962 He received
`the B S and M S degrees in electromc engineering from Shbaura Insti-
`tute of Technology, Tokyo, Japan, in 1985 and 1987, respectively
`
`Wataru Wakamiya was born in Osaka, Japan, on
`October 28, ,1953 He received the B.S degree in
`electncat engineering from Osaka Umversity,
`Osaka, Japan, in 1977
`He joined the LSI Research and Development
`Laboratory, Mitsubishi Electric Corporation,
`Hyogo, Japan, in 1977, and has been engaged in
`the development of the optical lithography pro-
`cess He IS currently worlung on the development
`of the device technology of MOS dynamic mem-
`ories.
`
`Shin-ichi Satoh was born in Gigu, Japan, on
`November 12, 1948 He received the B S degree
`in chemistry from Kobe Umversity, Kobe, Japan,
`in 1972, and the Ph D degree from Osaka Um
`versity, Osaka, Japan, in 1985
`He joined the Mitsubish Electric Corporation,
`Tokyo, Japan, in 1972, and has been engaged in
`the development of process technologies In 1977
`he joined the Mtsubishl LSI Research and De-
`velopment Laboratory, Hyogo, Japan, and is
`currently working on the development of device
`memones
`technologies of VLSI
`Dr. Satoh is a men
`iber of the Japan 3ociety of Applied Physics
`
`Michihiro Yamada was born in Japan on January
`10, 1950 He received the B S degree in applied
`physics from the University of Tokyo, Tokyo,
`Japan, in 1972, an
`degree from Osaka
`
`gasaki, Japan Starting in 1973 he became
`involved in the research and development of
`(CCD’s) In 1976 he
`transferred to Mitsubishi‘s LSI Research and
`he has been involved in
`Development Laboiatory, Itami, Japan, whe
`urrently worlung on the
`the development of CCD memories he is
`development of MOS dynamic memories
`Dr. Yamada is a member of the Institute of Electromcs and Communi-
`cation Engineers of Japan
`
`Takao Nakano (SM88) was bom in Hyogo,
`Japan, on September 1, 1939 He received the
`B S , M S , and Ph D degrees in electronics engi-
`neering from Osaka Umversity, Osaka, Japan, in
`1962, 1964, and 1968, respectwely
`He joined the Central Research Laboratones,
`Ivfitsubishi Electric Corporation, Tokyo, Japan,
`in April 1964 From 1964 to 1967 he was en-
`gaged in the research and development of opto-
`electromc devices at the Semiconductor Research
`Institute, Sendq Japan, and the Central Re-
`search Laboratones, Wtsubishi Electric Corporation Since 1968 he has
`been involved in the research and development of bipolar and MOS LSI
`devlces His most recent activities have included the development of
`high-speed large-capacity VLSI He is currently the Manager of the LSI
`Device Development Department at the LSI Research and Development
`Laboratory, Mtsubish Electric Corporahon, Itami, Hyogo, Japan.
`Dr Nakano is a member of the Physical Society of Japan, the Institute
`of Electromcs Informabon and Communication Engineers of Japan, the
`Applied Physics of Japan, and the Insbtute of Electrical Engineers of
`Japan
`
`7