UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`APPLE INC.,
`
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`
`Patent Owner.
`
`
`
`Patent No. 6,233,181
`Issue Date: May 15, 2001
`Filed: Feb. 17, 1999
`Inventor: Hideto Hidaka
`Title: SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`Inter Partes Review No. IPR2016-01561
`
`____________________________________________________________
`
`PATENT OWNER’S RESPONSE
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`
`
`
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`
`TABLE OF CONTENTS
`
`Page
`
`I. 
`
`II. 
`
`INTRODUCTION ........................................................................................... 1 
`
`SUMMARY OF THE ’181 PATENT ............................................................. 4 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`The Inventions Disclosed in the ’181 Patent ......................................... 4 
`
`Level of Ordinary Skill in the Art ......................................................... 9 
`
`Claim Interpretation ............................................................................ 11 
`
`Claim 3 Requires More Than A Mere Shared Sense
`Amplifier Design ................................................................................. 12 
`
`Claim 5 Requires Two Memory Arrays, And Control
`Circuitry For Driving Memory Blocks Into A Selected State ............ 15 
`
`III.  OVERVIEW OF THE CITED ART ............................................................. 16 
`
`A.  Overview of Sukegawa ....................................................................... 16 
`
`B. 
`
`C. 
`
`Overview of Fujishima ........................................................................ 22 
`
`Overview of Walck ............................................................................. 28 
`
`IV.  THE PETITION FAILS TO ESTABLISH THAT CLAIMS 3
`AND 5 ARE OBVIOUS ................................................................................ 31 
`
`A. 
`
`B. 
`
`Legal Standard ..................................................................................... 34 
`
`The Petition Fails To Establish That Claim 3 Is Obvious
`Over Sukegawa In View Of Fujishima Because It Does Not
`Provide Adequate Support For Combining The Teachings Of
`Fujishima With Sukegawa .................................................................. 36 
`
`1. 
`
`None Of The Alleged Motivations Asserted In The
`Petition Would Cause A Person Having Ordinary
`
`
`
`i
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`Skill In The Art To Arrive At The Proposed
`Combination .............................................................................. 38 
`
`a. 
`
`b. 
`
`Fujishima Does Not Suggest Any Reason For
`Adopting The Alternate Arrangement Type
`Shared Sense Amplifier Design—Particularly
`With Respect To The Claimed Redundancy
`Scheme ............................................................................ 38 
`
`None of the remaining alleged motivations
`would cause a person having ordinary skill in
`the art to arrive at the proposed combination ................. 40 
`
`2. 
`
`3. 
`
`Fujishima’s Alternate Arrangement Shared Sense
`Amplifier Design Was Understood To Be
`Incompatible With The ANY TO ANY Redundancy
`Scheme ...................................................................................... 45 
`
`The Ancillary Art And Dr. Mazumder Himself
`Taught Away From Applying Inter-Block Word Line
`Redundancy Schemes ............................................................... 50 
`
`a. 
`
`b. 
`
`c. 
`
`d. 
`
`e. 
`
`The Horiguchi IEEE Article Teaches Away
`From The Proposed Combination .................................. 51 
`
`The Arimoto IEEE Article Would Not Suggest
`The Proposed Combination ............................................ 53 
`
`U.S. Patent No. 5,687,123 (“Hidaka”) Would
`Not Suggest The Proposed Combination ....................... 55 
`
`U.S. Patent No. 5,726,946 (“Yamagata”)
`Would Not
`Suggest
`The
`Proposed
`Combination ................................................................... 55 
`
`U.S. Patent No. 6,003,148 (“Yamauchi”)
`Would Not
`Suggest
`The
`Proposed
`Combination ................................................................... 56 
`
`
`
`ii
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`U.S. Patent No. 6,075,743 (“Barth”) Would
`Not Suggest The Proposed Combination ....................... 57 
`
`U.S. Patent No. 5,956,285 (“Watanabe”)
`Would Not
`Suggest
`The
`Proposed
`Combination ................................................................... 57 
`
`The 1997 Horiguchi IEEE Article Would Not
`Suggest The Proposed Combination .............................. 58 
`
`f. 
`
`g. 
`
`h. 
`
`4. 
`
`Sukegawa Teaches Away From The ANY TO ANY
`Redundancy Scheme, And Therefore Would Not
`Motivate A Person Having Ordinary Skill In The Art
`To Adopt An Inter-Block Redundancy Scheme ....................... 60 
`
`D. 
`
`The Petition Fails To Establish That Claim 5 Is Obvious
`Over Sukegawa and Fujishima In View Of Walck Because
`The Proposed Combination Does Not Teach All Elements Of
`The Challenged Claim ......................................................................... 62 
`
`1.  Walck Does Not Disclose The Claimed Control
`Circuitry For Driving Memory Blocks Into A
`Selected State ............................................................................ 63 
`
`2. 
`
`The Teachings Of Sukegawa, Fujishima, And Walck
`Would Not Motivate A Person Having Ordinary Skill
`In The Art To Arrive At The Claimed Memory
`Device ....................................................................................... 65 
`
`V. 
`
`CONCLUSION .............................................................................................. 65 
`
`
`
`
`
`iii
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`TABLE OF AUTHORITIES
`
`Page
`
`Cases 
`Cisco Sys., Inc. v. C-Cation Techs., LLC,
`Case IPR2014-00454 (PTAB Aug. 29, 2014) (Paper 12) .................................... 12
`Comaper Corp. v. Antec, Inc.,
`596 F.3d 1343 (Fed. Cir. 2010) ............................................................................ 43
`Graham v. John Deere Co.,
`383 U.S. 1 (1966) ................................................................................................. 34
`In re NTP, Inc.,
`654 F.3d 1279 (Fed. Cir. 2011) ..................................................................... 36, 37
`InTouch Techs., Inc. v. VGo Comms., Inc.,
`751 F.3d 1327 (Fed. Cir. 2014) ............................................................... 36, 41, 43
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 34, 36
`Personal Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987 (Fed. Cir. 2017) ................................................................. 35, 40, 45
`Power Integrations, Inc. v. Fairchild Semiconductor Int’l, Inc.,
`711 F.3d 1348 (Fed. Cir. 2013) ..................................................................... 36, 62
`Star Scientific, Inc. v. R.J. Reynolds Tobacco Co.,
`655 F.3d 1364 (Fed. Cir. 2011) ............................................................................ 36
`Std. Oil Co. v. Am. Cyanamid Co.,
`774 F.2d 448 (Fed. Cir. 1985) ................................................................. 34, 35, 42
`Vivid Techs. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) .............................................................................. 11
`Wowza Media Sys., LLC v. Adobe Sys. Inc.,
`Case IPR2013-00054 (PTAB Jul. 13, 2013) (Paper 16) ...................................... 41
`Statutes 
`35 U.S.C. § 103 ................................................................................................. 34, 35
`35 U.S.C. § 316 .......................................................................................................... 1
`Regulations 
`37 C.F.R. § 42.100 ................................................................................................... 11
`37 C.F.R. § 42.6 ....................................................................................................... 12
`
`
`
`iv
`
`

`

`LIST OF EXHIBITS
`
`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`
`
`
`EXHIBIT
`TITLE
`NO.
`1001* Declaration of Dr. Pinaki Mazumder
`1002*
`Curriculum Vitae of Dr. Pinaki Mazumder
`1003* U.S. Patent No. 6,233,181
`1004*
`File History for U.S. Patent No. 6,233,181
`1005* U.S. Patent No. 5,487,040 to Sukegawa
`1006* U.S. Patent No. 5,267,214 to Fujishima
`1007* U.S. Patent No. 4,967,397 to Walck
`1008* U.S. Patent No. 5,956,285 to Watanabe
`Masashi Horiguchi et al., A Flexible Redundancy Technique for High-
`Density DRAM’s, IEEE Journal of Solid-State Circuits, Vol. 26, No.
`1, Jan. 1991, at 12-17.
`Kazutami Arimoto et al., A 60-ns 3.3-V-Only 16 Mbit DRAM with
`Multipurpose Register, IEEE Journal of Solid-State Circuits, Vol. 24,
`No. 5, Oct. 1989, at 1184-90.
`1011* U.S. Patent No. 5,687,123 to Hidaka
`1012* U.S. Patent No. 5,726,946 to Yamagata
`1013* U.S. Patent No. 6,003,148 to Yamauchi
`1014* U.S. Patent No. 6,075,743 to Barth
`Inter Partes Review No. IPR2016-00096, Decision Granting
`1015*
`Institution filed April 21, 2016.
`Inter Partes Review No. IPR2016-00096, Judgment Granting
`Request for Adverse Judgment filed August 3, 2016.
`Limestone Memory Sys. LLC v. Apple Inc., Case No. 8:15-cv-01274,
`Dkt. No. 52 (C.D. Cal. Jan. 12, 2016) (Order Granting Motions to
`Stay Cases Pending Inter Partes Review)
`Limestone Memory Sys. LLC v. Apple Inc., Case No. 8:15-cv-01274,
`2002*
`Dkt. No. 58 (C.D. Cal. Sep. 2, 2016) (Joint Status Report)
`2003* Micron Technology, Inc., v. Limestone Memory Systems LLC, Case
`IPR2016-00696, (PTAB Oct. 26, 2015) (Paper 1)
`Declaration of Dr. Sunil Khatri
`2004
`Curriculum Vitae of Dr. Sunil Khatri
`2005
`
`1009*
`
`1010*
`
`1016*
`
`2001*
`
`
`
`v
`
`

`

`2006
`
`2007
`2008
`
`2009
`
`2010
`
`2011
`
`2012
`
`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`KANAD CHAKRABORTY & PINAKI MAZUMDER, FAULT-TOLERANCE
`AND RELIABILITY TECHNIQUES FOR HIGH-DENSITY RANDOM-ACCESS
`MEMORIES (2002) (excerpts).
`Transcript of April 27, 2017 Deposition of Dr. Pinaki Mazumder
`IEEE STANDARD DICTIONARY OF ELECTRICAL AND ELECTRONIC
`TERMS (3d Ed. 1977) (excerpts)
`IEEE STANDARD DICTIONARY OF ELECTRICAL AND ELECTRONIC
`TERMS (5th Ed. 1992) (excerpts)
`IEEE STANDARD DICTIONARY OF ELECTRICAL AND ELECTRONIC
`TERMS (6th Ed. 1997) (excerpts)
`Fairchild Semiconductor, 74F538 1-of-8 Decoder with 3-STATE
`Outputs (April 1988), available at
`http://www.komponenten.es.aau.dk/fileadmin/komponenten/Data_She
`et/MOS-TTL/f/74F538.pdf.
`Masashi Horiguchi, Redundancy Techniques for High-Density
`DRAMs, INNOVATIVE SYSTEMS IN SILICON CONFERENCE,
`Oct. 1997, at p. 24
`2013 Masashi Horiguchi et al., NANOSCALE MEMORY REPAIR 30
`(Springer 2011) (excerpts)
`Search results for “APD/19760101->19980609 AND DRAM” in the
`USPTO Patent Full Text and Image Database
`Search results for “APD/19760101->19980609 AND (DRAM and
`"redundant memory")” in the in the USPTO Patent Full Text and
`Image Database
`Search results for “APD/19760101->19980609 AND ICL/G11C07/00
`OR ICL/G11C011/34 OR ICL/G11C013/00” in the in the USPTO
`Patent Full Text and Image Database
`
`2014
`
`2015
`
`2016
`
` Previously filed.
`
`vi
`
` *
`
`
`
`
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`
`I.
`
`INTRODUCTION
`
`This proceeding commenced when Petitioner, Apple Inc., filed a Petition for
`
`inter partes review of claims 3 and 5 of the ’181 patent. (Paper 1.) Patent Owner
`
`Limestone Memory Systems LLC (“LMS”) timely filed a Preliminary Response,
`
`arguing that the Petition failed to satisfy its burden, because it did not identify
`
`adequate motivation for combining the teachings of Fujishima with Sukegawa.
`
`(Paper 10.) The Patent Trial and Appeal Board (“Board”) entered its Decision on
`
`Institution on February 7, 2017 (“Decision”), by which it ordered the institution of
`
`trial on claims 3 and 5. (Paper 11.) LMS respectfully submits this Response in
`
`accordance with 37 C.F.R. § 42.120, opposing the Petition and responding to the
`
`Decision as to the two instituted grounds.
`
`The reasoning offered in the Petition does not hold up to the increased scrutiny
`
`required at this stage of the proceedings, which requires that the Petition must show
`
`by a preponderance of the evidence that claims 3 and 5 are invalid. 35 U.S.C. §
`
`316(e). Both of the asserted grounds of invalidity incorrectly characterize the
`
`disclosures and benefits of the prior art.
`
`The Petition asserts that claim 3 of U.S. Patent No. 6,233,181 (“the ’181
`
`patent”) is unpatentably obvious over a combined system comprising the ANY TO
`
`ANY redundancy scheme disclosed in U.S. Patent No. 5,487,040 to Sukegawa et al.
`
`(“Sukegawa”), in view of the alternative arrangement type shared sense amplifier
`
`
`
`1
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`design illustrated in FIG. 14 of U.S. Patent No. 5,267,214 to Fujishima et al.
`
`(“Fujishima”). The Decision cited the alleged benefits of using shared sense
`
`amplifier bands, as cited in the Petition, as motivation for combining the references.
`
`(Paper 11 at 7, 9–10.) But neither of the cited references nor the Petition identifies
`
`any benefits of the “alternative arrangement type shared sense amplifier” design,
`
`illustrated in Fujishima’s FIG. 14, relative to Fujishima’s other embodiments and
`
`the design implemented in Sukegawa. The alleged benefits of the proposed
`
`combination, as identified in the Petition, lack merit in view this failing to show why
`
`one of ordinary skill would choose one embodiment over another.
`
`Further, the Petition improperly ignores the full teachings of Sukegawa, and
`
`the Decision accordingly cited Sukegawa’s allegedly express encouragement of
`
`inter-block redundancy schemes as evidence overcoming contrary teachings in the
`
`art. (Paper 11 at 8.) But Sukegawa disfavors the ANY TO ANY approach, teaching
`
`a preferred embodiment that relies upon redundancy in which word lines are fixed
`
`to each memory block.
`
`Last with respect to claim 3, the Decision cited “evidence indicating that
`
`‘there would have been no undue obstacle’ to combining the cited teachings in
`
`Sukegawa and Fujishima.” (Paper 11 at 9.) The only evidence provided in the
`
`Petition is the declaration of the Petitioner’s hired expert, Dr. Mazumder, whose own
`
`book establishes that “inter-subarray replacement (i.e., replacing a defective normal
`
`
`
`2
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`line in a subarray by a spare line in another subarray) is an impractical idea because
`
`it will lead to undue complexity in the design of the sense circuitry.” (Ex. 2007 at 9
`
`(emphasis added).) Dr. Mazumder’s testimony establishes numerous design factors
`
`that his declaration simply ignores. Further, Dr. Mazumder’s testimony establishes
`
`that his analysis improperly relied upon hindsight, using the claims themselves as a
`
`roadmap for combining the prior art, based in part upon review of earlier Petitions
`
`filed against the ’181 patent, and supported by his own over-qualified experience.
`
`Both the Petition and Dr. Mazumder’s declaration ignore the considerable
`
`difficulties related to combining Fujishima with Sukegawa, as supported by exhibits
`
`hereto and the declaration of Dr. Sunil Khatri, a qualified expert retained by LMS.
`
`Claim 3 is therefore patentable over the combined system because the person having
`
`ordinary skill in the art would not have combined Fujishima with Sukegawa.
`
`As to claim 5, the Petition asserts it is obvious over a combined system
`
`comprising Sukegawa and Fujishima, further in view of the DRAM controller
`
`disclosed by U.S. Patent No. 4,967,397 to Walck (“Walck”). But Walck discloses
`
`an outdated arrangement designed to control separate DRAM chips, which simply
`
`does not disclose controller circuitry for selecting memory blocks. Claim 5 is
`
`therefore patentable both because it depends from claim 3 and because the combined
`
`system, as described in the Petition, does not disclose every limitation.
`
`
`
`3
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`
`II.
`
`SUMMARY OF THE ’181 PATENT
`
`A.
`
`The Inventions Disclosed in the ’181 Patent
`
`The ’181 patent discloses a memory chip having a spare memory array with
`
`spare memory cells, where the spare memory array is common to a plurality of
`
`normal sub-arrays having a plurality of normal memory cells. (Ex. 1003 at
`
`Abstract.) Thus, the disclosed spare memory array provides a redundancy circuit
`
`across block1 boundaries in a memory array divided into a plurality of memory
`
`blocks. (Ex. 1003 at 1:6–13.) The ’181 patent also discloses devices that provide a
`
`power supply circuit corresponding to each memory block. (Id.)
`
`The ’181 patent explains that “logical independence” of the plurality of
`
`memory blocks is a factor affecting efficient replacement of defective word lines
`
`across memory blocks. Memory blocks are logically independent if defective word
`
`lines in a first block may be replaced without affecting the second block. (Id. at 2:51–
`
`3:8 (“M/m is the number of memory arrays which are logically independent from
`
`one another,” where M is the number of memory blocks and m is the “number of
`
`memory arrays whose defective normal word lines are replaced with spare word
`
`lines simultaneously”).) Effectively, logical independence means that rows of one
`
`block can be replaced with spare rows without affecting what can be done with the
`
`other block. (Ex. 2004 ¶ 61.) For example, the ’181 patent explains that “in FIG. 53,
`
`
`1 The ’181 patent also refers to blocks as “sub-arrays.” (E.g., Ex. 1003 at Abstract.)
`
`
`
`4
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`if a normal word line is simultaneously selected in memory arrays MA0 and MA2,
`
`memory arrays MA0 and MA2 are not logically independent from each other.” (Id.
`
`at 2:67–3:3.) According to the ’181 patent, the logical independence of the memory
`
`blocks is important, because it allows more flexibility in the redundancy scheme (Ex.
`
`2004 ¶ 61).
`
`According to the ’181 patent, achieving logical independence is hard, from a
`
`replacement standpoint, because when components (such as sense amplifiers) are
`
`shared across memory blocks, control of the memory block needs to be more
`
`complicated to isolate the desired memory cells (whether redundant or normal) in a
`
`given memory block. (Ex. 2004 ¶ 62.) The following passage illustrates the problem
`
`as it was known in the prior art:
`
`If a defective normal word line in one memory array is replaced with a
`spare word line in another memory array, the control of the memory
`array related circuits will be complicated, and therefore such
`arrangement must be avoided and is not considered at all.
`
`(Ex. 1008 at 3:58–67 (referring to “A Flexible Redundancy Technique for High-
`
`Density DRAM’s,” Horiguchi et al., IEEE Journal of Solid-State Circuits, Vol. 26,
`
`No. 1, January 1991, pp. 12 to 17)2, cited at 1:24–26 and described throughout the
`
`“Description of the Background Art”).) Horiguchi et. al states that “to replace
`
`
`2 The Petition cites this same reference as Ex. 1009, and it is discussed further below.
`
`
`
`5
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`defective normal line in a subarray by a spare line in another subarray should be
`
`avoided in DRAM redundancy.” (Ex. 1009 at 12.) The ‘181 patent further describes
`
`similar problems that arise when controlling power supplies for the memory array.
`
`(Ex. 1008 at 6:25–40.) In view of these problems identified in the art, the ‘181 patent
`
`describes its objects in part as providing an array-divided semiconductor memory
`
`device including a redundancy circuit, which increases the use efficiency of spare
`
`lines without erroneous operation. (Id. at 6:43–51 (emphasis added).)
`
`The ’181 patent discloses a number of features. When arranged together, these
`
`features improve the replacement efficiency of spare word lines, thus improving the
`
`overall efficiency of the chip. (Ex. 2004 ¶ 63.) For example, the embodiment
`
`illustrated in figure 9 discloses shared spare row decoders, which reduce the overall
`
`number of such spare row decoders. (Ex. 1008 at 16:31–39.)
`
`
`
`6
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`
`
`
`(Id. at FIG. 9.) According to the ’181 patent, the advantage in this arrangement lies
`
`in the increased efficiency of using spare word lines because they are shared among
`
`all of the normal memory blocks. (Id. at 16:65–17:4.)
`
`Another feature that adds to the efficient use of chip resources is the use of
`
`shared sense amplifier bands.
`
`Sense amplifier bands SAB1 to SABm are provided between memory
`sub-arrays adjacent to one another in the column direction. A sense
`amplifier band SAB0 is provided outside normal memory sub-array
`MA#0-0, and a sense amplifier band SABm+l is provided adjacent to
`normal memory sub-array MA#l-N.
`
`These sense amplifier bands SAB0 to SABm+l have an alternate
`shared sense amplifier arrangement. When one normal memory sub-
`
`
`
`7
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`array or row block is selected, the sense amplifiers included in the sense
`amplifier bands provided on both sides are used for sensing operation.
`
`(Id. at 17:43–53 (emphasis added).) By positioning sense amplifier bands on either
`
`side of each memory block, the efficiency of the memory is improved. (Id. at 18:7–
`
`10.)
`
`The embodiment described above is illustrated in FIGS. 11 and 15, which
`
`illustrates yet another benefit of the shared sense amplifier architecture.
`
`
`
`8
`
`
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`(Id. at FIG. 11.) The written description explains that erroneous operation of the
`
`respective memory blocks is therefore reduced because access conflicts are
`
`prevented in this configuration. (Id. at 19:50–63.) These architectural features and
`
`others are recited in the claims of the ’181 patent, as discussed further below.
`
`B.
`
`Level of Ordinary Skill in the Art
`
`A person having ordinary skill in the art would have a bachelor’s degree in a
`
`field such as electrical engineering, computer engineering, computer science, or a
`
`closely related field, along with at least 4–5 years of experience in the design,
`
`development, and/or testing of memory devices. An individual with an advanced
`
`degree in a relevant field would require less experience in the design of memory
`
`devices. (Ex. 2004 ¶ 31.)
`
`The Petition asserts a substantially higher level of ordinary skill in the art
`
`based solely on the supporting Mazumder declaration. (Pet. at 5–6.) But the
`
`Mazumder declaration does not offer any analysis or reason for arriving at the high
`
`level of skill except in a footnote where Dr. Mazumder cites his “experience.” (Ex.
`
`1001 at 17 n.4.) Neither the Mazumder declaration nor the Petition explains how Dr.
`
`Mazumder’s experience informs his opinion. Dr. Mazumder testified that, in his
`
`experience, companies designing memory chips frequently hire individuals with
`
`graduate degrees. (E.g., Mazumder Depo. Tr. at 76:10–78:5, 78:21–83:8.)
`
`
`
`9
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`Dr. Khatri offers a contradictory analysis, based on his experience and
`
`knowledge of the industry, explaining that many of the individuals hired by
`
`companies designing memory chips do not have graduate degrees, and thus the level
`
`of ordinary skill in the art should specifically include such individuals. (Ex. 2004 ¶
`
`32.) Dr. Khatri explains that the customary practice in Japan and Korea, where many
`
`memory chip manufacturers design and fabricate memory chips, is to hire
`
`individuals with an undergraduate degree and then train them on the job. (Id.)
`
`Regardless of the typical educational background of the person having
`
`ordinary skill in the art, Dr. Khatri also offers the opinion that educational pedigree
`
`does not necessarily correspond to deeper knowledge of the art relevant to the ‘181
`
`patent. (Ex. 2004 ¶ 33.)
`
`In contrast, although Dr. Mazumder apparently has (and had) substantially
`
`more experience than the person of ordinary skill at the time of the invention, neither
`
`the Petition nor the supporting declaration offers any analysis of how the
`
`hypothetical person’s skill would differ from Dr. Mazumder’s own knowledge and
`
`skill. By 1998, the priority date of the ’181 patent, Dr. Mazumder was already an
`
`assistant professor at the University of Michigan with at least ten years of academic
`
`experience in addition to six years of industry experience. (See Ex. 1001 at 6–9; Ex.
`
`2007 at 86:14–87:14.) Indeed, Dr. Mazumder testified that he applied his own
`
`knowledge when analyzing the obviousness of the claims of the ’181 patent. (Ex.
`
`
`
`10
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`2007 at 85:5–86:13 (“I was mostly concentrating on the – the materials that I had in
`
`aggregation, plus my knowledge.”).) Because he ascribes an exceedingly high level
`
`of experience to the person having ordinary skill in the art, and further applies his
`
`own personal level of skill, Dr. Mazumder’s conclusions are apt to overstate the
`
`ability of the person having ordinary skill in the art and the relative obviousness of
`
`the proposed combinations.
`
`C. Claim Interpretation
`In an inter partes review, the Board construes claim terms in an unexpired
`
`patent using their broadest reasonable construction in light of the specification of the
`
`patent in which they appear. 37 C.F.R. § 42.100(b); Cuozzo Speed Techs., 136 S.Ct.
`
`at 2142. Only those terms that are in controversy need to be construed, and only to
`
`the extent necessary to resolve the controversy. Vivid Techs. v. Am. Sci. & Eng’g,
`
`Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). LMS contends that no construction is
`
`necessary, but notes that the plain language of the claims bears consideration.3
`
`Accordingly, the limitations of claims 3 and 5 are discussed in the paragraphs below.
`
`
`3 Petitioner notes that it does not disagree with constructions proposed by MTI in the
`
`’096 Petition. (Pet. at 6, note 2.) Those constructions, however, are not offered as
`
`part of the Petition and therefore cannot be considered by the Board in the instant
`
`case. 37 CFR §42.6 (a)(3); Cisco Sys., Inc. v. C-Cation Techs., LLC, Case IPR2014-
`
`
`
`11
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`D. Claim 3 Requires More Than A Mere Shared Sense Amplifier
`Design
`
`Claim 3 depends from and incorporates every limitation recited in both of
`
`claims 1 and 2. These three claims are provided below.
`
`1. A semiconductor memory device, comprising:
`a plurality of first memory blocks each having a plurality of first
`normal memory cells arranged in a matrix of rows and columns,
`each of said plurality of first memory blocks including word lines
`provided corresponding to said rows, respectively, and the first
`memory blocks aligned in the column direction; and
`a plurality of first spare memory cells arranged in a matrix of rows
`and columns in a particular one of said plurality of first memory
`blocks, each row of said plurality of first spare memory cells
`being capable of replacing a defective row including a defective
`first normal memory cell in said plurality of first memory blocks.
`
`2. The semiconductor memory device as recited in claim 1, further
`comprising:
`a plurality of second memory blocks arranged alternatively with said
`plurality of first memory blocks along the column direction, the
`second memory blocks each having a plurality of second normal
`memory cells arranged in a matrix of rows and columns; and
`
`
`00454, slip op. at 7–10 (PTAB Aug. 29, 2014) (Paper 12) (forbidding incorporation
`
`by reference).
`
`
`
`12
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`a plurality of second spare memory cells arranged in a matrix of
`rows and columns in a particular one of said plurality of second
`memory blocks, each row of said plurality of second spare
`memory cells being capable of replacing a defective row
`including a defective second normal memory cell in said
`plurality of second memory blocks.
`
`3. The semiconductor memory device as recited in claim 2, further
`comprising a plurality of sense amplifier bands provided between each
`of said plurality of first memory blocks and each of said second
`memory blocks, and shared by adjacent memory blocks in the column
`direction for sensing and amplifying data in each column of the adjacent
`memory block including a selected memory cell when activated.
`
`(Ex. 1006 at 45:55–46:31.)
`
`Claim 1 recites, in part, a first plurality of memory blocks and a plurality of
`
`first spare memory cells arranged in a matrix of rows and columns in a particular
`
`one of said plurality of first memory blocks. An example of this configuration is
`
`illustrated in FIGS. 9 and 10 (both of which also appear on the first page of the
`
`patent). (Ex. 2004 ¶¶ 63, 106.) Dr. Mazumder testified that this language requires
`
`replacing a normal memory cell in any block with the recited spare cell. (Ex. 2007
`
`at 128:10–129:4.) This language therefore requires replacing memory cells across
`
`block boundaries. (Ex. 2007 at 129:5–21; Ex. 2004 ¶ 122.)
`
`Claim 2 incorporates the limitations of claim 1 and further recites, in part, a
`
`second plurality of memory blocks, arranged alternatively with the first plurality.
`
`
`
`13
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`The plain language of claims 1 and 2 requires a column of memory blocks in which
`
`memory blocks from the first plurality alternate with memory blocks from the
`
`second plurality. Claim 1 recites “the first memory blocks aligned in the column
`
`direction” and claim 2 recites “a plurality of second memory blocks arranged
`
`alternatively with said plurality of first memory blocks along the column direction.”
`
`Because the memory blocks are all aligned in the column direction and because they
`
`are further arranged alternatively along the column direction, a memory block from
`
`the first plurality must be followed by a memory block from the second plurality,
`
`which must be followed by a memory block from the first plurality. (Ex. 2004 ¶107,
`
`see also ¶ 64.)
`
`Claim 3 incorporates the limitations of claims 1 and 2 and further recites, in
`
`part, “a plurality of sense amplifier bands provided between each of said plurality of
`
`first memory blocks and each of said second memory blocks.” Both Dr. Mazumder
`
`and Dr. Khatri agree that this limitation requires a sense amplifier band disposed on
`
`both sides of the first memory blocks to the extent there is a second memory block
`
`on both sides of the first memory block. (Ex. 2007 at 124:5–125:2; Ex. 2004 ¶ 108.)
`
`If a first memory block has a second memory block on each side, a sense amplifier
`
`band must lie between the first memory block and the respective second memory
`
`blocks on both sides of the first memory block. (Ex. 2004 ¶ 108.) This interpretation
`
`comports with the configuration illustrated in FIGS. 11 and 15, in which sense
`
`
`
`14
`
`

`

`PATENT OWNER’S RESPONSE IN IPR2016-01561
`U.S. PATENT NO. 6,233,181
`amplifier bands (e.g., SAB1 and SAB2) lie on both sides of a first memory block
`
`(e.g., MA#1-0), between the first memory block and respective second memory
`
`blocks (e.g., MA#0-0 and MA#0-1). (Id.)
`
`E. Claim 5 Requires Two Memory Arrays, And Control Circuitry For
`Driving Memory Blocks Into A Selected State
`
`Claim 5 depends from and incorporates every limitation recited in claims 1,
`
`2, and 3, as discussed above. Claim 5 recites the following additional limitations.
`
`5. The semiconductor memory device as recited in claim 3, wherein
`said plurality of first memory blocks, said plurality of second
`memory blocks and said plurality of sense amplifier bands form
`a first memory array, and
`said semiconductor memory device further comprises:
`a second memory array having a same arrangement as the first
`memory