Redundancy Techniques for High-Density DRAMs
`
`Masashi Horiguchi
`Semiconductor and Integrated Circuits Div., Hitachi Ltd.
`Kokubunji, Tokyo 185, Japan
`
`Abstract
`This paper describes the redundancy techniques for high-density DRAMs to solve the
`following two problems arisen with the increase in memory capacity: (1) the increase in
`·memory-array division reduces the replacement flexibility between defective lines and spare
`lines; (2) the defects causing OC-characteristics faults, especially excessive standby current
`faults cannot be repaired with the conventional redundancy techniques. First, two approaches
`to solve the first problem are discussed: enhancing the replacement flexibility within the limits
`of intra-subarray replacement, and the introduction of inter-subarray replacement. Next, the
`recent proposals to solve the second problem are reported. The DC-characteristics faults are
`repaired through the modification of bitline precharge eircuit or the subarray-replacement
`redundancy
`
`1. Introduction
`Redundancy techniques have been widely
`used as effective methods of enhancing the
`production yield and reducing cost-per-bit of
`DRAMs since 64 - 256-kbit generations [1] -
`[5]. The currently used technique replaces
`defective memory
`elements
`(usually
`wordlines and/or bitlines (datalines)) by on(cid:173)
`chip spare elements as shown in Fig. 1.
`However, with
`the increase in memory
`capacity, the following two problems have
`arisen.
`One is
`in memory-array
`the increase
`division shown in Fig .. 2. The number of
`subarrays doubled each generation before
`64-Mbit. This is mainly due to the bitline
`division
`for
`the
`signal/noise
`ratio
`enhancement and the charging/discharging
`current reduction [6], [7]. The number of
`divisions even quadrupled each generation
`introduction of hierarchical
`after
`the
`wordline architecture [8], [9]. The bounda(cid:173)
`ries between subarrays work as barriers to
`the defective-element
`replacement,
`and
`reduces the replacement flexibility, resulting
`in yield degradation.
`The other problem is the defects causing
`DC-characteristics faults, especially exces(cid:173)
`sive standby current (/SB) faults.
`An
`example of an lsB fault is shown in Fig. 3
`[10]. A short circuit between a wordline
`( electrically connected to the ground in the
`standby state) and a bitline (connected to the
`bitline precharge voltage, VDD/2) creates an
`
`MA
`
`X
`
`Ao • An-1 <l-'n __ .,i
`Programmed: Wo W1 W2 W3
`X: Row Decoder
`Y: Column Decoder
`SA: Sense Amplifiers
`AC: Address Comparator
`
`Fig. 1 Conventional redundancy technique
`applied to a DRAM.
`
`16384
`
`4096
`
`!ii.
`~
`! 1024
`
`~
`0)
`
`0
`
`i 256
`
`64
`
`16
`
`1SSCC'86 • 97
`
`. o~/'c,
`i~/
`
`o with J hierarchical
`• without wordline
`~,~f::/ :
`+/
`/( w
`
`i; 1c\'J~~~,~t~ :
`Ill
`Pl "
`Pl
`
`16M 64M 256M 1G
`4M
`Memory Capacity (bits)
`
`Fig. 2 Trend of memory-array division.
`
`22
`
`0-7803-4275-5/97 $8.00 ©1997 IEEE
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 1
`
`

`

`Session 2: Advances in Configuration for Fault Tolerance
`
`23
`
`to
`illegal DC current path from VDD/2
`ground. Replacing the wordline (bitline) by a
`spare wordline (spare bitline) inhibits the
`defective line from being accessed, but the
`current path still remains. Thus, the fault is
`not repaired by the conventional redundancy
`technique.
`redundancy
`the
`This paper describes
`techniques to solve these problems. First, the
`flexibility enhancement within the limits of
`intra-subarray replacement is discussed in
`Section 2.
`Second,
`the
`inter-subarray
`in
`replacement
`techniques are described
`Section 3. The recent proposals to repair the
`in
`OC-characteristics faults are
`reported
`Section 4.
`
`Chip
`
`Sense
`~;;;;;i-.i,~ Amplifier
`
`Spare I
`
`Wordline
`
`Word
`Driver
`
`~ DC Current Path
`
`Fig. 3 [SB fault model.
`
`J
`
`W1 W2 W3
`
`(a) simultaneous replacement
`
`2. Intra-subarray replacement
`redundancy
`Fig. 1 shows the well(cid:173)
`known redundancy technique
`[3], [5] applied to a DRAM
`without
`memory-array
`division. Redundant bitlines
`are
`omitted
`here
`for
`simplicity. The memory has
`L
`(here, L = 4)
`spare
`wordlines SWO - SW3 and as
`many address comparators
`ACO - AC3. Defective word
`addresses are programmed
`(usually by fuses)
`in
`the
`address
`comparators
`and
`compared with
`the
`input
`address. Thus, at most L
`defective normal wordlines
`can be repaired.
`In
`this
`example, defective normal
`- W3 are
`wordlines WO
`replaced by spare wordlines
`SWO - SW3, respectively, as
`shown by the arrows in the
`figure.
`consider
`let us
`Now
`dividing the memory array
`into subarrays.
`Two ap(cid:173)
`proaches within the limits of
`intra-subarray
`replacement
`are shown in Fig. 4(a) and
`(b ). Here the memory array
`MA in Fig. I is divided into
`four subarrays, MAo - MA3,
`only one of which is selected.
`In
`the simultaneous re(cid:173)
`placement (Fig. 4(a)),
`the
`
`Ao-An-a
`:
`'-------rl-.rL-YL---'"L_- _yL____ - n
`An-2, An-1
`Programmed: Wo W1 W, none Wa none none none
`
`ACo
`
`(b) individual replacement
`Fig. 4 Conventional intra-subarray replacement redundancy
`techniques applied to a DRAM with memory-array division.
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 2
`
`

`

`24
`
`1996 Innovative Systems in Silicon Conference
`
`MAa
`
`Xa
`
`number of address compara(cid:173)
`tors equals L, the number of
`spare wordlines
`in a sub(cid:173)
`array.
`Each address com(cid:173)
`parator compares only
`the
`intra-subarray address signals
`(here, Ao - An-3), and the
`output is commonly supplied
`to all the subarrays.
`The
`inter-subarray address signals
`(here, An-2 and An-I) in tum
`select one of the four spare
`wordlines. As many defec(cid:173)
`tive wordlines can be repaired
`as are shown in Fig. 1, if L is
`the same as that of Fig. 1. In
`this approach four normal
`lines are replaced simultane(cid:173)
`ously by spare lines. That is,
`to replace one defective normal line, three other normal lines with the same intra-subarray
`address are also replaced even if they are not defective. This caus.es the following problems.
`First, the usage efficiency of spare lines is lower, and the number of spare lines should be
`larger, which results in chip-area increase. Second, the probability of unsuccessful repair due
`to defects in the spare lines that replaced normal lines is higher, which results in yield
`degradation.
`In the individual replacement (Fig. 4(b)), every spare line in every subarray has its own
`address comparator. The number of address comparators is therefore L*M, where M (= 4) is
`the number of subarrays. Each address comparator compares both intra- and inter-subarray
`address signals.
`This approach has
`the following advantages over the simultaneous
`replacement. First, a smaller L is statistically required (here, L = 2) to repair as many defects.
`This is because the probability of clustered defects in a particular subarray is small under
`random defect distribution. Second, since only one normal line is at a time replaced by a spare
`line, the probability of a defect in the spare line is lower. This approach, however, has the
`
`Wa w, W2
`
`Fig. 5 Flexible intra-subarray replacement redundancy
`technique applied to a DRAM with memory-array division.
`
`1Gbit
`M a256
`ma4
`
`10
`8
`6
`
`40 s. ,,
`
`(1)
`Q.
`2 §
`Q. .,
`:,
`.l!
`1a
`
`Flexible
`(La 4, Ca 16)
`
`Conventional
`(LaCa8)
`
`6
`8
`2
`4
`Defect Density (cm -2)
`
`10
`
`4
`
`8
`6
`4
`2
`Defect Density (cm -2)
`
`6
`8
`2
`4
`Defect Density (cm -2)
`
`10
`
`(c) 1-Gbit DRAM
`(b) 64-Mbit DRAM
`(a) 4-Mbit DRAM
`Fig. 6 Calculated DRAM yield with conventional and flexible intra-subarray replacement
`redundancy techniques.
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 3
`
`

`

`Session 2: Advances in Configuration for Fault Tolerance
`
`25
`
`Sense Amplifier
`Defect MA,.,
`
`MA;
`
`B
`-!:B:........,,-.....0-.,..,c.....i:...i:.+ ......_.=x=-..'.,(J
`t
`Bitline
`Defect
`
`1/0
`
`disadvantage of lower usage efficiency of address comparators, resulting in an increase in the
`_
`,
`area of address comparators.
`Fig. 5 shows the flexible intra-subarray replacement scheme [11] proposed to overcome the
`problems described above. The spare lines and address comparators are not connected directly,
`but through the OR gates Go and GI. Each address comparators compares both intra- and inter(cid:173)
`subarray address signals. This connection provides a flexible relationship between spare lines
`and address comparators. In the architecture shown in Fig. 4, this relationship is fixed so that a
`spare line can be activated only by a particular address comparator. However in Fig. 5, a spare
`line can be activated by one of several address comparators. Another advantage of this
`architecture
`is
`that more
`flexible
`selection of the number of address
`as well as
`the
`comparators C.
`relationship L ~ C ~ L*Mlm stands,
`where mis the number of subarrays in
`which defective normal
`lines are
`simultaneously
`replaced by
`spare
`lines.
`The calculated yield through the
`conventional (Fig. 4(a)) and flexible
`intra-subarray replacement
`(Fig. 5)
`redundancy techniques is shown in
`Fig. 6. The yield improvement factors
`through the both techniques are almost
`the same in a 4-Mbit DRAM. The
`advantage of the flexible technique
`becomes apparent in 64-Mbit and 1-
`Gbit DRAMs, especially for a large
`defect density, that is, in the early
`stages of production. For a 1-Gbit
`DRAM, however,
`the yield
`is
`determined mainly by fatal defects,
`those causing excessive
`such as
`standby current.
`intra-subarray
`When the flexible
`is applied
`to bitline
`replacement
`redundancy, the problem of a' global'
`defect (a defect over two or more
`subarrays) arises. A defect on a
`sense-amplifier or a column selection
`line (CSL) in a DRAM using the
`multidivided bitline architecture [6],
`[7] causes two or more bitlines to fail
`simultaneously as shown in Fig. 7.
`Thus
`these
`types of defects are
`'global' and require more than one
`address comparators to be repaired.
`To solve this problem, programming
`in
`address
`"don't-care"
`values
`comparators was proposed
`[I I].
`Table I shows the number of address
`to repair the
`comparators required
`various defects with and without
`"don't-care" programming.
`to
`The access-time penalty due
`redundancy is the delay time required
`for the address comparison. Fig. 8
`
`B
`
`B
`
`" " " " · · ·
`
`t. _____ J _______ CSL ---------x ------ y
`t
`CSL
`Defect
`
`Fig. 7 Defect modes in memory array using
`multidivided bitline architecture.
`
`Table I Number of address comparators required to
`repair defects.
`
`Defect
`mode
`
`Bitline
`Sense amp.
`CSL
`
`Number of address comparators
`
`with "don't-care"
`programming
`
`without "don't-care"
`programming
`
`1
`1
`1
`
`1
`2
`n*
`
`*n: number of subarrays connected to a CSL
`
`i MA,
`
`Fig. 8 No access-penalty intra-subarray replacement
`redundancy technique [12] (simultaneous activation of
`normal and spare lines)-
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 4
`
`

`

`26
`
`1996 Innovative Systems in Silicon Conference
`
`shows a technique to eliminate this delay time for a high-speed SRAM [12]. In this technique, a
`defective line in a subarray is replaced by a spare line in the adjacent subarray. The two
`subarrays are activated simultaneously and one of the data from them is selected according to the
`result of address comparison. This technique is difficult to be applied to wordline redundancy
`of a DRAM because of the doubling of the bitline charging/discharging current·· 1;1owever,. it
`can be applied to bitline redundancy [13]. Note that this technique is not inter-subarray
`replacement. This will be clear if the hatched areas in Fig. 8 are assumed to be a subarray and
`the white areas are assumed to be another subarray.
`
`MA1
`
`MA2
`
`MAa
`
`MAo
`
`,
`
`3. lnter-subarray replacement redundancy
`With the further increase in memory-array division, the probability of clustered defects in a
`particular subarray becomes no more negligible. In the intra-subarray replacement, the number
`of spare lines in a subarray, L, must be larger or equal to the maximum number of .defective
`lines in a subarray to repair clustered defects. This causes the increase in L and chip-area
`penalty.
`To solve this problem, inter-subarray replacement redundancy techniques [14] - [16] were
`proposed, which permit a defective line to be replaced by a spare line in any subarray. They are
`classified into two categories as shown in Fig. 9.
`In the distributed-spare-line approach [14] shown in Fig. 9(a), each subarray has its own
`spare lines like the intra-subarray replacement. Each spare line, however, can replace any
`defective normal line not only
`in the same subarray but also
`in another subarray. There(cid:173)
`fore at most L*M defects
`in
`a particular
`clustered
`subarray can be repaired,
`where M is the number of
`subarrays.
`In this example,
`four
`clustered
`defective
`normal wordlines WO - W3
`are replaced · by the spare
`wordlines in subarrays MAo,
`It is suffi(cid:173)
`MAI and MA2.
`cient for successful repair that
`the number L is the average
`number of defective lines in a
`subarray and is smaller than,
`that of
`intra-subarray
`re(cid:173)
`placement. The number of
`address comparators C
`is
`equal to L * M in this case.
`The number, however, can
`be
`reduced
`through
`the
`similar technique shown in
`Fig. 5.
`In the concentrated-spare(cid:173)
`line approach
`[15],
`[16]
`shown in Fig. 9(b), each
`subarray has no spare lines.
`There is a spare subarray
`MAs, instead, composed of
`L' (here, L' = 5) spare lines.
`Each spare line can replace a
`defective normal line in any
`subarray. Therefore at most
`
`(a) distributed spare lines
`
`W3
`
`- r:-:::,1,r
`
`Ao - An-3 -
`An-2, An~1
`Programmed: Wo W1
`
`w. Wa none none none
`
`.
`(b) concentrated spare lines
`Fig.9 Inter-subarray replacement redundancy techniques.
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 5
`
`

`

`Session 2: Advances in Configuration for Fault Tolerance
`
`27
`
`100 1-,-~~------.----------,
`L' defects clustered in a subarray can.
`be repaired. The number of address
`~
`16 Subarrays
`comparators C is equal to L'. This:
`e...
`--···--···· lntra-subarray
`approach has an advantage of more ~ 80
`:a
`- - lnter-subarray
`flexible selection of L' (= C) and
`
`L:1
`
`0'--'---'---'--_.__-'-'-'-'.._-'-~~~~~~~~~~
`0
`10
`20
`30
`Number of Defects K
`
`Fig. IO Comparison between intra- and inter-subarray
`replacement redundancy techniques.
`
`64M
`
`256M
`
`1G
`
`D=2cm·2
`
`80
`
`-., 60
`.;
`;;:
`
`40
`
`20
`
`better usage of address comparators I so
`o.
`compared to the distributed-spare-
`:a 40
`line approach. This is because the
`size of the spare subarray need not
`f!
`·.;
`be the same as that of a normal
`The problem of this £ 20
`subarray.
`approach is that additional circuits (a
`decoder, a sense amplifier, etc.) for
`MAs are needed. A solution of this
`problem using the hierarchical bitline
`architecture is proposed in [15J.
`Fig. 10 compares the repairable
`probability using intra- and inter(cid:173)
`subarray
`replacement
`redundancy
`techniques [14], [l6J. Here, defects
`causing fatal faults and defects on
`spare
`lines
`are neglected
`for
`simplicity.
`In the intra-subarray
`replacement, the repairable probabil-
`ity of a memory composed of M
`subarrays
`decreases with
`the
`increase in the number of defects, K,
`because the probability of excessive
`(> L) defects in a particular subarray
`increases. On the other hand, the
`repairable probability is constantly
`100% as long as K ::; L*M in the
`inter-subarray replacement
`The
`expectation of repairable defects
`through inter-subarray replacement
`is about three times that through
`intra-subarray replacement when the
`number of subarrays is 16.
`The access-time penalty of the inter-subarray replacement is usually larger than that of intra(cid:173)
`subarray replacement. This is because not only an activated-line but also an activated subarray
`may be changed according to the result of address comparison.
`
`0
`1
`
`2
`Chip Area (cm 21
`Fig. I I Yield improvement through line and subarray
`replacement.
`
`4
`
`4. Repair of DC-characteristics faults
`As described in Section 2, the yield of gigabit DRAMs will be mainly determined by defects
`causing DC-characteristics faults, especially excessive standby current (!SB) faults. The
`conventional line-replacement redundancy is not sufficient for DRAMs of 256 Mbit or larger,
`due to !SB faults as shown in Fig. 11 [IO]. Several redundancy techniques were proposed to
`enable the repairof such faults [IO], [16], [17].
`Fig. 12 shows two techniques to repair a short circuit between a wordline and a bitline. Both
`technique modify the bitline precharge circuit. The first approach (Fig. 12(a)) [16] limits the
`illegal OC-current through the short circuit to a small value (-15 µA/ short circuit) by a current
`limiter. The !SB of a memory chip with a relatively small number of short circuits is thereby
`limited within the specification. The second approach (Fig. l 2(b)) [ 17] cuts off the DC-current
`It is reported that the test to locate short-circuit
`path by a power switch controlled by a fuse.
`faults is possible using the switch.
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 6
`
`

`

`28
`
`1996 Innovative Systems in Silicon Conference
`
`Fig. 13 shows another
`technique [10) using spare
`subarrays.
`A defective
`subarray including an !SB
`fault is replaced by an on(cid:173)
`chip spare subarray. Each
`subarray
`has
`power
`switches for bitline pre(cid:173)
`charge voltage VDD/2 and
`memory-cell plate voltage
`VPL, logic gates for timing
`to
`signals, and a fuse
`control them. The power
`switches of the defective ,
`subarray are turned off and I
`those of the spare subarray
`are turned on. Thus the !SB
`fault is repaired by cutting
`of the OC current. The
`logic gates of the defective
`subarray are also turned off
`to avoid unnecessary power
`dissipation in the subarray.
`This
`technique combined
`with the conventional line(cid:173)
`replacement
`redundancy
`doubles the yield of a 256-
`Mbit DRAM as shown in
`Fig. 11. An advantage of
`this technique is that the
`in an unused
`wordlines
`spare subarray are used as
`spare wordlines of
`the
`concentrated-spare-line
`inter-subarray replacement
`in
`redundancy described
`Section 3 [18).
`redundancy
`Since
`this
`technique
`requires
`spare
`subarrays, it is not suitable
`for a small-capacity mem(cid:173)
`ory with a small number of
`subarrays. However, the
`number of subarrays
`in(cid:173)
`creases with every DRAM
`generation as shown in Fig.
`2. The area penalty will be
`allowable for DRAMs of
`256 Mbit and beyond as
`shown in Fig. 14.
`It is
`interesting that the memory(cid:173)
`array division, which was
`the barrier
`to
`the
`line(cid:173)
`replacement redundancy, in
`tum, supports the subarray(cid:173)
`replacement redundancy.
`
`Bitline
`Prech_~_r11,e
`
`B
`
`e
`
`Bltllne
`Precharg_e
`
`B
`
`e
`
`PC
`
`Voo/2
`
`PC
`
`(b) power switch
`(a) current limiter
`Fig. 12 Short-circuit defect repairing schemes [ 16], [ 1 7).
`
`Timing~------- >--,,,_ _____ __.. __ ,._....1.
`Address ======c.'==11========='-'=
`Fig. 13 Subarray-replacement redundancy technique [ 1 OJ.
`
`8 Spare Subarrays
`4 Spare Lines/ Subarray
`~ ROMs and Circuitry
`[:=J Spare Cells
`
`16M
`
`256M
`64M
`Memory Capacity (bit)
`
`1G
`
`64
`
`256
`128
`Number of Subarrays
`
`512
`
`Fig. 14 Chip-area penalty due to redundancy.
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2012, p. 7
`
`

`

`Session 2: Advances in Configuration for Fault Tolerance
`
`29
`
`S. Conclusion
`Redundancy techniques to solve the problems arisen with the increase in DRAM capacity
`were discussed. Enhancing the replacement flexibility between defective lines and spare lines
`through the flexible intra-subarray replacement or through inter-subarray replacement is
`effective for DRAMs of increased memory-array division. The DC-characteristics faults,
`especially excessive standby-current faults, are repaired through the modification of bitline
`precharge circuit or the subarray-replacement redundancy. The optimal combination of these
`techniques will be critical for the yield enhancement and bit-per cost reduction of gigabit
`DRAMs.
`
`Acknowledgment
`The author would like to thank K. Itoh, M. Aoki, G. Kitsukawa, and Y. Nakagome for their
`suggestions and discussions.
`
`References
`[1] R. P. Cenker etal., "A fault-tolerant64K dynamic random-access memory," IEEE Trans.
`Electron Devices, vol. ED-26, pp. 853-860, June 1979.
`[2] T. Mano et al., "A redundancy circuit for a fault-tolerant 256K MOS RAM," IEEE J. Solid(cid:173)
`State Circuits, vol. SC-17, pp. 726-731, Oct. 1982.
`[3] S. S. Eaton et al., "A lOOns 64K dynamic RAM using redundancy techniques, 11 in ISSCC
`Dig. Tech. Papers, Feb. 1981, pp. 84-85.
`[ 4] R. T. Smith et al., "Laser programmable redundancy and yield improvement in a 64K
`DRAM" IEEE J. Solid-State Circuits, ,vol. SC-16, pp. 506-514, Oct. 1981.
`[5] K. Shimohigashi et al., "Redundancy techniques for dynamic RAMs, 11 in Proc. 14th Conf.
`Solid State Devices, Aug. 1982, pp. 63-67.
`[6] R. Hori et al., "An experimental 1 Mbit DRAM based on high S/N design," IEEE J. Solid(cid:173)
`State Circuits, vol. SC-19, pp. 634-640, Oct. 1984.
`[7] K. ltoh, ''Trends in megabit DRAM circuit design," IEEE J. Solid-State Circuits, vol. 25,
`pp. 778-789, June 1990.
`[8] D. Galbi et al., "A 33-ns 64-Mbit DRAM with master-wordline architecture," in ESSCIRC
`Dig. Tech. Papers, Sep. 1992, pp. 131-134.
`[9] T. Sugibayashi et al., "A 30-ns 256-Mb DRAM with multidivided array structure," IEEE J.
`Solid-State Circuits, vol. 28, pp. 1092-1098, Nov. 1993.
`[10] G. Kitsukawa et al., "256-Mb DRAM circuit technologies for file applications," IEEE J.
`Solid-State Circuits, vol. 28, pp. 1105-1113, Nov. 1993.
`[11] M. Horiguchi et al., "A flexible redundancy technique for high-density DRAMs" IEEE J.
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