74F538 1-of-8 Decoder with 3-STATE Outputs
`
`April 1988
`Revised January 2004
`
`74F538
`1-of-8 Decoder with 3-STATE Outputs
`
`Features
`I Output polarity control
`I Data demultiplexing capability
`I Multiple enables for expansion
`I 3-STATE outputs
`
`General Description
`The 74F538 decoder/demultiplexer accepts three Address
`(A0–A2) input signals and decodes them to select one of
`eight mutually exclusive outputs. A polarity control input (P)
`determines whether the outputs are active LOW or active
`HIGH. A HIGH Signal on either of the active LOW Output
`Enable (OE) inputs forces all outputs to the high imped-
`ance state. Two active HIGH and two active LOW input
`enables are available for easy expansion to 1-of 32 decod-
`ing with four packages, or for data demultiplexing to 1-of-8
`or 1-of-16 destinations.
`
`Ordering Code:
`
`Package Description
`Order Number Package Number
`20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
`74F538SC
`M20B
`20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
`74F538PC
`N20A
`Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
`
`Logic Symbols
`
`Connection Diagram
`
`IEEE/IEC
`
`© 2004 Fairchild Semiconductor Corporation
`
`DS009551
`
`www.fairchildsemi.com
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 1
`
`

`

`U.L.
`HIGH/LOW
`1.0/1.0
`1.0/1.0
`1.0/1.0
`1.0/1.0
`1.0/1.0
`150/40 (33.3)
`
`Input IIH/IIL
`Output IOH/IOL
`20 µA/−0.6 mA
`20 µA/−0.6 mA
`20 µA/−0.6 mA
`20 µA/−0.6 mA
`20 µA/−0.6 mA
`−3 mA/24 mA (20 mA)
`
`Outputs Equal P Input
`
`Outputs
`A0 O0 O1 O2 O3 O4 O5 O6 O7
`X
`Z
`Z
`Z
`Z
`Z
`Z
`Z
`Z
`X
`Z
`Z
`Z
`Z
`Z
`Z
`Z
`Z
`X
`X
`X
`X
`L
`H
`L
`H
`L
`H
`L
`H
`L
`H
`L
`H
`L
`H
`L
`H
`
`H
`L
`L
`L
`L
`L
`L
`L
`L
`H
`H
`H
`H
`H
`H
`H
`
`L
`H
`L
`L
`L
`L
`L
`L
`H
`L
`H
`H
`H
`H
`H
`H
`
`L
`L
`H
`L
`L
`L
`L
`L
`H
`H
`L
`H
`H
`H
`H
`H
`
`L
`L
`L
`H
`L
`L
`L
`L
`H
`H
`H
`L
`H
`H
`H
`H
`
`L
`L
`L
`L
`H
`L
`L
`L
`H
`H
`H
`H
`L
`H
`H
`H
`
`L
`L
`L
`L
`L
`H
`L
`L
`H
`H
`H
`H
`H
`L
`H
`H
`
`L
`L
`L
`L
`L
`L
`H
`L
`H
`H
`H
`H
`H
`H
`L
`H
`
`L
`L
`L
`L
`L
`L
`L
`H
`H
`H
`H
`H
`H
`H
`H
`L
`
`Unit Loading/Fan Out
`
`Pin Names
`
`Description
`
`74F538
`
`A0–A2
`E1, E2
`E3, E4
`P
`OE1, OE2
`O0–O7
`
`Truth Table
`
`Address Inputs
`Enable Inputs (Active LOW)
`Enable Inputs (Active HIGH)
`Polarity Control Input
`Output Enable Inputs (Active LOW)
`3-STATE Outputs
`
`Function
`
`High
`Impedance
`Disable
`
`Active HIGH
`Output
`(P = L)
`
`Active LOW
`Output
`(P = H)
`
`OE1 OE2
`H
`X
`X
`H
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`
`E1
`X
`X
`H
`X
`X
`X
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`
`Inputs
`E3
`X
`X
`X
`X
`L
`X
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`
`E2
`X
`X
`X
`H
`X
`X
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`L
`
`E4
`X
`X
`X
`X
`X
`L
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`H
`
`A2
`X
`X
`X
`X
`X
`X
`L
`L
`L
`L
`H
`H
`H
`H
`L
`L
`L
`L
`H
`H
`H
`H
`
`A1
`X
`X
`X
`X
`X
`X
`L
`L
`H
`H
`L
`L
`H
`H
`L
`L
`H
`H
`L
`L
`H
`H
`
`H = HIGH Voltage Level
`L = LOW Voltage Level
`X = Immaterial
`Z = High Impedance
`
`www.fairchildsemi.com
`
`2
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 2
`
`

`

`74F538
`
`Logic Diagram
`
`Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
`
`3
`
`www.fairchildsemi.com
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 3
`
`

`

`Absolute Maximum Ratings(Note 1)
`−65°C to +150°C
`−55°C to +125°C
`−55°C to +150°C
`−0.5V to +7.0V
`−0.5V to +7.0V
`−30 mA to +5.0 mA
`
`74F538
`
`Storage Temperature
`Ambient Temperature under Bias
`Junction Temperature under Bias
`VCC Pin Potential to Ground Pin
`Input Voltage (Note 2)
`Input Current (Note 2)
`Voltage Applied to Output
`in HIGH State (with VCC = 0V)
`Standard Output
`3-STATE Output
`Current Applied to Output
`in LOW State (Max)
`
`Recommended Operating
`Conditions
`
`Free Air Ambient Temperature
`Supply Voltage
`
`0°C to +70°C
`+4.5V to +5.5V
`
`−0.5V to VCC
`−0.5V to +5.5V
`
`Note 1: Absolute maximum ratings are values beyond which the device
`may be damaged or have its useful life impaired. Functional operation
`under these conditions is not implied.
`Note 2: Either voltage limit or current limit is sufficient to protect inputs.
`
`twice the rated IOL (mA)
`
`DC Electrical Characteristics
`
`10% VCC
`10% VCC
` 5% VCC
` 5% VCC
`
`10% VCC
`
`Symbol
`VIH
`VIL
`VCD
`VOH
`
`Parameter
`
`Input HIGH Voltage
`Input LOW Voltage
`Input Clamp Diode Voltage
`Output HIGH
`Voltage
`
`VOL
`
`IIH
`IBVI
`
`ICEX
`
`VID
`
`IOD
`
`IIL
`IOZH
`IOZL
`IOS
`IZZ
`ICCH
`ICCL
`ICCZ
`
`Output LOW
`Voltage
`Input HIGH Current
`Input HIGH Current
`Breakdown Test
`Output HIGH
`Leakage Current
`Input Leakage
`Test
`Output Leakage
`Circuit Current
`Input LOW Current
`Output Leakage Current
`Output Leakage Current
`Output Short-Circuit Current
`Bus Drainage Test
`Power Supply Current
`Power Supply Current
`Power Supply Current
`
`Min
`
`2.0
`
`2.5
`2.4
`2.7
`2.7
`
`4.75
`
`−60
`
`www.fairchildsemi.com
`
`Typ
`
`Max
`
`Units
`
`VCC
`
`Conditions
`
`0.8
`−1.2
`
`0.5
`
`5.0
`
`7.0
`
`50
`
`3.75
`
`−0.6
`50
`−50
`−150
`500
`45
`56
`56
`
`V
`V
`V
`
`V
`
`V
`
`µA
`
`µA
`
`µA
`
`V
`
`µA
`
`mA
`µA
`µA
`mA
`µA
`mA
`mA
`mA
`
`Recognized as a HIGH Signal
`Recognized as a LOW Signal
`IIN = −18 mA
`IOH = −1 mA
`IOH = −3 mA
`IOH = −1 mA
`IOH = −3 mA
`IOL = 20 mA
`VIN = 2.7V
`VIN = 7.0V
`
`VOUT = VCC
`IID = 1.9 µA
`All Other Pins Grounded
`VIOD = 150 mV
`All Other Pins Grounded
`VIN = 0.5V
`VOUT = 2.7V
`VOUT = 0.5V
`VOUT = 0V
`VOUT = 5.25V
`VO = HIGH
`VO = LOW
`VO = HIGH Z
`
`Min
`
`Min
`
`Min
`
`Max
`
`Max
`
`Max
`
`0.0
`
`0.0
`
`Max
`Max
`Max
`Max
`0.0V
`Max
`Max
`Max
`
`31
`37
`37
`
`4
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 4
`
`

`

`74F538
`
`TA = +25°C
`VCC = +5.0V
`CL = 50 pF
`Typ
`11.0
`7.5
`8.5
`6.5
`11.0
`10.0
`11.5
`11.0
`5.5
`9.0
`4.0
`5.0
`
`Max
`16.0
`11.0
`15.0
`9.0
`16.0
`14.0
`18.0
`16.0
`10.0
`13.0
`6.0
`8.0
`
`Min
`6.0
`4.0
`5.0
`4.0
`6.0
`5.0
`6.0
`6.0
`3.0
`5.0
`2.0
`3.0
`
`TA = 0°C to +70°C
`VCC = +5.0V
`CL = 50 pF
`Min
`Max
`6.0
`17.0
`4.0
`12.0
`5.0
`16.0
`4.0
`10.0
`6.0
`17.0
`5.0
`15.0
`6.0
`20.0
`6.0
`17.0
`3.0
`11.0
`5.0
`14.0
`2.0
`7.0
`3.0
`9.0
`
`Units
`
`ns
`
`ns
`
`ns
`
`AC Electrical Characteristics
`
`Symbol
`
`Parameter
`
`tPLH
`tPHL
`tPLH
`tPHL
`tPLH
`tPHL
`tPLH
`tPHL
`tPZH
`tPZL
`tPHZ
`tPLZ
`
`Propagation Delay
`An to On
`Propagation Delay
`E1 or E2 to On
`Propagation Delay
`E3 or E4 to On
`Propagation Delay
`P to On
`Output Enable Time
`OE1 or OE2 to On
`Output Disable Time
`OE1 or OE2 to On
`
`5
`
`www.fairchildsemi.com
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 5
`
`

`

`Physical Dimensions inches (millimeters) unless otherwise noted
`
`74F538
`
`20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
`Package Number M20B
`
`www.fairchildsemi.com
`
`6
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 6
`
`

`

`74F538 1-of-8 Decoder with 3-STATE Outputs
`
`Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
`
`20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
`Package Number N20A
`
`Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
`Fairchild reserves the right at any time without notice to change said circuitry and specifications.
`
`LIFE SUPPORT POLICY
`
`FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
`DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
`SEMICONDUCTOR CORPORATION. As used herein:
`1. Life support devices or systems are devices or systems
`which, (a) are intended for surgical implant into the
`body, or (b) support or sustain life, and (c) whose failure
`to perform when properly used in accordance with
`instructions for use provided in the labeling, can be rea-
`sonably expected to result in a significant injury to the
`user.
`
`2. A critical component in any component of a life support
`device or system whose failure to perform can be rea-
`sonably expected to cause the failure of the life support
`device or system, or to affect its safety or effectiveness.
`
`www.fairchildsemi.com
`
`7
`
`www.fairchildsemi.com
`
`Limestone Memory Systems, LLC – Exhibit 2011, p. 7
`
`