Sunil P Khatri
`Professor
`Department of ECE, MS 3259,
`Texas A&M University,
`
`College Station, TX 77843
`sunilkhatri@tamu.edu
`Phone: (979) 845-8371
`Fax: (979) 845-2630
`http://www.ece.tamu.edu/~sunil/
`
`
`
`Background and Summary
`
`My research areas are:
`• Computer Systems: My work on Computer Systems is divided in two subcategories: 1)
`circuits and computer architecture (including the design of efficient Networks-on-Chip
`(NoCs), special function units for comparison, hashing, Boolean Satisfiability and sorting,
`low energy, low power circuit and high-speed design, system prototyping, as well as
`circuit/architectural approaches for radiation
`tolerance/detection, resilience, crosstalk
`avoidance, clocking, leakage/power reduction and testability); and 2) algorithm acceleration
`(using GPUs, FPGAs, map-reduce clusters and custom ICs) for algorithms in the VLSI CAD
`domain.
`Logic Synthesis and algorithms for VLSI Design: In this area, my work initially started in
`the space of logic synthesis for VLSI CAD. In the last few years, I have directed this work
`toward genomics, noise based logics, and Boolean Satisfiability solvers (using GPUs, FPGAs,
`map-reduce clusters and custom IC based accelerators).
`Interdisciplinary extensions: The above two areas form a springboard from which I engage
`in research in other domains. I explore extensions of the above two areas to other areas such
`as IP routing, Digital Signal Processing (for FFT and radar signal processing), optical
`networking, wireless communication and coding, cryptography, satellite tracking and gene
`sequencing.
`
`•
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`•
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`I have a total of 235 peer-reviewed publications (35 journal papers, 159 conference papers, 41
`workshop papers). Among these papers, 5 received a best paper award, while 5 others received
`best paper nominations (including 1 journal best paper nomination). An additional 2 journal
`papers and 5 conference papers are currently undergoing peer review. I have co-authored 9
`research monographs (with 1 additional contract signed) and 1 edited research monograph, 3 book
`chapters (with an additional 2 invited chapters in progress) and 6 US Patents (one of which was
`filed at Texas A&M, and an additional patent submitted at Texas A&M). I have co-authored 1
`invited journal paper, 13 invited conference or workshop papers (including 1 from DAC and 1
`from Allerton). Moreover, I was invited to serve as a panelist at a conference 7 times, and have
`presented 2 conference tutorials. I received the “Outstanding Professor Award” in the ECE
`Department at Texas A&M University in 2007. My H-index is 28 (per Google Scholar).
`
`I have graduated 9 Ph.D. students (1 co-advised, 5 US citizens or residents, and one woman), 15
`M.S. students (3 US citizens, 2 of my MS students joined my Ph.D. program) and 5 B.S. Honors
`student whose thesis I advised. Currently, I advise 4 Ph.D. students (2 co-advised), 2 M.S.
`students and 2 B.S Honors research students (both US citizens). I have advised 28 undergraduates
`(17 under the NSF REU, URA or USRG programs), of which 4 students received an award for
`their research. Six papers in international conferences (1 invited) resulted from my work with
`undergraduates. The Ph.D. thesis of one of my students was nominated for the ACM Best
`Dissertation Award, 2014.
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`I have taught 3 distinct graduate courses and 3 distinct undergraduate courses at Texas A&M, have
`substantially redesigned the laboratories for one undergraduate course, and have assisted in the
`overhaul (lectures and laboratories) of another undergraduate course. My average undergraduate
`(graduate) teaching ratings are 4.49/5 (4.50/5). The departmental averages for similar courses are
`4.15 (undergraduate) and 4.45 (graduate). For undergraduate courses, my average numerical grade
`is 2.82, while the departmental average for equivalent level courses is 3.18. For graduate courses,
`these numbers are 3.74 and 3.66 respectively. In Fall 2009, I was awarded the “Association of
`Former Students’ Distinguished Achievement Award in Teaching”.
`
`I have 5 current research grants (total grant amount $2.2M, of which my portion is about $603K).
`The total amount of the grants in which I was involved to date is $13.02M, of which my portion is
`$3.27M. Some of these grants are with colleagues in ECE as well as other academic departments
`at TAMU. My research has been funded through government (NSF, LLNL, NSA, DNDO, DTRA,
`DoE) as well as industrial (Intel, Nascentric, NSC, SRC, Accelicon, Iris Technologies) sources.
`
` I
`
` currently serve, or have served, as the Associate Editor (ACM Transactions on Design
`Automation of Electronic Systems, IEEE Transactions on Computers, MDPI Journal of
`Electronics), EDA Track Co-Chair for ICECS 2014, Panel Chair for TexasWISE 2014, Track Co-
`Chair (VLSI Systems, Applications and Computer Aided Design track) for ICECS 2013, Poster
`Session Chair for TexasWISE 2013, Advisory Committee for HotPI 2013, Panel Session Chair for
`SLiP 2013, Track Chair (Logic track) for ICCAD 2009-10, 2015-6, Track Chair (logic track) for
`DAC 2016, General Chair for IWLS 2009, Technical Program Chair for IWLS 2008, Track Co-
`Chair, Computer Aided Network DEsign (CANDE) Track, for ISCAS 2008-10, Track Co-Chair,
`Test and Methodologies Track, for ICCD 2007, Panel Chair for ITSW 2009, Publicity Co-Chair
`for GLS-VLSI 2009, and as a member of the TPC for several conferences. I have conducted
`reviews of a large number of IEEE and ACM journal and conference papers. I have also served as
`a session chair at several conferences. In addition, I have been involved in Department and group
`level service activities.
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`Ph.D. University of California, Berkeley. Department of Electrical Engineering and Computer
`Sciences. (1993 - 99). Awarded the California MICRO Fellowship, 1993-94. Maintained
`a GPA of 3.963.
`
`
`M. S. University of Texas, Austin. Department of Electrical and Computer Engineering (1987
`- 89). Awarded the Microelectronics and Computer Development (MCD) Fellowship,
`1987-89). Maintained a GPA of 3.909.
`
`B. S.
`
`Indian Institute of Technology, Kanpur, India. Department of Electrical Engineering
`(1983 - 87). Obtained a GPA of 3.72, ranked fourth in a class of sixty students.
`
`Dissertation/Thesis
`
`
`Ph. D. "Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics". Committee:
`Professor R. K. Brayton (Co-chair), A. Sangiovanni-Vincentelli (Co-chair) and Professor
`Dorit Hochbaum, University of California, Berkeley.
`
`
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`
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`Education
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`
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`M. S. "The Design of the METRIC Memory Interface and Memory System". This involved
`the design of the memory interface of METRIC, a multi-threaded RISC Microprocessor.
`Committee: Professor M. Ray Mercer (chair) and Professor Donald Fussell, University of
`Texas at Austin.
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`Sunil P. Khatri
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`B. S.
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`
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`Senior project involved implementing graphics algorithms on a MC68000-based
`terminal. Advisor: Professor A Joshi, Indian Institute of Technology, Kanpur, India.
`
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`Research and Professional Experience
`
`
`Texas A&M University, College Station, TX. Associate Professor in Electrical and Computer
`Engineering, 9/2010 – present, Assistant Professor in Electrical and Computer Engineering.
`6/2004 - present. Conducting research on 3 areas. The first is Computer Systems, including
`computer architecture from the circuits up, and algorithm acceleration using GPUs, FPGAs and
`custom ICs. The second is Logic and its applications, while the third area consists of
`Interdisciplinary extensions of the first two.
`
`Sabbatical at U.T. Austin, 7/2011 – 7/2012. I spent my sabbatical at UT Austin, working with
`Prof. Jacob Abraham on several topics such as genomics, sinusoidal signal based data transfer, and
`medical electronics. One paper resulted from this effort, and additional collaboration is being
`pursued.
`
`University of Colorado, Boulder. Assistant Professor, Electrical and Computer Engineering.
`1/2000 – 5/2004. Performed research on VLSI logic design automation, VLSI layout design
`automation, VLSI design methodologies to address Deep Submicron (DSM) issues such as cross-
`talk and power along with interdisciplinary extensions.
`
`University of California, Berkeley. Research Assistant with the CAD group, under
`Professors Robert Brayton and A. Sangiovanni-Vincentelli (8/1993 – 12/1999). Research
`topics included CAD for DSM design, Sets of Pairs of Functions to be Distinguished (SPFDs),
`Binary Decision Diagrams, Engineering Change, Hierarchical Synthesis and Verification, Model
`Matching and Combinational Verification, Timing Analysis in the Presence of Cross-talk and
`Multi-valued Logic Synthesis.
`
`Design Engineer with Motorola's MC88110 RISC and PowerPC 603 microprocessor groups
`in Austin, Texas (8/1989 – 7/1993). Was involved in various design areas from Design for
`Testability to Digital and Analog Circuit Design, along with high-level design.
`
`Independently responsible for the design of the factory test controller for the MC88110. Familiar
`with various ad-hoc and structured test methodologies. Designed digital as well as analog
`circuitry. Designed the MC88110's input / output buffers and clock PLL logic. Performed all
`attendant tasks in a "vertical" VLSI design methodology, including high-level modeling, layout
`design and verification, as well as global and detailed routing.
`
`During my years at Motorola, I had definite plans to pursue an academic career. As a result, I
`intentionally attempted to get an understanding of as many tasks as possible in an entire VLSI
`design flow, to make for a more rich research base in my future as an academic researcher.
`
`University of Texas, Austin. Researcher with Professor M. Ray Mercer's group (8/1988 -
`7/1993). Research topics included IC testing and Boolean function representation using Canonical
`XOR-based circuit decompositions.
`
`University of Texas, Austin. Researcher with Professor Donald Fussell's group (8/1987 –
`7/1989). Research areas included Computer Architecture and Memory Interface design, applied in
`the context of the METRIC multi-threaded RISC microprocessor, which Professor Fussell was
`developing.
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`Research Interests
`
`
`My research interests are broadly divided into 3 areas listed below. Each area has representative
`topics listed alongside the heading.
`
`• Computer Systems: My work in Computer Systems is divided into 2 categories: 1) VLSI
`circuits and computer architecture (including the design of efficient NoCs using a resonant
`clocking as well as a superposition-of-sinusoids paradigm, special function units for
`comparison, hashing, Boolean Satisfiability and sorting, low energy and low power design
`using sub-threshold circuits, high-speed circuit design, system prototyping, specialized
`architectures for radiation tolerance/detection, as well as circuit and architectural approaches
`for resilience, crosstalk avoidance, clocking, leakage reduction and testability). My group also
`develops system prototypes to validate our ideas – for example, in extreme low power/energy
`computation, architectures for cryptography and FPGA based architectures for Boolean
`Satisfiability, and 2) Algorithm acceleration (using GPUs, FPGAs, map-reduce clusters and
`custom ICs), for algorithms in the VLSI CAD (for fault simulation, logic simulation, circuit
`simulation, fault table generation, SAT) domain.
`• Logic Synthesis and Algorithms for VLSI Design: In this area, my work initially started in
`the space of logic synthesis for VLSI CAD. In the last few years, I have directed this work
`toward genomics (predictor inference, Gene Regulatory Network (GRN) construction,
`determining optimal drug regime for a genetic disease, gene sequencing and alignment), noise
`based logics and their realization, and fast Boolean Satisfiability solvers (using GPUs,
`FPGAs, map-reduce clusters and custom IC based accelerators).
`Interdisciplinary extensions: The above two areas form a spring-board from which I engage
`in research in other domains. I explore extensions of the above two areas to other areas such
`as IP routing (routing table compression, architecture and circuit design of Ternary CAMs),
`Digital Signal Processing (architectures and designs for FFT, FPGA and GPU based radar
`signal processors), optical networking (SAT based Routing and Wavelength Assignment for
`DWDM optical networks), wireless communication (MIMO decoders, WiMAX decoders)
`and coding (LDPC decoders, fix-free code generators), satellite tracking and cryptography.
`
`Some of my current research projects (which are yet unpublished) include an interdisciplinary
`project (with Dr. Suman Chakravorty (Aerospace, TAMU)) in which we are accelerating a
`receding horizon control method to track satellites, a method to help IC debug by sampling
`the power supply grid on the fly, a combined hardware and software programming language,
`a fast map-reduce based implementation of a Boolean Satisfiability (SAT) solver, an
`asynchronous, low leakage power Network-on-Chip router, several methods to accelerate
`gene sequencing and alignment, a method to detect coincident events in radiation detection
`when multiple detectors are deployed (this will be fabricated in a near-threshold IC in the next
`year), a fast superposition-of-sinusoids approach to deliver very high speed data across ICs on
`a circuit board, and a new highly efficient circuit design approach that uses flash transistors
`(which have historically been used only for memory).
`
`•
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`Conventions used:
`
` •
`
` For all publications, the names of past or present, graduate or undergraduate student co-
`authors (who were advised by me or had no advisor at the time of publication) are
`underlined. The students with no advisor at the time of publication were students who
`took my graduate course, and we decided to publish their class project.
`
`
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`Publications
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`Sunil P. Khatri
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`• The names of past or present co-authors who were graduate students at the time of
`publication (and were not advised by me) are indicated in underlined italics. Such
`students are the students of colleagues with whom I collaborated after becoming a faculty
`member, or peer students with whom I collaborated while I was a graduate student.
`• All publications listed (other than invited papers) are peer reviewed.
`•
`I have first listed books/book chapters, followed by conference tutorials presented,
`invited papers or panels, journal papers, conference papers, workshop papers and patents.
`Accepted items and items which are under review are listed under separate headings.
`Items under review are not included in the paper count totals.
`Invited papers are listed under “Conference Papers” and “Workshop Papers”, and also
`under a separate heading for distinguishability.
`In a handful of cases, page numbers are not available.
`
`•
`•
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`•
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`Books or Book Chapters Published:
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`"A Sum-Of-Product Based Multiplication Approach For FIR Filters And DFT", Kumar, Khatri.
`Monograph published by LAP LAMBERT Academic Publishing. 1st edition, January 2014. 64p.
`ISBN 978-3-8484-8636-6.
`
`"Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling",
`Mandal, Khatri, Mahapatra. Monograph published by Springer Publishers. 1st edition November
`2013. 160p. ISBN 978-1-4614-9404-1.
`
`"Logic Synthesis for Genetic Diseases: Modeling Disease Behavior Using Boolean Networks",
`Lin, Khatri. Monograph published by Springer Publishers. 1st edition, November 2013. 140p.
`ISBN 978-1-4614-9428-7.
`
`"Practical & Real Time IP Routing Table Compression - Extending algorithms from digital logic
`synthesis". Bollapalli, Khatri. Published by LAP Lambert Academic Publishing, January 2012.
`68p. ISBN 978-3847321521.
`
`“Advanced Techniques in Logic Synthesis, Optimizations and Applications”, Khatri, Gulati,
`editors. Springer Publishers, 1st ed, 2011. 240p. ISBN 978-1-4419-7517-1.
`
`“Robust Window-Based Multi-node Minimization Technique Using Boolean Relations”, Cobb,
`Gulati, Khatri. pp 309-333, In “Advanced Techniques in Logic Synthesis Optimizations and
`Applications”, Khatri, Gulati, ed. Springer Publishers.
`
`“Digital Logic Using Non-DC Signals” Bollapalli, Khatri, Kish. pp 383-400. In “Advanced
`Techniques in Logic Synthesis Optimizations and Applications”, Khatri, Gulati, ed. Springer
`Publishers 2011. ISBN 978-1-4419-7517-1.
`
`“On and Off-chip Cross-talk Avoidance in VLSI Designs”, Duan, LaMeres, Khatri. Monograph
`published by Springer Publishers. 1st edition, 2010. 240p. ISBN 978-1-4419-0946-6.
`
`“EDA Algorithm Acceleration with FPGAs, GPUs, and Custom ICs”, Gulati, Khatri. Monograph
`published by Springer Publishers. 1st edition, 2010. 194p. ISBN 978-1-4419-0943-5.
`
`“Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations”,
`Garg, Khatri. Monograph published by Springer Publishers. 1st edition, 2010. 212p. ISBN 978-1-
`4419-0930-5.
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`“Minimizing and Exploiting Leakage in VLSI Design”, Jayakumar, Paul, Garg, Khatri.
`Monograph published by Springer Publishers. 1st edition, 2010. 214p. ISBN 978-1-4419-0949-7.
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`Invited chapter "Logic Synthesis" in the CRC EDA handbook “EDA for IC Implementation,
`Circuit Design and Process Technology”. Editors L. Lavagno, L. Scheffer, G. Martin. ISBN
`0849379245, 9780849379246, 571pp, published 2006. Chapter co-authored by Narendra Shenoy
`of Synopsys Inc. The Wikipedia entry on “Logic Synthesis” is based on the material in this
`chapter.
`
`"Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics", Khatri, Brayton,
`Sangiovanni-Vincentelli. Research Monograph published by Kluwer Academic Publishers. ISBN
`# 0-7923-7407-X.
`
`Book Contracts or Chapter Invitations:
`
`“Metastability Reduction on Asynchronous Circuits”, Sharma. Khatri. Contract for this research
`manuscript being pursued through LAP LAMBERT publishers, 2016.
`
`“VLSI Design from the Middle Out” Khatri, Gerosa. Contract for this electronic textbook on VLSI
`design approved by Springer Publishers. This book is expected to be published in 2014.
`
`Invited chapter “A GPU-based Implementation of a Receding Horizon Sensor Tracking
`Methodology”, Abusultan, Chakravorty, Khatri. Invited to publish as a chapter in the Elsevier
`book “Advances in GPU Research and Practice”, H. Sarbazi-Azad (Editor).
`
`Invited chapter “GPU-based Algorithms in Electronic Design Automation”, Gulati, Khatri,
`Croix. Invited to publish as a chapter in the Elsevier book “Advances in GPU Research and
`Practice”, H. Sarbazi-Azad (Editor).
`
`Conference Tutorials Presented:
`
`"Introduction to GPU Programming for EDA", Croix, Khatri. This tutorial was presented at the
`International Conference on Computer-Aided Design (ICCAD), San Jose, CA. November 2-5,
`2009.
`
`"Structured ASIC Design Approaches and Trends", Technical Forum, DesignCon East, Worcester,
`MA. September 19-21, 2005.
`
`Conference Panel Invitations:
`
`“Stochastic and Approximate Computing”. Invited to serve on a panel at the IEEE/ACM
`International Conference on Computer-Aided Design (ICCAD), 2016, Austin TX.
`
`“Looking Beyond Moore’s Law”, Invited to serve on a panel at the IEEE Texas Workshop on
`Integrated System Integration (TexasWISE) 2016, Houston, TX.
`
`"Models and High-Speed Simulation”. Invited to Chair a Panel Session to discuss this topic, at the
`15th ACM/IEEE System Level Interconnect Prediction (SLIP) Workshop 2013, Austin, TX. June
`2, 2013.
`
`“Multi-core and GPU based Parallelism”. Invited to serve as a panelist to discuss this topic,
`along with leading academic and industry practitioners in this area. The panel was part of the
`IEEE CTS CAS/SSC/CEDA Workshop on Data Parallelism for Multi-core Chips and GPUs”,
`Austin, TX. October 5, 2012. My talk was titled "Algorithm Acceleration for GPU Architectures".
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`“Manycore, Heterogenous, or Neither: Which One is the Way to Go for EDA?”. Invited to serve
`as a panelist to discuss this topic, along with other leading researchers in the field of GPU based
`implementation of EDA algorithms. The panel was part of the IEEE/ACM International
`Conference on Computer-Aided Design (ICCAD), San Jose, CA. November 7-10, 2011.
`
` “The Top of Testing’s Most Wanted List – What is the most critical Testing challenge? (or have
`all the bad guys been caught already?)”, invited panelist (along with Jason Doege, T.M. Mak,
`Rob Dassch, Tom Williams and Luis Basto, some leading researchers in VLSI testing). This panel
`was part of the International Test Synthesis Workshop (ITSW) 2007, San Antonio, TX. March 5-
`7, 2007.
`
` “Are we Fighting a Losing Battle, Dealing with Numerous and Complex Defects?”, invited to
`serve as a panelist along with 3 leaders in the field. Peer panelists were Dr. Tom Williams
`(Synopsys), Prof. Melvin Bruer (USC), and Al Crouch (Inovys Corporation). The panel was part
`of the International Test Synthesis Workshop (ITSW) 2006, Santa Barbara, CA. April 9-12, 2006.
`
`Invited Papers, Book Chapters and Talks:
`Note: These papers are re-listed along with regular papers in a later section. They are
`separately listed here for ease of perusal.
`
`Invited chapter “A GPU-based Implementation of a Receding Horizon Sensor Tracking
`Methodology”, Abusultan, Chakravorty, Khatri. Invited to publish as a chapter in the Elsevier
`book “Advances in GPU Research and Practice”, H. Sarbazi-Azad (Editor).
`
`Invited chapter “GPU-based Algorithms in Electronic Design Automation”, Gulati, Khatri,
`Croix. Invited to publish as a chapter in the Elsevier book “Advances in GPU Research and
`Practice”, H. Sarbazi-Azad (Editor).
`
`Invited paper, "Information, noise and energy dissipation: Laws, limits and applications", Kish,
`Granqvist, Khatri, Sundqvist, Peper Plenary talk at International Workshop on Molecular
`Architectonics, Shiretoko, Hokkaido, Japan, August 3-6, 2015.
`
`Invited paper ""Demonic" challenge: Landauer's erasure-dissipation" Kish, Granqvist, Khatri.
`44th Winter Colloquium on the Physics of Quantum Electronics (PQE) 2014, Snowbird, UT.
`January 5-9, 2014.
`
`Invited paper "Demons: Maxwell demon; Szilard engine; and Landauer's erasure-dissipation",
`Kish, Granqvist, Khatri, Wen. Hot Topic of Physical Informatics (HoTPI) 2013, November 10-13,
`Changsha, China. November 10-13, 2013.
`
`Invited paper, "Using GPUs to Accelerate CAD Algorithms", Croix, Gulati, Khatri. IEEE Design
`& Test, Vol. 30, Issue 1. February 2013, pp 8-16.
`
`Invited paper, "Algorithm Acceleration for GPU Architectures", IEEE CTS CAS/SSC/CEDA
`Workshop on Data Parallelism for Multi-Core Chips and GPUs, Austin, TX. October 5, 2012.
`
`Invited paper, "Application of logic synthesis to the understanding and cure of genetic diseases",
`Lin, Khatri. IEEE/ACM Design Automation Conference (DAC) 2012, San Francisco, CA. June 3-
`7, 2012, pp 734-740.
`
`Invited paper, “Noise-based Information Processing”, Kish, Khatri, Bezrukov, Peper, Gingl,
`Horváth. 21st International Conference on Noise and Fluctuations. June 12-16 2011, Toronto,
`Canada. June 12-16, 2011, pp 28-33.
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`Invited paper "DFM-Aware Structured ASIC Design", Gopalani, Garg, Khatri. International
`Symposium on Integrated Circuits (ISIC) 2009, Singapore. December 14-16, 2009, pp 29-32.
`
`Invited paper "A PTL based Highly Testable Structured ASIC Design Approach", Gulati,
`Jayakumar, Khatri. International Symposium on Integrated Circuits (ISIC) 2009, Singapore.
`December 14-16, 2009, pp 33-36.
`
`Invited paper “Highly Parallel Decoding of Space-Time Codes on Graphics Processing Units”,
`Bollapalli, Wu, Gulati, Khatri, Calderbank. Annual Allerton Conference on Communication,
`Control and Computing, 2009, Urbana, IL. September 30 – October 2, 2009, pp 1262-1269.
`
`Invited paper “Noise-based logic”, Kish, Khatri, Bezrukov, Gingl, Sethuraman. International
`Workshop on Natural Computing (IWNC) 2009, Himeji, Japan. September 23-25, 2009.
`Published by Springer, Eds. F. Peper et al., IWNC 2009, PICT 2, pp 13–22, 2010.
`
`Invited paper "Extreme Low Power Computing using Sub-threshold Circuits", Segundo Magno
`Congreso Interancional del CIC 2007, Mexico City, Mexico. November 6-8, 2007.
`
`Invited chapter "Logic Synthesis" in the CRC EDA handbook “EDA for IC Implementation,
`Circuit Design and Process Technology”. Editors L. Lavagno, L. Scheffer, G. Martin. ISBN
`0849379245, 9780849379246, 571pp, published 2006. Chapter co-authored by Narendra Shenoy
`of Synopsys Inc. The Wikipedia entry on “Logic Synthesis” is based on the material in this
`chapter.
`
`Invited paper "A Routing Technique for Structured Designs which Exploits Regularity". Khatri,
`Das. VLSI Design and Test Workshop (VDAT-2001), August 2001.
`
`Invited paper "Multi-valued Logic Synthesis"- Brayton, Khatri. 12th International Conference on
`VLSI Design (VLSI-99), Goa, India. 1999, pp 196-205.
`
`Peer-reviewed Journal Publications:
`
`"A Survey of Software and Hardware Approaches to Performing Read Alignment in Next
`Generation Sequencing", Al-Kawam, Khatri, Datta. Accepted at the IEEE/ACM Transactions on
`Computational Biology and Bioinformatics, June 2016. To appear.
`
`"FTCAM: An Area-Efficient Flash-Based Ternary CAM Design", Fedorov, Abusultan, Khatri.
`IEEE Transactions on Computers. Vol 65, issue 8, pp 2652-2658, Aug 2016.
`
`"Response to “Comment on ‘Zero and negative energy dissipation at information-theoretic
`erasure’”, Kish, Granqvist, Khatri, Peper. Accepted for publication in Journal of Computational
`Electronics. Vol 15, Issue 1, pp 343-346. Mar 2016.
`
`"Zero and negative energy dissipation at information theoretic erasure", Kish, Granqvist, Khatri,
`Peper. Journal of Computational Electronics, 15(1), pp 335-339, Mar 2016.
`
`"Demons: Maxwell’s Demon, Szilard’s Engine and Landauer’s Erasure-dissipation”, Kish,
`Granqvist, Khatri, Wen. International Journal of Modern Physics: Conference Series 33 (2014)
`1460364-1 to 1460364-5.
`
`"List Mode with the ORTEC digiBASE-E", Hearn, Marianno, Khatri, Gypp. In Health Physics:
`The Radiation Safety Journal, Vol. 106, Issue 2, February 2014, pp S12-S15.
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`Invited paper, "Using GPUs to Accelerate CAD Algorithms", Croix, Gulati, Khatri. IEEE Design
`& Test, Vol. 30, Issue 1. February 2013, pp 8-16.
`
`"On Optimal and Achievable Fix-Free Codes", Savari, Yazdi, Abedini, Khatri. IEEE Transactions
`on Information Theory 58(8): 5112-5129, 2012.
`
`"Application of Max-SAT-based ATPG to optimal cancer therapy design", Lin, Khatri. BMC
`Genomics 2012, 13 (Suppl 6):S5, 26 October, 2012.
`
`“A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications”, Turker, Khatri,
`Sanchez-Sinencio. IEEE Transactions On Circuits and Systems – I, Vol. 58, No. 6, June 2011, pp
`1225-1238.
`
`“Computation using Noise-based Logic: Efficient String Verification over a Slow Communication
`Channel”, Kish, Khatri, Horvath. European Journal of Physics B 79, January 2011, pp 85-90.
`
`"Noise-based deterministic logic and computing: a brief survey", Kish, Khatri, Bezrukov, Peper,
`Gingl, Horvath. International Journal of Unconventional Computing 7, February 2011, pp 101-
`113.
`
`“A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage
`with Zero Delay Penalty”, Jayakumar, Khatri. ACM Transactions on Design Automation of
`Electronic Systems, 2010.
`
`"Towards brain-inspired computing", Gingl, Khatri, Kish. Fluctuation and Noise Letters 9,
`December 2010, pp 403–412.
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`"Instantaneous noise-based logic", Kish, Khatri, Peper. Fluctuation and Noise Letters 9,
`December 2010, pp 323–330.
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`"Fault Table Computation on GPUs", Gulati, Khatri. Journal of Electronic Testing: Theory and
`Applications (JETTA). Vol. 26, No. 2, April 2010, pp 195-209.
`
`"Selective Forward Body Bias for High Speed and Low Power SRAMs", Bollapalli, Garg, Gulati,
`Khatri. Accepted for publication at the Journal of Low Power Electronics (JOLPE), Vol. 5, No. 2,
`August 2009.
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`"Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization", Ekambavanan,
`Garg, Khatri, Narayanan. Accepted for publication at the Journal of Low Power Electronics
`(JOLPE), Vol. 5, No. 2, August 2009, pp 157-172.
`
`"Noise-based Logic Hyperspace with the Superposition of 2N States in a Single Wire". Kish,
`Khatri, Sethuraman. Physics Letters A. Vol. 373, No. 22, May 2009, pp 1928-1934.
`
`"Circuit-level Design Approaches for Radiation-hard Digital Electronics", Garg, Jayakumar,
`Khatri, Choi. IEEE Transactions on Very Large Scale Integration Systems, Vol. 17, No. 6, June
`2009, pp 781-792.
`
`"Efficient On-Chip Crosstalk Avoidance CODEC Design", Duan, Cordero, Khatri. IEEE
`Transactions on Very Large Scale Integration Systems, Vol. 17, No. 4, April 2009, pp 551-560.
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`"FPGA-Based Hardware Acceleration for Boolean Satisfiability", Gulati, Paul, Khatri, Patil, Jas.
`ACM Transactions on Design Automation of Electronic Systems (TODAES). Vol. 14, No. 2, March
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`Sunil P. Khatri
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`2009. Among the top 10 downloaded papers for the journal in 2010. Nominated for best paper
`for the journal, 2010.
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`for Approximate, Efficient Logarithm and Antilogarithm
`"A Fast Hardware Approach
`Computations", Paul, Jayakumar, Khatri. IEEE Transactions on Very Large Scale Integration
`Systems, Vol. 17, No. 2, February 2009, pp 269-277.
`
`"A Dynamically De-skewable Clock Distribution Methodology", Jayakumar, Kapoor, Khatri.
`IEEE Transactions on Very Large Scale Integration (TVLSI), Vol. 16, No. 9, September 2008, pp
`1220-1229.
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`"Resource Sharing among Mutually Exclusive Sum-of-Product Blocks for Area Reduction", Das,
`Khatri. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, No.
`3, July 2008, pp 51:1-51:7.
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`“Efficient, Scalable Hardware Engine for Boolean Satisfiability and Unsatisfiable Core
`Extraction”, Gulati, Waghmode, Khatri, Shi. IET Computers and Digital Techniques, Vol. 2, No.
`3, May 2008, pp 214-229.
`
`"A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs in
`the Presence of Random PVT Variations", Gulati, Jayakumar, Khatri, Walker. Integration, the
`VLSI Journal, Vol. 41, No. 3, May 2008, pp 399-412.
`
`"SAT-based ATPG using Multi-level Compatible Don't-Cares", Gulati, Saluja, Khatri. ACM
`Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, No. 2, April
`2008, pp 24:1-24:18.
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`"A Novel Hybrid Parallel-Prefix Adder Architecture with Efficient Timing-Area Characteristic",
`Das, Khatri. IEEE Transactions on Very Large Scale Integration, Vol. 16, No. 3, March 2008, pp
`326-331.
`
`"A Timing-Driven Approach to Synthesize Fast Barrel Shifters", Das, Khatri. IEEE Transactions
`on Circuits and Systems II (TCAS-II), Vol. 55, No. 1, January 2008, pp 31-35.
`
`"Polymer Sensors to Monitor Roach Locomotion", Lee, Cooper, Mika, Clayton, Garg, Gonzalez,
`Vinson, Khatri, Liang. IEEE Sensors Journal, Vol. 7, No. 12, December 2007, pp 1698-1702.
`
`"High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction
`Problems". Nagarajan, Laendner, Jayakumar, Milenkovic, Khatri. Springer Journal of VLSI
`Signal Processing, Vol. 49, No. 1, October 2007, pp 185-206.
`
`"A Predictably Low Leakage ASIC Design Style", Jayakumar, Khatri. IEEE Transactions on Very
`Large Scale Integration, Vol. 15, No. 3, March 2007, pp 276-285.
`
`"SPFD-based Wire Removal in Standard-cell and Network-of-PLA Circuits"- Khatri, Sinha,
`Brayton, Sangiovanni-Vincentelli. IEEE Transactions on Computer-Aided Design of Circuits and
`Systems, Vol. 23, No. 7, June 2004, pp 1020-1030.
`
`"An Efficient and Regular Routing Methodology for Datapath Designs Using Net Regularity
`Extraction". Das, Khatri. Short paper, IEEE Transactions on CAD, Vol. 21, Number 1. Special
`issue on Physical Design, January 2002, pp 93-101.
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`Peer-reviewed Journal Submissions Under Review:
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`Sunil P. Khatri
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`Page 10 of 47
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`Limestone Memory Systems, LLC – Exhibit 2005,