UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`APPLE, INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS, LLC,
`Patent Owner.
`____________________
`
`Case IPR2016-01561
`Patent 6,233,181
`____________________
`
`DECLARATION OF SUNIL P. KHATRI, Ph.D.
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 1
`
`

`

`TABLE OF CONTENTS
`
`Page
`
`Introduction ...........................................................................................1
`I.
`Background and Qualifications .............................................................2
`II.
`III. Materials Considered .............................................................................9
`IV. Applicable Legal Standards ................................................................ 11
`V.
`Person Of Ordinary Skill In The Art .................................................. 14
`VI. Overview Of The Relevant Technology ............................................ 16
`VII. Overview Of The ’181 Patent ............................................................ 28
`VIII. Overview of Sukegawa ....................................................................... 36
`IX. Overview of Fujishima ....................................................................... 43
`X. Overview of Walck ............................................................................. 54
`XI. Claim 3 Of The ’181 Patent Claims Is Not Obvious Over
`Sukegawa In View Of Fujishima ....................................................... 58
`A. Claim 3 Requires More Than A Mere Shared Sense
`Amplifier Design ...................................................................... 61
`B. A Person Having Ordinary Skill In The Art Would Not
`Necessarily Look To Combine Sukegawa With
`Fujishima, Because They Attempt To Solve Separate
`Problems ................................................................................... 64
`C. The Teachings Of Sukegawa And Fujishima Would Not
`Motivate A Person Having Ordinary Skill In The Art To
`Arrive At The Claimed Memory Device ................................. 66
`1.
`The Person Having Ordinary Skill In The Art
`Balances Numerous Factors When Implementing
`New DRAM Designs ................................................ 66
`Fujishima Does Not Teach Any Advantage Of
`The “Alternate Arrangement Shared Sense
`Amplifier” Design .................................................... 68
`Sukegawa Disfavors The ANY TO ANY
`Redundancy Scheme ................................................. 69
`
`3.
`
`2.
`
`i
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 2
`
`

`

`4.
`
`3.
`
`4.
`
`5.
`
`6.
`
`2.
`
`Fujishima’s Alternate Arrangement Shared Sense
`Amplifier Design Was Understood To Be
`Incompatible With Sukegawa’s ANY TO ANY
`Redundancy Scheme ................................................. 70
`D. Ancillary References Would Not Motivate The Person
`Having Ordinary Skill In The Art To Combine
`Sukegawa and Fujishima.......................................................... 74
`1.
`The Horiguchi IEEE Article Teaches Away From
`The Proposed Combination ...................................... 74
`The Arimoto IEEE Article Would Not Suggest
`Proposed Combination ............................................. 76
`U.S. Patent No. 5,687,123 (“Hidaka”) Would
`Not Suggest The Proposed Combination ................. 78
`U.S. Patent No. 5,726,946 (“Yamagata”) Would
`Not Suggest The Proposed Combination ................. 78
`U.S. Patent No. 6,003,148 (“Yamauchi”) Would
`Not Suggest The Proposed Combination ................. 79
`U.S. Patent No. 6,075,743 (“Barth”) Would Not
`Suggest The Proposed Combination ........................ 80
`U.S. Patent No. 5,956,285 (“Watanabe”) Would
`Not Suggest The Proposed Combination ................. 80
`The 1997 Horiguchi IEEE Article Would Not
`Suggest The Proposed Combination ........................ 81
`Dr. Mazumder’s Book, Published In 2002,
`Teaches Away From The Proposed Combination .... 83
`XII. Claim 5 of the ‘181 Patent Is Not Obvious Over Sukegawa In
`View of Fujishima And Walck ........................................................... 84
`A. Claim 5 Requires Two Memory Arrays, And Control
`Circuitry For Driving Memory Blocks Into A Selected
`State .......................................................................................... 85
`B. Walck Does Not Disclose The Claimed Control Circuitry
`For Driving Memory Blocks Into A Selected State ................. 86
`
`7.
`
`8.
`
`9.
`
`ii
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 3
`
`

`

`C. The Teachings Of Sukegawa, Fujishima, And Walck Would
`Not Motivate A Person Having Ordinary Skill In The Art
`To Arrive At The Claimed Memory Device ............................ 89
`XIII. Conclusion .......................................................................................... 90
`
`
`iii
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 4
`
`

`

`I.
`
`Introduction
`
`I, Sunil P. Khatri, declare as follows:
`
`1.
`
`I have been retained on behalf of Limestone Memory Systems, LLC
`
`(“LMS”), and its counsel, Fitch Even Tabin & Flannery LLP, as an expert in this
`
`proceeding. I am personally knowledgeable about the matters stated herein and am
`
`competent to make this declaration.
`
`2.
`
`I understand that Petitioners filed a Petition for inter partes review
`
`regarding certain claims of United States Patent No. 6,233,181 (“the ’181 patent”),
`
`which was accompanied by the Declaration of Pinaki Mazumder In Support Of
`
`Petition For inter partes review. I am aware that, after LMS submitted its
`
`Preliminary Response, the Patent Trial & Appeal Board (“Board”) issued a Decision
`
`on February 17, 2017 instituting trial as to claims 3 and 5. I understand that the trial
`
`will address issues of alleged unpatentability under 35 U.S.C. § 103(a), including
`
`the alleged unpatentability of claim 3 over U.S. Patent No. 5,487,040 to Sukegawa
`
`et al. (Ex. 1005) (“Sukegawa”) in view of U.S. Patent No. 5,267,214 to Fujishima et
`
`al. (Ex. 1006) (“Fujishima”), and the alleged unpatentability of claim 5 over
`
`Sukegawa in view of Fujishima and U.S. Patent No. 4,967,397 to Walck (Ex. 1007)
`
`(“Walck”).
`
`3.
`
`I have been asked to analyze the patentability of claims 3 and 5 in view
`
`of the art cited in the Petition, and to provide my conclusions and bases thereof
`1
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 5
`
`

`

`regarding several aspects of the issues in dispute. Based on my investigation in this
`
`matter, I conclude that claim 3 of the ’181 patent is patentable over Sukegawa in
`
`view of Fujishima and that claim 5 of the ’181 patent is patentable of Sukegawa in
`
`view of Fujishima and Walck.
`
`4.
`
`The analysis in this declaration is exemplary. Additional reasons may
`
`support the validity of claims 3 and 5, but they do not form part of my current
`
`analysis. The fact that I do not address a particular reason does not imply that I would
`
`agree or disagree with such additional reason.
`
`5.
`
`I receive compensation at my standard hourly rate of $450 per hour for
`
`my time working on this matter, plus expenses. I have no financial interest in LMS
`
`or in the ’181 patent, and my compensation is not dependent on the outcome of this
`
`trial or any of the related district court proceedings involving the ’181 patent. The
`
`conclusions I present reflect my own judgment, based on my experience in the field
`
`and the contents of the documents cited herein.
`
`II. Background and Qualifications
`6.
`The paragraphs below present my qualifications as an expert in the field
`
`of semiconductor design, testing and CAD, including memory devices and
`
`specifically including dynamic random access memory (DRAM) devices and
`
`redundancy schemes relevant to the subject matter of the ’181 patent, which
`
`describes a semiconductor memory device with improved flexible redundancy
`2
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 6
`
`

`

`scheme. A copy of my latest curriculum vitae (CV) is included herewith as Ex. 2005
`
`and provides further details regarding my background and qualifications.
`
`7.
`
`I have over thirty-four years of experience with electronics, electrical
`
`engineering, and computer engineering. Over this time, I have acquired extensive
`
`knowledge and experience with VLSI circuits, computer architecture, test,
`
`computer-aided design (CAD) algorithms and algorithm acceleration, logic
`
`synthesis, semiconductor memory, redundancy, clock synchronous circuits, and
`
`related software and hardware topics. Most relevant to the ’181 patent, my technical
`
`expertise includes extensive work with semiconductor memory, including burst
`
`transfers, redundancy, EEPROM (and flash) and clocking and source synchronous
`
`design.
`
`8.
`
`I earned my Bachelor of Science in Electrical Engineering in 1987 from
`
`the Indian Institute of Technology, Kanpur, India. After graduating with my B.S.
`
`degree, I was a candidate for a Master of Science degree in Electrical and Computer
`
`Engineering at the University of Texas from 1987–89. At the University of Texas, I
`
`held the Microelectronics and Computer Development (MCD) Fellowship from
`
`1987–89. I also conducted my M.S. research and wrote my thesis on the design of
`
`the METRIC memory interface and memory system. METRIC was one of the first
`
`super-scalar processors that was developed in the world.
`
`3
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 7
`
`

`

`9.
`
`After leaving the University of Texas, I worked at Motorola Inc. from
`
`1989–93 as a design engineer for reduced instruction set computing (RISC)
`
`microprocessors. My duties included the design of digital and analog circuitry, test
`
`logic and circuits, JTAG boundary scan design, input/output driver design, and clock
`
`phase-locked loop (PLL) logic. During my time at Motorola, I was independently
`
`responsible for the design of the factory test controller of the MC88110
`
`microprocessor. I performed all attendant tasks in a “vertical” VLSI design
`
`methodology, which included high-level modeling, layout design and verification,
`
`as well as global and detailed routing. I also helped in the design of the Translation
`
`Lookaside Buffer (TLB) unit, which included a static random-access memory
`
`(SRAM) block.
`
`10.
`
`In 1999, I earned a Doctor of Philosophy degree in Electrical
`
`Engineering and Computer Sciences from the University of California, Berkeley.
`
`While at Berkeley, I held the California Microelectronics (MICRO) Fellowship in
`
`1993.
`
`11.
`
`I joined the faculty at the University of Colorado, Boulder, in 2000 as
`
`an Assistant Professor of Electrical and Computer Engineering. At the University
`
`of Colorado my research focused on VLSI logic design automation, VLSI layout
`
`design automation, and VLSI design methodologies to address Deep Submicron
`
`(DSM) issues such as crosstalk and power.
`4
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 8
`
`

`

`12.
`
`I joined the faculty at Texas A&M University in 2004 as an Assistant
`
`Professor in Electrical and Computer Engineering. In 2010 I was promoted to
`
`Associate Professor in Electrical and Computer Engineering. In 2015, I was
`
`promoted to full Professor in Electrical and Computer Engineering. My research
`
`focuses on three primary areas: the first is computer systems, including computer
`
`architecture from the circuits up, and algorithm acceleration using GPUs, FPGAs
`
`and custom ICs. The second is logic and its applications, while the third area
`
`consists of interdisciplinary extensions of the first two.
`
`13. At Texas A&M I teach classes that cover memories extensively,
`
`featuring thorough discussion of sense amplifiers and different types of memory
`
`circuits. For example, in “Advances in VLSI Circuit Design,” a graduate level
`
`course, I cover all aspects of VLSI design, including memories and sense amplifiers;
`
`in “Microprocessor System Design,” a senior level course, I cover memories, and
`
`design techniques that can be used to optimize them; and in “Digital Circuit
`
`Design,” a senior level course, I cover circuit design techniques for memory,
`
`including sense amplifiers, in detail. I am also currently working with a student on
`
`research involving secure erasure of flash-based memory using beta radiation. Also,
`
`the Ph.D. thesis of my most recent doctoral student dealt with the use of flash
`
`transistors to design logic circuits. Further, I am working with one of my students
`
`on research in a new way of implementing DRAM memory, which will be
`5
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 9
`
`

`

`submitted for publication soon.
`
`14. Since 2000, I have earned 24 research contracts from funders including
`
`Intel, the National Science Foundation, the National Security Agency, Altera
`
`Corporation,
`
`the National Center
`
`for Atmospheric Research, National
`
`Semiconductor Corporation, and several private sources. The total amount for these
`
`research grants is $12.83 million, of which my portion is $2.17 million.
`
`15. Since 2003, I have published 211 research monographs, journal papers,
`
`and conference papers on memory systems, redundancy, timing circuits, clocking
`
`and source synchronous design. A few papers on relevant subject areas authored or
`
`co-authored by me include:
`
`• Selective Forward Body Bias for High Speed and Low Power SRAMs,
`
`Journal of Low Power Electronics, Vol. 5, No. 2, Aug. 2009, pp. 185-
`
`95;
`
`• Low Power and High Performance SRAM Design using Bank-based
`
`Selective Forward Body Bias, IEEE/ACM Great Lakes Symposium on
`
`VLSI, May 10-12, 2009, Boston, MA, pp. 441-44;
`
`
`1 Two additional peer-reviewed journal submissions are currently under review.
`6
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 10
`
`

`

`• Modeling Dynamic Stability of SRAMs in the Presence of Single Event
`
`Upsets (SEUs), IEEE International Symposium on Circuits and
`
`Systems, May 18-21, 2008, Seattle, WA, pp. 1788-91;
`
`• FTCAM: An Area-efficient Flash-based Ternary CAM Design, IEEE
`
`Transactions on Computers, Vol. 65, No. 8, Aug. 2016, pp. 2652-58;
`
`• An Area-efficient Ternary CAM Design Using Floating Gate
`
`Transistors, IEEE International Conference on Computer Design, Oct.
`
`19-22, 2014, Seoul, S. Kor., pp. 55-60; and
`
`• A Fast Ternary CAM Design for IP Networking Applications,
`
`International Conference on Computer Communications and Networks,
`
`October 22, 2003, Dallas, TX, pp. 434-39 (awarded best paper).
`
`16.
`
`I have served as an editor for IEEE Transactions on Computers, ACM
`
`Transactions on Design Automation of Electronic Systems, and MDPI Journal of
`
`Electronics.
`
`17.
`
`I am generally familiar with the analysis of patents. I am the inventor
`
`of the following U.S. Patents:
`
`• Data Processing System Having Serial Self Address Decoding and
`
`Method of Operation, United States Patent No. 5,347,523, issued
`
`September 13, 1994;
`
`7
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 11
`
`

`

`• Circuit Identifier for Use with Focused Ion Beam Equipment, United
`
`States Patent No. 5,408,131, issued April 18, 1995 (“the ‘131 patent”);
`
`• Driver Circuit with Self-Adjusting Impedance Matching, United States
`
`Patent No. 5,448,182, issued September 5, 1995 (“the ‘182 patent”);
`
`• Circuit Identifier for Use with Focused Ion Beam Equipment, United
`
`States Patent No. 6,156,579, issued December 5, 2000 (“the ‘579
`
`patent);
`
`• Datapath Design Methodology and Routing Apparatus, United States
`
`Patent No. 6,598,215, issued July 22, 2003;
`
`• Low Power Reconfigurable Circuits with Delay Compensation, United
`
`States Patent No. 7,880,505, issued February 1, 2011.
`
`18. The ’131 and ’579 patents are directed to an identification means for
`
`redundant circuits that distinguishes said circuits by respective function. This allows
`
`for identification by ion beam equipment, which can then repair, replace, or
`
`supplement circuits as necessary. These patents disclose a scheme for replacing
`
`defective cells or circuits within a larger unit.
`
`19. The ’182 patent relates to a driver circuit capable of switching from one
`
`driver portion to a second in response to the output signal of the first portion reaching
`
`8
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 12
`
`

`

`a predetermined voltage. It discloses a driver circuit capable of adjusting circuit
`
`configurations upon a designated output state.
`
`20. The ’181 patent concerns a semiconductor device with a spare array of
`
`memory cells for providing an improved flexible redundancy scheme for DRAMs. I
`
`recognize this technology as being well within the sphere of my experience and
`
`expertise, and I understand the technology described in the ’181 patent fully. My
`
`experience and education in this industry qualify me to explain this technology and
`
`to address the issues of patent validity from the perspective of a person of ordinary
`
`skill in the art.
`
`III. Materials Considered
`21. The opinions expressed in this declaration are mine and were developed
`
`after studying and considering the ’181 patent (Ex. 1003), its file history (Ex. 1004)
`
`and the following documents:
`
`• U.S. Patent No. 5,487,040 to Sukegawa et al. (Ex. 1005);
`
`• U.S. Patent No. 5,267,214 to Fujishima et al. (Ex. 1006);
`
`• U.S. Patent No. 4,967,397 to Walck (Ex. 1007);
`
`• U.S. Patent No. 5,956,285 to Watanabe et al. (Ex. 1008);
`
`• Masashi Horiguchi et al., A Flexible Redundancy Technique for High-
`
`Density DRAM’s, IEEE JOURNAL OF SOLID-STATE CIRCUITS,
`
`VOL. 26, NO. 1, Jan. 1991, at 12-17 (Ex. 1009);
`9
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 13
`
`

`

`• Kazutami Arimoto et al., A 60-ns 3.3-V-Only 16 Mbit DRAM with
`
`Multipurpose Register,
`
`IEEE JOURNAL OF SOLID-STATE
`
`CIRCUITS, VOL. 24, NO. 5, Oct. 1989, at 1184-90 (Ex. 1010);
`
`• U.S. Patent No. 5,687,123 to Hidaka et al. (Ex. 1011);
`
`• U.S. Patent No. 5,726,946 to Yamagata et al. (Ex. 1012);
`
`• U.S. Patent No. 6,003,148 to Yamauchi et al. (Ex. 1013);
`
`• U.S. Patent No. 6,075,743 to Barth et al. (Ex. 1014);
`
`•
`
`Inter Partes Review No. IPR2016-00096 paper no. 8, Decision on
`
`Institution of Inter Partes Review filed April 21, 2016 (Ex. 1015);
`
`•
`
`Inter Partes Review No. IPR2016-00096 paper no. 11, Judgment
`
`Granting Request for Adverse Judgment filed August 3, 2016 (Ex.
`
`1016); and
`
`• Paper no. 1, Petition for Inter Partes Review of the ’181 patent (Aug.
`
`12, 2016);
`
`• Paper no. 10, Patent Owner’s Preliminary Response (Nov. 23, 2016);
`
`• Declaration of Dr. Pinaki Mazumder In Support Of Petition For Inter
`
`Partes Review (Ex. 1001);
`
`• Paper no. 11, Decision on Institution of Inter Partes Review (Feb. 7,
`
`2017);
`
`• The additional background materials mentioned below in this
`10
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 14
`
`

`

`declaration.
`
`Naturally, my review of these materials was informed by my education, my
`
`experience in and knowledge of industry, and my work as both as a researcher and
`
`a consultant.
`
`IV. Applicable Legal Standards
`22. As a technical expert, I am not offering any legal opinions. Rather I am
`
`offering technical assessments and opinions. In rendering my analysis, I have been
`
`informed by counsel regarding various legal standards for determining patentability.
`
`I have applied those standards informing my technical opinions expressed in this
`
`report.
`
`23. The patent claims describe the invention made by the inventor and
`
`describe what the patent owner owns and what the owner may prevent others from
`
`doing. I understand that an independent claim sets forth all the requirements that
`
`must be met to be covered by that claim. I further understand that a dependent claim
`
`does not itself recite all of the requirements of the claim but refers to another claim
`
`and incorporates all of the requirements of the claim to which it refers.
`
`24.
`
`It is my understanding that a claimed invention is unpatentable if the
`
`differences between the invention and the prior art are such that the subject matter
`
`as a whole would have been obvious at the time the invention was made to a person
`
`having ordinary skill in the art to which the subject matter pertains. Obviousness, as
`11
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 15
`
`

`

`I understand it, is based on the scope and content of the prior art, the differences
`
`between the prior art and the claim, and the level of ordinary skill in the art.
`
`25.
`
`I understand that when evaluating obviousness, one must not consider
`
`whether the claimed invention would have been obvious to a layman or to an expert;
`
`not use hindsight when comparing the prior art to the claimed invention; not consider
`
`what was learned from the teachings of the patent. In particular, I understand that it
`
`is improper to use the patent claims as a road map for selecting and combining items
`
`of prior art. In other words, one should avoid using the challenged patent as a guide
`
`through the prior art references, combining the right references in the right way so
`
`as to achieve the result of the claims at issue. Instead, one must put oneself in the
`
`place of a person of ordinary skill at the time the invention was made and consider
`
`only what was known before the invention was made and not consider what is known
`
`today.
`
`26.
`
`I understand that obviousness should be considered in light of the
`
`problems known to the person having ordinary skill in the art and the complexity of
`
`the alternatives for solving the problem. That individual elements of the claimed
`
`invention are disclosed in the prior art is not alone sufficient to reach a conclusion
`
`of obviousness.
`
`27.
`
`I also understand that when considering the obviousness of a patent
`
`claim, one must consider whether a teaching, suggestion, or motivation to combine
`12
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 16
`
`

`

`the references exists so as to avoid impermissibly applying hindsight when
`
`considering the prior art. I understand that a teaching, suggestion, or motivation may
`
`be found explicitly or implicitly: (1) in the prior art; (2) in the knowledge of those
`
`of ordinary skill in the art; or (3) from the nature of the problem to be solved. I also
`
`understand that the legal determination of the motivation to combine references
`
`allows recourse to logic, judgment, and common sense, but that any such motivation
`
`to combine references must still avoid the improper application of hindsight or
`
`reliance on the patentee’s disclosure of his invention as found in the patent
`
`specification, drawings, and claims.
`
`28.
`
`I understand that if the teachings of a prior art reference would lead one
`
`skilled in the art to make a modification that would render that prior art device,
`
`system, or method inoperable, then such a modification would generally not be
`
`obvious. I also understand that if a proposed modification would render the prior art
`
`device, system, or method unsatisfactory for its intended purpose, then there is
`
`strong evidence that no suggestion or motivation existed at the time of the subject
`
`invention to make the proposed modification.
`
`29.
`
`I understand that it is improper to combine references where the
`
`references teach away from their combination. I understand that a reference may be
`
`said to teach away when a person of ordinary skill, upon reading the reference, would
`
`be discouraged from following the path set out in the reference, or would be led in a
`13
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 17
`
`

`

`direction divergent from the path that was taken by the applicant. It is also my
`
`understanding that the degree of teaching away will depend on the particular facts;
`
`in general, a reference will teach away if it suggests that the line of development
`
`flowing from the reference’s disclosure is unlikely to be productive of the result
`
`sought by the applicant. I understand that a reference teaches away, for example, if
`
`(1) the combination would produce a seemingly inoperative device, or (2) the
`
`references leave the impression that the product would not have the property sought
`
`by the applicant or would no longer achieve the intended purpose(s) of the references
`
`being modified or combined.
`
`V.
`
`Person Of Ordinary Skill In The Art
`30.
`
`I have been asked to address the issues raised in the Petition from the
`
`perspective of a person of ordinary skill in the field of the ’181 patent (“POSITA”).
`
`As stated in the ’181 patent, the field of the invention relates to “a redundancy circuit
`
`for repairing a defective memory cell in a semiconductor memory device having such
`
`an array-divided arrangement.” (Ex. 1003 at 1:10–12.)
`
`31. A POSITA would have a bachelor’s degree in a field such as electrical
`
`engineering, computer engineering, computer science or a closely related field, along
`
`with at least 4–5 years of experience in the design, development, and/or testing of
`
`memory devices. An individual with an advanced degree in a relevant field would
`
`require less experience in the design of memory devices.
`14
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 18
`
`

`

`32.
`
`I understand that Apple’s Petition and Dr. Mazumder’s declaration (Ex.
`
`1001 ¶ 28–30) asserts a POSITA would have a higher level of skill in the art. I
`
`understand further that Dr. Mazumder testified that, in his experience, companies
`
`designing memory chips frequently hire individuals with graduate degrees. (E.g.,
`
`Mazumder Depo. Tr. at 76:10–78:5, 78:21–83:8.) But many of the individuals hired
`
`by such companies do not have graduate degrees, and thus the level of ordinary skill
`
`in the art should specifically include such individuals. Particularly in Japan and
`
`Korea, where many memory chip manufacturers design and fabricate memory
`
`chips, it is my understanding that the common practice is to hire individuals with an
`
`undergraduate degree and then train them on the job. With the experience described
`
`above such individuals would be familiar with and readily understand the design
`
`tradeoffs relevant to the technology described in the ’181 patent.
`
`33. Focusing on a higher level of educational credentials may improperly
`
`suggest that a POSITA would be more likely to arrive at the inventions recited in
`
`claims 3 and 5 of the ’181 patent. I disagree. In many instances, a graduate degree
`
`would provide the POSITA with deeper knowledge in fields unrelated to the
`
`problems addressed in the ’181 patent or more generally to the design, development,
`
`and/or testing of memory devices. Thus, my conclusions regarding the patentability
`
`of claims 3 and 5 of the ’181 patent would not change even if Dr. Mazumder’s
`
`definition of the level of ordinary skill in the art.
`15
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 19
`
`

`

`34.
`
`I consider myself to have at least the credentials of a person of ordinary
`
`skill in the art, and I am capable of addressing the issues from the perspective of
`
`such a person. As a result of my education, academic experience, and industrial
`
`experience, I am familiar with semiconductor memory devices having a memory
`
`array divided in to a plurality of memory blocks, and also with the state of that
`
`technology in June of 1998, when the first application to which the ’181 patent
`
`claims priority to was filed.
`
`VI. Overview Of The Relevant Technology
`35. A Dynamic Random Access Memory (“DRAM”) cell is a memory cell,
`
`comprising one capacitor and one transistor. Each memory cell holds one bit of data.
`
`Figure 1 displays the one-transistor/one-capacitor memory cell widely-accepted and
`
`utilized in commercial DRAM integrated circuits throughout the world.
`
`word line
`
`bit line
`
`transistor
`
`Storage
`capacitor
`
`
`
`Figure 1 (DRAM cell structure)
`
`36. A DRAM integrated circuit comprises memory cells arranged in one or
`16
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 20
`
`

`

`more large grids, known as arrays. Below is an exemplary 16 x 8 array of DRAM
`
`memory cells, containing 16 vertical columns and 8 horizontal rows of memory
`
`cells.
`
`Figure 2 (16 x 8 DRAM array)
`
`
`
`As shown in Figure 2, each horizontal row of memory cells has a corresponding
`
`word line capable of supplying the voltage necessary to activate the desired row of
`
`cells. Each vertical column of memory cells has a corresponding bit line capable of
`
`writing data onto and reading data from individual memory cells. Each row
`
`includes an arbitrary number of memory cells.
`
`37. When writing data onto a cell, a voltage is applied to the word line of
`
`the row of the desired cell to select / activate that row of cells (the word line is
`
`“asserted”). Data is then transmitted through the bit line of the column of the desired
`
`cell, and written onto the cell lying at the intersection of the asserted word line and
`
`17
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 21
`
`

`

`data-transmitting bit line. The data is stored as a charge in the storage capacitor of
`
`the cell, labeled 𝐶𝐶𝑇𝑇 in Figure 1 above. For example, the value “1” might be
`
`associated with a high voltage (i.e., a stored charge) in the capacitor and the value
`
`“0” might be associated with a zero voltage (i.e., no stored charge) in the capacitor,
`
`or vice versa.
`
`38. When reading data from a cell, the bit lines are precharged to an
`
`intermediate voltage, and the word line of the row of the desired cell is asserted.
`
`The voltage stored in the cell at the intersection of the asserted word line and a
`
`precharged bit line will cause a charge redistribution between the storage capacitor
`
`of the cell (𝐶𝐶𝑇𝑇 in Figure 1) and bit line capacitor (𝐶𝐶𝐵𝐵𝐵𝐵 in Figure 1). This will cause
`
`the bit line voltage to increase slightly (if there was a high voltage stored in the cell
`
`prior to charge distribution) or decrease slightly (if there was a zero voltage stored
`
`in the cell prior to charge distribution). The magnitude of the bit line voltage change
`
`is high if CT is higher, and if CBL is lower.
`
`39. The redistribution of charge accompanying reading of a memory cell is
`
`destructive to any data that was stored within the cell. The charge (or absence
`
`thereof) stored in the storage capacitor is redistributed with the bitline charge,
`
`causing the corresponding increase or decrease in the bitline (and cell) voltage as a
`
`result of the read operation. Hence the stored cell voltage is destroyed by the read
`
`operation.
`
`18
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 22
`
`

`

`40. Due to the charge redistribution between CT and CBL, the final read
`
`voltage is slightly above or below the bit line precharge voltage. Since this is not a
`
`“rail” voltage (either of the supply or ground voltages), special circuits need to be
`
`employed to “sense” the change in bit line voltage, and thereby read the cell value.
`
`41. To read the small bit line voltage changes, mentioned in paragraphs 39–
`
`40, sense amplifiers are employed in DRAM arrays. Sense amplifiers sense the low
`
`voltage increase (or decrease) on the bit line during a read operation depending on
`
`whether the cell capacitance was charged (or discharged) respectively, and amplify
`
`it to a clean, recognizable logic level that can be read and properly interpreted by a
`
`receiving data output buffer. Additionally, after the read operation is complete, the
`
`read voltage is reasserted and written onto the recently read memory cell, thereby
`
`recharging the storage capacitor and rewriting the data.
`
`42. A simple exemplary sense amplifier is diagrammed below in Figure 3.
`
`
`
`Figure 3 (sense amplifier)
`
`19
`
`Limestone Memory Systems, LLC – Exhibit 2004, p. 23
`
`

`

`The cross-linked transistor gates in this sense amplifier design amplify the voltage
`
`difference between in and 𝚤𝚤𝚤𝚤� .
`In Figure 3 in and 𝚤𝚤𝚤𝚤� are the left and right halves of a bit line. One half
`
`43.
`
`of the bit line brings data, as a non-rail voltage value, from an adjacent memory cell.
`
`The other half of the bit line contains no data, but is the pre-charged value from the
`
`read operation. In some designs, it is the value of an unselected bit line, used as a
`
`reference. Without loss of generality, if the voltage of in is slightly above (below)
`
`that of 𝚤𝚤𝚤𝚤� , then out pulls lower (higher), causing the transistor whose gate is
`connected to out to turn on stronger (less strongly), and thereby causing 𝑜𝑜𝑜𝑜𝑜𝑜����� to pull
`higher (lower). This positive feedback continues until out and 𝑜𝑜𝑜𝑜𝑜𝑜����� resolve into rail
`
`values, at which point the out signal can then be sent to a data out