IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`David Locket, et al.
`In re Patent of:
`8,457,476 Attorney Docket No.: 39843-0039IP1
`U.S. Patent No.:
`June 4, 2013
`Issue Date:
`Appl. Serial No.: 12/498,335
`Filing Date:
`July 6, 2009
`Title:
`Multimedia Signal Processing System
`
`
`DECLARATION OF JEFFREY J. RODRIGUEZ, PhD
`
`
`
`
`
`1
`
`SAMSUNG 1003
`
`
`
`David Locket, et al.
`In re Patent of:
`8,457,476 Attorney Docket No.: 39843-0039IP1
`U.S. Patent No.:
`June 4, 2013
`Issue Date:
`Appl. Serial No.: 12/498,335
`Filing Date:
`July 6, 2009
`Title:
`Multimedia Signal Processing System
`
`
`DECLARATION OF JEFFREY J. RODRIGUEZ, PhD
`
`
`
`
`
`1
`
`SAMSUNG 1003
`
`
`
`I, Jeffrey J. Rodriguez, Ph.D., of La Jolla, California, declare that:
`
`I.
`
`QUALIFICATIONS AND BACKGROUND INFORMATION
`1.
`I am currently a faculty member in the Dept. of Electrical and
`
`Computer Engineering, Director of the Signal and Image Laboratory (SaIL), and a
`
`faculty member in the Biomedical Engineering Graduate Interdisciplinary Program
`
`at the University of Arizona. A copy of my curriculum vitae, which describes in
`
`further detail my qualifications, employment history, honors, awards, professional
`
`associations, presentations, and publications is attached hereto as Exhibit 1.
`
`2. My formal education includes a bachelor's degree in Electrical
`
`Engineering from the University of Texas at Austin in May 1984 and a master’s
`
`degree in Electrical Engineering from Massachusetts Institute of Technology in
`
`June 1986, and I earned a Ph.D. degree in Electrical Engineering from the
`
`University of Texas at Austin in May 1990.
`
`3.
`
`Since 1990, I have been a faculty member in the Department of
`
`Electrical and Computer Engineering at the University of Arizona, where I hold or
`
`have held the following positions: (a) Tenured Associate Professor of Electrical
`
`and Computer Engineering (1997-present), (b) Director of the Signal and Image
`
`Laboratory (1990-present), (c) Faculty member in the Biomedical Engineering
`
`Interdisciplinary Program (2002-present), (d) Director of Graduate Studies for the
`
`Department of Electrical and Computer Engineering (2000-2003, 2005-2016).
`
`2
`
`
`
`From 2003 to 2008, I served as Co-Director of Connection One, a National Science
`
`Foundation industry/university cooperative research center focused on wired and
`
`wireless communication circuits and systems. I teach courses at both the graduate
`
`and undergraduate level, including Circuit Analysis, Signals and Systems, Signal
`
`Processing, and Advanced Signal Processing. I have also taught other courses,
`
`including Image Processing and Image Analysis. In 1992 I was awarded the
`
`Outstanding Teaching Award by the IEEE and Eta Kappa Nu, given by the
`
`students at the University of Arizona to one outstanding professor each year.
`
`4. My research activity is generally directed to the design and analysis of
`
`hardware (analog and digital) and software for electronic systems (including
`
`microprocessor systems), especially for automated signal/image/video processing
`
`applications.
`
`5.
`
`For example, one of my research projects included the development of
`
`an electronic system for digital flow cytometry for real-time measurement of
`
`biological cells. We designed and built a custom board including FIFOs for
`
`buffering the signals, a microprocessor for FIFO control and real-time signal
`
`analysis, a system bus for interfacing to SRAM, a dual-ported memory system for
`
`handshaking and data communication between the processor and a PC via a PCI
`
`bus.
`
`3
`
`
`
`6.
`
`Another example of my research activity is the design and
`
`development of a real-time video processing system for automated behavioral
`
`analysis of zebrafish for use in ototoxicity assessment of drugs. The system we
`
`designed and built includes an array of Raspberry Pi microcomputer systems
`
`configured for parallel video capture of sixteen parallel zebrafish populations. Each
`
`Raspberry Pi features a Broadcom system on a chip, which includes an ARM-
`
`compatible CPU, a video graphics processing unit (GPU), and a memory system.
`
`Data collected is then automatically transmitted to a high-performance cluster for
`
`further video processing and analysis.
`
`7.
`
`I am a Senior Member of the Institute of Electrical and Electronics
`
`Engineers (IEEE) and the IEEE Signal Processing Society. Over the years, I have
`
`served as General Chair of several IEEE conferences, served on numerous IEEE
`
`organizing committees, and held other positions on various IEEE committees, and
`
`I have served as a technical reviewer for numerous journals and professional
`
`conferences.
`
`8.
`
`In writing this Declaration, I have considered the following: my own
`
`knowledge and experience, including my work experience in the field of
`
`signal/image/video processing; my experience in teaching those subjects; and my
`
`experience in working with others involved in those fields. In addition, I have
`
`4
`
`
`
`analyzed the following publications and materials, in addition to other materials I
`
`cite in my declaration:
`
` U.S. Pat. No. 8,457,476 to Locket et al. (“the ’476 patent”, Exhibit
`
`SE1001), and its accompanying prosecution history (Exhibit SE1002);
`
` U.S. Patent No. 6,369,855 to Chauvel et al., including Appendix A
`
`and Appendix B (“Chauvel”, Exhibit SE1004);
`
` U.S. Patent No. 5,909,559 to So (“So”, Exhibit SE1005);
`
` U.S. Patent No. 5,812,930 to Zavrel (“Zavrel”, Exhibit SE1006)
`
` TIVO’s P.R. 4-2 Disclosure (Exhibit SE1007);
`
` TIVO'S FOURTH SUPPLEMENTAL OBJECTIONS AND
`
`RESPONSES TO DEFENDANTS’ FIRST SET OF
`
`INTERROGATORIES (No. 18) (“TiVo Responses to
`
`Interrogatories”, Exhibit SE1008).
`
` U.S. Patent No. 6,233,389 to Barton et al. (“the ’389 patent”, Exhibit
`
`SE1009)
`
` U.S. Patent Application Publication No. 2002/0057892 to Mano et al.
`
`(“Mano”, Exhibit SE1010)
`
` Prosecution History of Ex Parte Reexamination of claims 31 and 61 of
`
`the ’389 patent (Serial No. 90/009329) (“Second Reexam”, Exhibit
`
`SE1011)
`
`5
`
`
`
`9.
`
`Although this Declaration refers to selected portions of the cited
`
`references for the sake of brevity, it should be understood that these are examples,
`
`and that one of ordinary skill in the art would have viewed the references cited
`
`herein in their entirety and in combination with other references cited herein or
`
`cited within the references themselves. The references used in this Declaration,
`
`therefore, should be viewed as being incorporated herein in their entirety.
`
`10.
`
`I am not, and never was, an employee of the Petitioner in this
`
`proceeding, Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
`
`I have been engaged in the present matter to provide my independent analysis of
`
`the issues raised in the petition for inter partes review of the ’476 patent. I
`
`received no compensation for this declaration beyond my normal hourly
`
`compensation based on my time actually spent studying the matter, and I will not
`
`receive any added compensation based on the outcome of this inter partes review
`
`of the ’476 patent.
`
`II. LEGAL PRINCIPLES
`A. Anticipation
`11.
`I have been informed that a patent claim is invalid as anticipated
`
`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
`
`is found either explicitly or inherently in a single prior art reference. Under the
`
`6
`
`
`
`principles of inherency, if the prior art necessarily functions in accordance with, or
`
`includes the claimed limitations, it anticipates.
`
`12.
`
`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
`
`if the claimed invention was known or used by others in the U.S., or was patented
`
`or published anywhere, before the applicant’s invention. I further have been
`
`informed that a claim is invalid under 35 U.S.C. § 102(b) if the invention was
`
`patented or published anywhere, or was in public use, on sale, or offered for sale in
`
`this country, more than one year prior to the filing date of the patent application.
`
`And a claim is invalid, as I have been informed, under 35 U.S.C. § 102(e), if an
`
`invention described by that claim was described in a U.S. patent granted on an
`
`application for a patent by another that was filed in the U.S. before the date of
`
`invention for such a claim.
`
`B. Obviousness
`13.
`I have been informed that a patent claim is invalid as “obvious” under
`
`35 U.S.C. § 103 in light of one or more prior art references if it would have been
`
`obvious to a person of ordinary skill in the art at the time of the invention of the
`
`’389 patent (“POSITA”), taking into account (1) the scope and content of the prior
`
`art, (2) the differences between the prior art and the claims, (3) the level of
`
`ordinary skill in the art, and (4) any so called “secondary considerations” of non-
`
`obviousness, which include: (i) “long felt need” for the claimed invention, (ii)
`
`7
`
`
`
`commercial success attributable to the claimed invention, (iii) unexpected results
`
`of the claimed invention, and (iv) “copying” of the claimed invention by others.
`
`14.
`
`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. To be obvious in light of a
`
`single prior art reference or multiple prior art references, there must be a reason to
`
`modify the single prior art reference, or combine two or more references, in order
`
`to achieve the claimed invention. This reason may come from a teaching,
`
`suggestion, or motivation to combine, or may come from the reference or
`
`references themselves, the knowledge or “common sense” of one skilled in the art,
`
`or from the nature of the problem to be solved, and may be explicit or implicit
`
`from the prior art as a whole. I have been informed that the combination of
`
`familiar elements according to known methods is likely to be obvious when it does
`
`no more than yield predictable results. I also understand it is improper to rely on
`
`hindsight in making the obviousness determination.
`
`III. OVERVIEW OF CONCLUSIONS FORMED
`15. This expert Declaration explains the conclusions that I have formed
`
`based on my analysis. In summary, based upon my knowledge and experience and
`
`my review of the prior art publications listed above, I believe that claims 1, 6-11,
`
`and 14 of the ’476 patent are anticipated by Chauvel. Based upon my knowledge
`
`and experience and my review of the prior art publications listed above, I believe
`
`8
`
`
`
`that claims 1, 6-11, 13, and 14 are rendered obvious by Chauvel. Based upon my
`
`knowledge and experience and my review of the prior art publications listed above,
`
`I believe that claims 1, 6-11, 13, and 14 are rendered obvious by Chauvel in view
`
`of So.
`
`IV. BACKGROUND
`16. The technology in the ’476 patent at issue generally relates to
`
`streaming of audio and video data. Prior to the filing date of the ’476 patent, there
`
`existed products, publications, and patents that implemented or described
`
`functionality claimed in the ’476 patent. Thus, the system and methodology of the
`
`’476 patent was known in the prior art. Further, to the extent there was any
`
`problem to be solved in the ’476 patent, it had already been solved in prior art
`
`systems before the filing date of the ’476 patent.
`
`A. Overview of the ’476 Patent
`17. The ’476 patent “relates to the real time capture, storage, and display
`
`of television broadcast signals.” [SE1001, 1:28-30.] FIG. 14 (annotated and
`
`reproduced below) provides a “high level view” of the ’476 patent’s system.
`
`[SE1001, 2:55-56.] Within that high level framework, claim 1 is directed to the
`
`features described below.
`
`18. Referring to annotated FIG. 14 of the ’476 patent below, a system
`
`board 1400 includes an input section 1401 that accepts an input signal from a
`
`9
`
`
`
`source —e.g., a television input stream. [Id. at 3:26-39, 12:18-24.] The input
`
`section 1401 produces an MPEG transport stream, which is a stream of data with
`
`interleaved audio and video segments. [Id. at 3:39-56.] The system board 1400
`
`includes an output section 1402, which includes a CPU 1403, a decoder/graphics
`
`subsystem 1404, and a media switch containing a media manager 1405. [Id. at
`
`12:24-60; claim 1.] The CPU 1403 functions to initialize and control operation of
`
`the various hardware components. [Id. at 12:24-60.] The decoder/graphics
`
`subsystem 1404 accepts a transport stream delivered from the input section 1401
`
`over a transport stream interface 1406, and communicates with the CPU 1403.
`
`[Id.] The decoder/graphics subsystem 1404 decodes the transport stream received
`
`from the input section, and outputs the decoded stream as a video signal to a
`
`television set. [Id.] The media manager 1405 primarily acts as a bridging element
`
`between system components. [Id.] In particular, through the action of a media
`
`stream processor and a high-speed transport output interface, the media manager
`
`mediates the transfer of media streams between system components. [Id. at
`
`14:42-46.] In addition, the media manager 1405 communicates with the
`
`decoder/graphics subsystem 1404 and saves the transport stream to a storage
`
`subsystem. [Id. at 13:24-60.] The media manager 1405 includes a host controller,
`
`which, in certain implementations, may encrypt data to be stored. [Id. at 14:8-34,
`
`14:59-65.] The media manager 1405 also includes a PCI bus arbiter. [Id.]
`
`10
`
`
`
`[SE1001, FIG. 14 (annotated).]
`19. The media switch containing the media manager runs asynchronously
`
`
`
`with the microprocessor CPU because the media manager includes a DMA
`
`controller that moves large quantities of data with minimal intervention by the
`
`CPU. [Id. at 5:1-9, 13:20-34.] Data may be stored to and retrieved from the
`
`storage subsystem by DMA engines that can be working at the same time, based on
`
`program instructions from the CPU. [Id. at 6:4-12, 6:33-49, 6:58-62, 6:65-7:32.]
`
`
`
`11
`
`
`
`B.
`Background Prior Art - Chauvel
`20. A review of other relevant literature available at the time shows that
`
`the idea of “multimedia signal processing” for “real time capture, storage, and
`
`display of television broadcast signals” was well known in the technical
`
`community by 1998. For example, Chauvel discloses a system for processing data
`
`streams with an audio and video decoder circuit. Chauvel’s system is represented
`
`at its highest level in Figure 1A (annotated and reproduced below), showing an
`
`input section including a satellite reception dish 5, a low noise amplifier 10, a tuner
`
`20, a quadrature phase-shift keying (QPSK) circuit 30, and a forward error
`
`correction (FEC) circuit 40 providing input to circuit 200, which provides audio
`
`and video output.
`
`[SE1004, FIG. 1A (annotated).]
`
`12
`
`
`
`
`
`21. Chauvel discloses a multimedia data processing system. For example,
`
`Figure 1A of Chauvel (annotated and reproduced above) shows an input section,
`
`including a satellite reception dish 5, a low noise amplifier 10, a tuner 20, a
`
`quadrature phase-shift keying (QPSK) circuit 30, and a forward error correction
`
`(FEC) circuit 40, and also shows an output section. As shown in more detail in
`
`Figure 1B of Chauvel (annotated and reproduced below), the circuit 200 receives
`
`transport data and includes an ARM CPU 220 as a processor, a Transport Packet
`
`Parser (TPP) 210 and A/V Core 250 with Video Decoder 252 and Audio Decoder
`
`254 and On Screen Display (OSD) module as a decoder subsystem, a storage
`
`subsystem in the form of SDRAM 312 and/or RAM 240 and a 1394 device, a 1394
`
`Interface (I/F) 290 as a host controller and a Traffic Controller 310, which serves
`
`to interface several of the system components, as a media switch and media
`
`manager. [SE1004 at 10:16-19, 10:39-40, 12:15-21, 21:14-17.] In addition, the
`
`Traffic Controller (TC) 310 controls two physical DMA channels for DMA
`
`transfers, includes an arbiter block 313-12, and processes packets of the data
`
`stream. [Id.]
`
`13
`
`
`
`
`
`[SE1004, FIG. 1B (annotated).]
`
`
`
`C. Background Prior Art – So
`22.
`In addition to Chauvel, by the time of the alleged invention of the
`
`’476 patent, other systems provided multimedia data processing with simultaneous
`
`playback and record. For example, So discloses an apparatus and process for data
`
`stream processing that includes executing simultaneous playback and record with a
`
`dual-ported memory for simultaneous access. [SE1005 at 52:4-10, 95:44-46.]
`
`
`
`14
`
`
`
`D.
`Person of Ordinary Skill in the Art
`23. Based on the foregoing and upon my experience in this area, a person
`
`of ordinary skill in the art in this field at the time of invention (“POSITA”) would
`
`have had a combination of experience and education in signal processing
`
`component and/or signal processing system design. This typically would consist
`
`of a minimum of a bachelor of science in electrical engineering, computer
`
`engineering, or a related field plus 2-5 years of work, graduate study, and/or
`
`research experience in the field of signal processing component and/or signal
`
`processing system design. Additional education in a relevant field, such as
`
`computer science, software engineering, or a related field, or additional industry
`
`experience may compensate for a deficit in one of the other aspects of the
`
`requirements stated above.
`
`24. Because I do not know the precise date the invention as claimed was
`
`made, I have used the filing date of U.S. Patent No. 6,233,389 as the invention
`
`date, for the sole purpose of this Declaration, since that is the earliest alleged
`
`priority date of the ’476 patent. That date was July 30, 1998. My analysis and
`
`opinions in this Declaration would still be the same even if the invention date is
`
`found to be later, up to the filing date of the ‘476 patent, which was July 6, 2009.
`
`Based on my experiences, I have at least the level of skills of a POSITA.
`
`15
`
`
`
`V. CLAIM CONSTRUCTION
`25.
`I understand that, for purposes of my analysis in this inter partes
`
`review proceeding, the terms appearing in the patent claims should be interpreted
`
`according to their broadest reasonable construction in light of the specification of
`
`the patent in which it appears. In that regard, I understand that the best indicator of
`
`claim meaning is its usage in the context of the patent specification as understood
`
`by a POSITA. I further understand that the words of the claims should be given
`
`their plain meaning unless that meaning is inconsistent with the patent
`
`specification or the patent’s history of examination before the Patent Office. I also
`
`understand that the words of the claims should be interpreted as they would have
`
`been interpreted by a POSITA.
`
`26.
`
`I also understand that in district court, Patent Owner has proposed
`
`constructions for a number of claim terms of the ’476 patent. [See SE1007.] I
`
`have been informed that the claim construction standard for district court is
`
`different than the broadest reasonable interpretation standard (“BRI”). I
`
`understand that Patent Owner’s interpretation of the claim terms under BRI will be
`
`at least as broad as Patent Owner’s interpretation of the claim terms in district
`
`court. Thus, for the purpose of this proceeding, I am applying constructions on the
`
`following terms that are at least as broad as the constructions proposed by Patent
`
`Owner, including:
`
`16
`
`
`
`
`
`1
`
`Claim Term
`transport stream
`(claims 1, 8, 9)
`
`media switch
`(claims 1, 13)
`
`multimedia data stream
`processor
`(claim 1)
`
`transport stream
`interface
`(claim 8)
`front panel
`navigation cluster
`(claim 13)
`
`2
`
`3
`
`4
`
`5
`
`
`
`Construction
`“a stream of data that includes interleaved video
`and audio segments.”
`SE1007 at 14; see also SE1001 at 4:42-59 and
`14:29-51.
`“hardware and/or code that mediates between a
`microprocessor CPU, hard-disk or storage
`device, and memory.”
`SE1007 at 14; see also SE1001 at 4:60-67 and
`7:48-57.
`“media switch/media manager processor(s) that
`processes multimedia data.”
`SE1007 at 14; see also SE1001 at 15:8-34 and
`18:18 – 19:21.
`“an interface that receives transport streams.”
`SE1007 at 14; see also SE1001 at 13:18-38.
`
`“exterior buttons or keys to control the device.”
`SE1007 at 14; see also SE1001 at 15:8-34,
`15:66 – 16:10, and 17:66 – 18:14.
`
`27. For all other terms, I have assumed the plain and ordinary meaning.
`
`Understanding that claim interpretation in district courts can be different than, and
`
`possibly narrower than, claim interpretation under the BRI standard, I have
`
`performed no analysis as to whether the above constructions are correct under the
`
`standard in district court, and consequently, offer no opinion on that subject.
`
`VI. ANALYSIS OF CHAUVEL
`28. As explained above, Chauvel is directed to “audio-visual systems and
`
`integrated circuits used therein” to process multimedia data. [SE1004 at 1:28-31.]
`
`Chauvel discloses a video and audio decoder system, including an integrated
`
`17
`
`
`
`circuit and television signal receiver, that has a portion corresponding to the
`
`claimed input section and a portion corresponding to the remainder of the claimed
`
`system, as shown in Chauvel’s Figure 1A, which I have included below with
`
`annotation.
`
`[SE1004, FIG. 1 (annotated).]
`
`29. As illustrated in Chauvel’s Figures 1B and 2, which I have annotated
`
`for clarity below, components disclosed by Chauvel correspond to the claimed
`
`transport stream, processor, decoder subsystem, storage subsystem, and media
`
`switch comprised of a host controller, DMA controller, bus arbiter, and multimedia
`
`data stream processor.
`
`18
`
`
`
`[SE1004, FIG. 1B (annotated).]
`
`30. The traffic controller 310 managing the flow of the data stream by
`
`interfacing multiple system components is shown by Chauvel in the higher level
`
`block diagram of Figure 2, which I have annotated and included below.
`
`19
`
`
`
`[SE1004, FIG. 2 (annotated).]
`
`31. Additional details of Chauvel’s arbiter, which corresponds to the
`
`claimed bus arbiter, are shown in Figure 16Q, which I have annotated and provided
`
`below. For example, there are multiple incoming requests to pass data and an
`
`arbiter to arbitrate those requests being sent along the bus as commands.
`
`20
`
`
`
`
`
`[SE1004, FIG. 16Q (annotated).]
`
`32. A portion of Chauvel’s system is shown in Figure 18B, which I have
`
`annotated and provided below, illustrating multiple buses serving to interconnect
`
`multiple system components, including a data bus connecting components that
`
`correspond to the claimed decoder subsystem to the processor and a data bus
`
`connecting components that correspond to the media switch to the components that
`
`correspond to the claimed decoder subsystem.
`
`21
`
`
`
`
`
`[SE1004, FIG. 18B (annotated).]
`
`33.
`
`In the paragraphs that follow, I will discuss how Chauvel anticipates
`
`or renders obvious all features of claims 1, 6-11, 13, and 14, and how Chauvel in
`
`view of So renders obvious all features of claims 1, 6-11, 13, and 14.
`
`A. Claim 1
` [1.Pre] A system for the simultaneous storage and retrieval of multimedia data,
`comprising:
`34. The preamble of claim 1 recites a “system for the simultaneous
`
`storage and retrieval of multimedia data.” None of the claim elements in claim 1
`
`has antecedents or finds support in the preamble.
`
`22
`
`
`
`35. Moreover, Chauvel discloses a system for the simultaneous storage
`
`and retrieval of multimedia data. Playback may occur without data being stored
`
`and retrieved from a storage subsystem – for example, when data is sent directly to
`
`the decoder. Chauvel discloses a “recording mode,” a “playback mode,” and
`
`“decod[ing] one program while recording from 1 to all 32 possible services from a
`
`transponder.” [SE1004 at 17:19-38.] In addition, Chauvel discloses storing
`
`transport stream data in SDRAM 312 and reading transport stream data from
`
`SDRAM 312. [SE1004 at 10:25-26, 60-64 (“The data transfer from TPP 210 to
`
`SDRAM 312 is done via DMA set up by the traffic controller (TC) 310. . . . both
`
`audio and video data is stored in external SDRAM 312. The video 252 and audio
`
`254 decoders then read the bitstream from SDRAM 312.”); 10:8-11 (“Continuing
`
`to refer to FIG. 2, it may be seen how the circuit 200 accepts a transport bitstream
`
`from the output 10 of a forward error correction (FEC) device (not depicted) with a
`
`maximum throughput of 40 Mbits/s or 7.5 Mbytes/s.”).] Chauvel further discloses
`
`that “as long as there is no collision in the source and destination, it is possible to
`
`have two concurrent DMA transfers.” [SE1004 at 12:17-19.]
`
`36.
`
`In addition, Chauvel discloses that data packets from the TPP 210 can
`
`be sent to both the 1394 Interface 290 and to the RAM 240 at the same time,
`
`allowing for “decod[ing] one program while recording from 1 to all 32 possible
`
`services from a transponder.” [SE1004 at 17:19-38 (“In recording mode, the
`
`23
`
`
`
`circuit 200 will send either encrypted or clean packets to the 1394 interface 290. . .
`
`. During playback mode, the packet coming from the interface will go directly into
`
`the TPP 210 module. … The packet coming out from TPP 210 can go either to the
`
`1394 interface 290 or to the RAM 240 through traffic controller TC, or to both
`
`places at the same time. This allows the circuit 200 to decode one program while
`
`recording from 1 to all 32 possible services from a transponder.”)] Thus, Chauvel
`
`discloses retrieving from memory for decoding during playback of multimedia data
`
`simultaneously with recording by sending multimedia data to the 1394 interface for
`
`storage on the 1394 device. Therefore, Chauvel discloses simultaneous storage
`
`and retrieval of multimedia data, as claimed.
`
` [1.a] an input section that acquires an input signal;
`37. Referring to Figure 1A of Chauvel, which I have annotated and
`
`provided below, an exemplary communication system is illustrated. A portion of
`
`Chauvel’s communication system shown in Figure 1A corresponds to the claimed
`
`input section that acquires an input signal (e.g., satellite signals). For example,
`
`Chauvel discloses as an input section: a satellite reception dish 5, a low noise
`
`amplifier 10, a tuner 20, a quadrature phase-shift keying (QPSK) circuit 30, and a
`
`forward error correction (FEC) circuit 40. [SE1004 at 8:38-51 (“More particularly,
`
`there may be seen a satellite reception dish that receives signals from a satellite and
`
`provides them to a low noise amplifier 10. The low noise amplifier provides its
`
`24
`
`
`
`signals to a tuner 20. The tuner 20 is employed to select the signals a user wishes
`
`to watch. The tuner 20 is connected to a quadrature phase-shift keying (QPSK)
`
`circuit 30 that recovers the digital data in the selected signal. This data is then error
`
`corrected by a forward error correction (FEC) circuit 40 using Viterbi, Reed-
`
`Solomon, or other techniques to compensate for data errors. The corrected received
`
`data is then passed to the circuit 200 of the present invention.”); claim 10 (“digital
`
`television signal”).]
`
`[SE1004, FIG. 1A (annotated).]
`
`
`
` [1.b] the input section creates a transport stream from the input signal;
`38. Referring to FIG. 1A above, the portion corresponding to the claimed
`
`input section creates a transport stream, for example, from the signals received
`
`from a satellite. Referring to annotated FIG. 1B below, transport data in the form
`
`25
`
`
`
`of a transport stream is passed from the input section to circuit 200. Thus, Chauvel
`
`discloses “a satellite reception dish 5 that receives signals from a satellite and
`
`provides them to a low noise amplifier 10,” which “provides its signals to a tuner
`
`20 . . . employed to select the signals a user wishes to watch.” [SE1004 at 8:41-45.]
`
`Chauvel further discloses that the “TPP receives a high speed bit stream of
`
`transport data that requires it to analyze the bit stream and direct the data to the
`
`right destination,” and that “the circuit 200 accepts a transport bitstream from the
`
`output of a forward error correction (FEC) device,” which is part of the input
`
`section. [SE1004 at 9:32-34, 10:9-10.]
`
`[SE1004, FIG. 1B (annotated).]
`
`26
`
`
`
`39. Thus, Chauvel discloses that the input section creates a transport
`
`stream from the input signal.
`
`[1.c] a processor;
`40. Referring to Figure 1B of Chauvel, which I have annotated and
`
`provided above, the system includes ARM/Thumb CPU 220, also called ARM
`
`processor 220, which is a processor. SE1004 at 18:24-28 (“Preferably, the CPU
`
`220 in the circuit 200 is a 32 bit RISC 25 processor, the ARM7TDMI/ Thumb . . . .
`
`Other RISC processors may be employed.”); 6:47-49 (“It is an object of the present
`
`invention to provide a 32/16 bit ARM/Thumb processor that removes the need of
`
`another CPU in the set-top box.”); see also 11:65-12:13. Thus, Chauvel discloses
`
`that the system includes a processor.
`
`[1.d] a decoder subsystem that decodes said transport stream, the decoder
`subsystem is communicatively connected to the processor; and
`41. Chauvel discloses an audio decoder, a video decoder, a transport
`
`packet parser, and an on screen display module, which collectively correspond to
`
`the claimed decoder subsystem that decodes the transport stream. [SE1004 at
`
`5:42-43 (“The present invention provides a decoder that accepts transport
`
`bitstreams up to 40 Mbits per second.”); 5:46-51 (“The present invention provides
`
`a video decoder that decodes MPEG-1 and MPEG-2 Main Profile and Main Level
`
`bitstreams. The present invention provides an audio decoder that decodes MPEG-
`
`1 Layer I and II and MPEG-2 Multichannel bitstreams.”); 9:7-13 (“As depicted
`
`27
`
`
`
`inside the dashed line portion of FIG. 1B, this circuit consists of a transport packet
`
`parser (TPP) block or module 210 that includes a bitstream decoder or descrambler
`
`212 and clock recovery circuitry 214, . . . an audio/video (A/V) core block 250 that
`
`includes an MPEG-2 audio decoder 254 and an MPEG-2 video decoder 252.”).]
`
`42. For example, Chauvel discloses that the “MPEG2 transport stream
`
`parser (TPP) receives the MPEG transport stream and selects video, audio or
`
`services information packets. After decoding, the packets are stored to memory
`
`buffers to form a data stream. The audio decoder 254 processes the MPEG audio
`
`stream and produces an analog audio signal. The video decoder 252 decompresses
`
`the MPEG video and generates a video sequence.” [SE1004 at 22:25-31; 21:47
`
`(“The TPP Module 210 parses transport bitstreams”).] Further, for example,
`
`Chauvel discloses graphics processing via “an on screen display (OSD) controller
`
`block 270 to mix graphics and video.” [SE1004 at 9:14-15; 6:43-46 (“It is an
`
`object of the present invention to provide an OSD processor that enables mixture
`
`of OSD and video data with transparent BitBLT hardware that accelerates memory
`
`block move.”).]
`
`43.
`
`In addition, Chauvel discloses that the components described above as
`
`corresponding to the claimed decoder subsystem are communicatively connected
`
`to the processor. For example, Figure 1B of Chauvel shows data bus 330
`
`connecting the ARM processor 220 to each of the TPP 210 and A/V Core 250,
`
`28
`
`
`
`which is connected to the OSD module 270. [SE1004 at 9:30-32 (“There may also
`
`be seen an internal 32 bit address bus 320 that interconnects the blocks and an
`
`internal 32 bit data bus 330 that interconnects the blocks.”).] Thus, a POSITA
`
`would have understood that the TPP 210, the A/V Core 250, and the OSD module
`
`270 are communicatively connected to the ARM processor 220 at least via the data
`
`bus 330 because Chauvel discloses a data bus interconnecting those components.
`
`[SE1004, FIG. 18B (annotated and reproduced below).]
`
`[SE1004, FIG. 18B (annotated).]
`
`
`
`29
`
`
`
`[1.e] a media switch communicatively connected to the decoder subsystem, the
`media switch operative to interface a plurality of system components and
`operates asynchronously from the processor,
`44. Chauvel discloses a Traffic Controller, a 1394 interface, several
`
`peripheral components (e.g., optional RAM 300-1, EEPROM 300-2, Front End
`
`Control 300-5, and Extra Peripheral 300-7) and communication coprocessors,
`
`which collectively correspond to the claimed media switch, connected to the
`
`decoder subsystem by a data bus. [SE1004 at 9:30-32 (“There may also be seen an
`
`internal 32 bit address bus 320 that interconnects the blocks and an internal 32 bit
`
`data bus 330 that interconnects the blocks.”); FIG. 1B (annotated and provided
`
`below).] Referring to annotated FIG. 18B above, Chauvel shows that Traffic
`
`Controller 310, as part of a media switch (described in more detail below) is
`
`communicatively connected to the audio/video decoders 250, as part of the decoder
`
`subsystem. SE1004, FIGs. 1B and 18B.
`
`45.
`
`In addition, Chauvel discloses a Traffic Controller 310 that is
`
`operative to interface
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
