IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`
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`
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`David Locket, et al..
`In re Patent of:
`7,558,472 Attorney Docket No.: 39843-0038IP2
`U.S. Patent No.:
`July 7, 2009
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`Issue Date:
`Appl. Serial No.: 09/935,426
`
`Filing Date:
`Aug. 22, 2001
`
`Title:
`Multimedia Signal Processing System
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`
`DECLARATION OF JEFFREY J. RODRIGUEZ, PhD
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`1
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`SAMSUNG 1003
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`
`
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`
`
`David Locket, et al..
`In re Patent of:
`7,558,472 Attorney Docket No.: 39843-0038IP2
`U.S. Patent No.:
`July 7, 2009
`
`Issue Date:
`Appl. Serial No.: 09/935,426
`
`Filing Date:
`Aug. 22, 2001
`
`Title:
`Multimedia Signal Processing System
`
`
`DECLARATION OF JEFFREY J. RODRIGUEZ, PhD
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`1
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`SAMSUNG 1003
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`I, Jeffrey J. Rodriguez, Ph.D., of La Jolla, California, declare that:
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`I.
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`QUALIFICATIONS AND BACKGROUND INFORMATION
`1.
`I am currently a faculty member in the Dept. of Electrical and
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`Computer Engineering, Director of the Signal and Image Laboratory (SaIL), and a
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`faculty member in the Biomedical Engineering Graduate Interdisciplinary Program
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`at the University of Arizona. A copy of my curriculum vitae, which describes in
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`further detail my qualifications, employment history, honors, awards, professional
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`associations, presentations, and publications is attached hereto as Exhibit 1.
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`2. My formal education includes a bachelor's degree in Electrical
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`Engineering from the University of Texas at Austin in May 1984, a master’s
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`degree in Electrical Engineering from Massachusetts Institute of Technology in
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`June 1986, and I earned a Ph.D. degree in Electrical Engineering from the
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`University of Texas at Austin in May 1990.
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`3.
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`Since 1990, I have been a faculty member in the Department of
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`Electrical and Computer Engineering at the University of Arizona, where I hold or
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`have held the following positions: (a) Tenured Associate Professor of Electrical
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`and Computer Engineering (1997-present), (b) Director of the Signal and Image
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`Laboratory (1990-present), (c) Faculty member in the Biomedical Engineering
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`Interdisciplinary Program (2002-present), (d) Director of Graduate Studies for the
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`Department of Electrical and Computer Engineering (2000-2003, 2005-2016).
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`From 2003 to 2008, I served as Co-Director of Connection One, a National Science
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`Foundation industry/university cooperative research center focused on wired and
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`wireless communication circuits and systems. I teach courses at both the graduate
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`and undergraduate level, including Circuit Analysis, Signals and Systems, Signal
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`Processing, and Advanced Signal Processing. I have also taught other courses,
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`including Image Processing and Image Analysis. In 1992 I was awarded the
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`Outstanding Teaching Award by the IEEE and Eta Kappa Nu, given by the
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`students at the University of Arizona to one outstanding professor each year.
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`4. My research activity is generally directed to the design and analysis of
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`hardware (analog and digital) and software for electronic systems (including
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`microprocessor systems), especially for automated signal/image/video processing
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`applications.
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`5.
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`For example, one of my research projects included the development of
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`an electronic system for digital flow cytometry for real-time measurement of
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`biological cells. We designed and built a custom board including FIFOs for
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`buffering the signals, a microprocessor for FIFO control and real-time signal
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`analysis, a system bus for interfacing to SRAM, a dual-ported memory system for
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`handshaking and data communication between the processor and a PC via a PCI
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`bus.
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`6.
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`Another example of my research activity is the design and
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`development of a real-time video processing system for automated behavioral
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`analysis of zebrafish for use in ototoxicity assessment of drugs. The system we
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`designed and built includes an array of Raspberry Pi microcomputer systems
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`configured for parallel video capture of sixteen parallel zebrafish populations. Each
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`Raspberry Pi features a Broadcom system on a chip, which includes an ARM-
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`compatible CPU, a video graphics processing unit (GPU), and a memory system.
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`Data collected is then automatically transmitted to a high-performance cluster for
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`further video processing and analysis.
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`7.
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`I am a Senior Member of the Institute of Electrical and Electronics
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`Engineers (IEEE) and the IEEE Signal Processing Society. Over the years, I have
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`served as General Chair of several IEEE conferences, served on numerous IEEE
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`organizing committees, and held other positions on various IEEE committees, and
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`I have served as a technical reviewer for numerous journals and professional
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`conferences.
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`8.
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`In writing this Declaration, I have considered the following: my own
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`knowledge and experience, including my work experience in the field of
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`signal/image/video processing; my experience in teaching those subjects; and my
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`experience in working with others involved in those fields. In addition, I have
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`analyzed the following publications and materials, in addition to other materials I
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`cite in my declaration:
`
` U.S. Patent No. 7,558,472 (Exhibit SE1001), and its accompanying
`prosecution history (Exhibit SE1002);
` U.S. Patent No. 6,233,389 to Barton et al. (“the ’389 patent”, Exhibit
`SE1004), and Prosecution History of Ex Parte Reexamination of
`claims 31 and 61 of the ’389 patent (Serial No. 90/009329) (Exhibit
`SE1012);
` U. S. Patent Provisional Application No. 60/226,856 (“the ’856
`provisional”, Exhibit SE1005);
` U.S. Patent No. 6,853,385 to MacInnis et al. (“MacInnis”, Exhibit
`SE1006) and U.S. Patent Application Publication No. 2005/0122335
`to MacInnis et al. (Exhibit SE1008);
` TIVO’s P.R. 4-2 Disclosure (Exhibit SE1007);
` International Publication No. WO 00/24192 to Meandzija et al.
`(“Meandzija”, Exhibit SE1009);
` Excerpts of the IEEE Standard Dictionary of Electrical and
`Electronics Terms, Sixth Edition (1996) (“IEEE Dictionary”, Exhibit
`SE1010).
` TIVO'S RESPONSES TO DEFENDANTS’ FIRST SET OF
`INTERROGATORIES (No. 18) (“TiVo Responses to
`Interrogatories”, Exhibit SE1011).
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`9.
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`Although this Declaration refers to selected portions of the cited
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`references for the sake of brevity, it should be understood that these are examples,
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`and that one of ordinary skill in the art would have viewed the references cited
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`herein in their entirety and in combination with other references cited herein or
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`cited within the references themselves. The references used in this Declaration,
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`therefore, should be viewed as being incorporated herein in their entirety.
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`10.
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`I am not, and never was, an employee of the Petitioner in this
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`proceeding, Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
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`I have been engaged in the present matter to provide my independent analysis of
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`the issues raised in the petition for inter partes review of the ’472 patent. I
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`received no compensation for this declaration beyond my normal hourly
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`compensation based on my time actually spent studying the matter, and I will not
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`receive any added compensation based on the outcome of this inter partes review
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`of the ’472 patent.
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`II. LEGAL PRINCIPLES
`A.
`
`Anticipation
`11.
`I have been informed that a patent claim is invalid as anticipated
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`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
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`is found either explicitly or inherently in a single prior art reference. Under the
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`principles of inherency, if the prior art necessarily functions in accordance with, or
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`includes the claimed limitations, it anticipates.
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`12.
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`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
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`if the claimed invention was known or used by others in the U.S., or was patented
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`or published anywhere, before the applicant’s invention. I further have been
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`informed that a claim is invalid under 35 U.S.C. § 102(b) if the invention was
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`patented or published anywhere, or was in public use, on sale, or offered for sale in
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`this country, more than one year prior to the filing date of the patent application.
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`And a claim is invalid, as I have been informed, under 35 U.S.C. § 102(e), if an
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`invention described by that claim was described in a U.S. patent granted on an
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`application for a patent by another that was filed in the U.S. before the date of
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`invention for such a claim.
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`B. Obviousness
`13.
`I have been informed that a patent claim is invalid as “obvious” under
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`35 U.S.C. § 103 in light of one or more prior art references if it would have been
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`obvious to a person of ordinary skill in the art at the time of the invention
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`(“POSITA”), taking into account (1) the scope and content of the prior art, (2) the
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`differences between the prior art and the claims, (3) the level of ordinary skill in
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`the art, and (4) any so called “secondary considerations” of non-obviousness,
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`which include: (i) “long felt need” for the claimed invention, (ii) commercial
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`success attributable to the claimed invention, (iii) unexpected results of the claimed
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`invention, and (iv) “copying” of the claimed invention by others.
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`14.
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`I have been informed that a claim can be obvious in light of a single
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`prior art reference or multiple prior art references. To be obvious in light of a
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`single prior art reference or multiple prior art references, there must be a reason to
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`modify the single prior art reference, or combine two or more references, in order
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`to achieve the claimed invention. This reason may come from a teaching,
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`suggestion, or motivation to combine, or may come from the reference or
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`references themselves, the knowledge or “common sense” of one skilled in the art,
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`or from the nature of the problem to be solved, and may be explicit or implicit
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`from the prior art as a whole. I have been informed that the combination of
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`familiar elements according to known methods is likely to be obvious when it does
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`no more than yield predictable results. I also understand it is improper to rely on
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`hindsight in making the obviousness determination.
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`C. Written Description Requirements
`15.
`I have been informed that a later-filed patent application may rely on
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`the filing date of an earlier provisional patent application or an earlier
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`non-provisional patent application only if the claim has written description support
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`in the specification of the earlier-filed application. To satisfy written description
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`support for a claim, the specification must convey with reasonable clarity to a
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`POSITA that, as of the filing date sought, the inventors were in possession of the
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`invention.
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`16.
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`I understand that for an earlier patent application to provide sufficient
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`written description for a claim in a later-filed patent application, the earlier patent
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`application must either actually or inherently disclose each and every claim
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`element of a claim in a later-filed patent application. I understand that the test for
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`written description is an objective inquiry into the four corners of the specification
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`from the perspective of a POSITA.
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`17.
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`I have been informed that to satisfy actual disclosure, a term recited in
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`the claim does not need to appear exactly the same in the specification. However,
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`entitlement to a filing date does not extend to subject matter which is not disclosed,
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`but would be obvious over what is expressly disclosed. Moreover, I have been
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`informed that the written description requirement is not satisfied if the disclosure
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`would lead a POSITA to speculate as to modifications that the inventor might have
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`envisioned, but failed to disclose.
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`18.
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`I have been informed that to satisfy inherent disclosure, the missing
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`descriptive matter must necessarily be present in the application’s specification
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`such that a POSITA would recognize such a disclosure. I understand that if there
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`are more than one undisclosed ways to interpret a claim element that is not actually
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`disclosed in an application’s specification, the missing descriptive matter would
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`not necessarily be present in the specification.
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`19.
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`I have been informed that if an earlier patent application does not
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`actually or inherently disclose each and every claim element of a claim in a later-
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`filed patent application, the earlier application does not provide sufficient written
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`description support for the claim, and the claim cannot rely on the filing date of the
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`earlier patent application.
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`20.
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`I have been informed that a later-filed Continuation-in-part (CIP)
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`application may claim priority to an earlier-filed parent application. The later-filed
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`CIP application may include new disclosures that are not actually or inherently
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`described in the earlier-filed parent application. If a claim recites a feature that is
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`supported by the CIP application but not by the earlier-filed parent application, the
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`claim cannot claim priority to the earlier-filed parent application. I have been
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`informed that different claims of a CIP application may receive different effective
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`filing dates depending on whether the recited features are supported by the parent
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`application(s).
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`III. OVERVIEW OF CONCLUSIONS FORMED
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`21. This expert Declaration explains the conclusions that I have formed
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`based on my analysis. To summarize those conclusions:
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` Based upon my knowledge and experience and my review of the prior
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`art publications listed above, I believe that at least claims 1, 12-16, 20,
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`22, 23, 30, and 32 of the ’472 patent are not supported by the ’389
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`patent, and therefore are not entitled to the ’389 patent filing date.
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` Based upon my knowledge and experience and my review of the prior
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`art publications listed above, I believe that at least claims 1, 12-16, 20,
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`22, 23, 30, and 32 of the ’472 patent are not supported by the ’856
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`provisional, and therefore are not entitled to the ’856 provisional
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`filing date.
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` Based upon my knowledge and experience and my review of the prior
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`art publications listed above, I believe that claims 1, 12-16, 20, and 32
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`of the ’472 patent are anticipated by MacInnis.
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` Based upon my knowledge and experience and my review of the prior
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`art publications listed above, I believe that claims 1, 12-16, 20, 30,
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`and 32 of the ’472 patent are rendered obvious by MacInnis.
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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` Based upon my knowledge and experience and my review of the prior
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`art publications listed above, I believe that claims 22 and 23 of the
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`’472 patent are rendered obvious by MacInnis in view of Meandzija.
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`IV. BACKGROUND
`A. Overview of the ’472 Patent
`22. The ’472 patent “relates to the real time capture, storage, and display
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`of television broadcast signals.” SE1001 at 1:18-20. Referring to FIG. 14 of the
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`’472 patent, a system board 1400 includes an input section 1401 that accepts an
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`input signal from a source — e.g., a television input stream. Id. at 4:29-41 and
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`13:18-24. The input section 1401 produces an MPEG transport stream, which is a
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`multiplex stream of data that supports video and audio feeds. Id. at 4:42-59. The
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`system board 1400 includes an output section 1402, which includes a CPU 1403, a
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`decoder/graphics subsystem 1404, and a media switch containing a media manager
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`1405. Id. at 13:24-60; claim 1. The CPU 1403 functions to initialize and control
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`operation of the various hardware components. Id. at 13:24-60. The
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`decoder/graphics subsystem 1404 accepts a transport stream delivered from the
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`input section 1401 over a transport stream interface 1406, and communicates with
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`the CPU 1403 by a first bus 1408. Id. The decoder/graphics subsystem 1404
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`decodes the transport stream received from the input section, and outputs the
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`Attorney Docket No. 39843-0038IP2
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`decoded stream as a video signal to a television set. Id. The media manager 1405
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`acts as a bridging element between system components. Id. In addition, the media
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`manager 1405 communicates with the decoder/graphics subsystem 1404 by a
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`second bus 1407, which may be a PCI bus, and saves the transport stream to a
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`storage subsystem. Id. The media manager 1405 includes an IDE (Integrated
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`Drive Electronics) host controller that provides encryption that can be applied to
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`the stored data. Id. at 15:8-34, 15:59-65. The media manager 1405 also includes a
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`PCI bus arbiter. Id.
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`Attorney Docket No. 39843-0038IP2
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`Declaration of Dr. Jeffrey J. Rodriguez
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`23. The media switch containing the media manager runs asynchronously
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`with the microprocessor CPU because the media manager includes a DMA
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`controller that moves large quantities of data with minimal intervention by the
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`CPU. Id. at 7:7-15; 15:20-34. Data may be stored to and retrieved from the
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`storage subsystem by DMA at the same time, based on program instructions from
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`the CPU. Id. at 7:7 – 8:34.
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`B.
`Person of Ordinary Skill in the Art
`24. Based on the foregoing and upon my experience in this area, a person
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`of ordinary skill in the art in this field at the time of invention (“POSITA”) would
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`have had a combination of experience and education in signal processing
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`component and/or signal processing system design. This typically would consist
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`of a minimum of a bachelor of science in electrical engineering, computer
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`engineering, or a related field plus 2-5 years of work, graduate study, and/or
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`research experience in the field of signal processing component and/or signal
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`processing system design. Additional education in a relevant field, such as
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`computer science, software engineering, or a related field, or additional industry
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`experience may compensate for a deficit in one of the other aspects of the
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`requirements stated above.
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`25. Based on my experiences, I have at least the level of skill of a
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`POSITA. The qualification of a POSITA would be the same at least for the period
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`between the ‘389 patent filing date and the ‘472 patent filing date.
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`V. CLAIM CONSTRUCTION
`26.
`I understand that, for purposes of my analysis in this inter partes
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`review proceeding, the terms appearing in the patent claims should be interpreted
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`according to their broadest reasonable construction in light of the specification of
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`the patent in which it appears. In that regard, I understand that the best indicator of
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`claim meaning is its usage in the context of the patent specification as understood
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`by a POSITA. I further understand that the words of the claims should be given
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`their plain meaning unless that meaning is inconsistent with the patent
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`specification or the patent’s history of examination before the Patent Office. I also
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`understand that the words of the claims should be interpreted as they would have
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`been interpreted by a POSITA.
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`27.
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`I also understand that in district court, Patent Owner has proposed
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`constructions for a number of claim terms of the ’472 patent. SE1007. I have been
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`informed that the claim construction standard for district court is different than,
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`and possibly narrower than, the broadest reasonable interpretation standard
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`(“BRI”). I understand that Patent Owner’s interpretation of the claim terms under
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`BRI will be at least as broad as Patent Owner’s interpretation of the claim terms in
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`district court. Thus, for the purpose of this proceeding, I am applying
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`constructions on the following terms that are at least as broad as the constructions
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`proposed by Patent Owner, including:
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`
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`1
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`Claim Term
`transport stream
`(claims 1, 12, 15, 16)
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`BRI Construction
`“a stream of data that includes interleaved video
`and audio segments.”
`SE1007 at 13; see also SE1001 at 4:42-59 and
`14:29-51.
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`16
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`media switch
`(claim 1)
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`multimedia data stream
`processor
`(claim 1)
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`transport interface
`(claim 12)
`
`transport stream
`interface
`(claim 15)
`front panel
`navigation cluster
`(claim 30)
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`“hardware and/or code that mediates between a
`microprocessor CPU, hard-disk or storage
`device, and memory.”
`SE1007 at 12; see also SE1001 at 4:60-67 and
`7:48-57.
`“media switch/media manager processor(s) that
`processes multimedia data.”
`SE1007 at 13; see also SE1001 at 15:8-34 and
`18:18 – 19:21.
`“an interface that receives transport streams.”
`SE1007 at 13; see also SE1001 at 13:61 – 14:59
`and 16:55 – 17:48.
`“an interface that receives transport streams.”
`SE1007 at 13; see also SE1001 at 13:18-38.
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`“exterior buttons or keys to control the device.”
`SE1007 at 13; see also SE1001 at 15:8-34,
`15:66 – 16:10, and 17:66 – 18:14.
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`2
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`3
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`4
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`5
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`6
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`28. Claim 1 recites an output section that includes a media switch that is
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`operative to interface a plurality of system components and operates
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`asynchronously from the processor, where the “media switch comprises a media
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`manager.” The media switch as recited in claim 1 does not recite any additional
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`element other than the media manager. The ’472 patent discloses that “[w]hile the
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`media manager provides a number of functions, its major function is that of a
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`bridging element between system components, due to the number and type of I/O
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`functions it incorporates.” SE1001 at col. 13:39-60. Accordingly, it is reasonable
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`to consider the term “media manager” as broad enough to encompass “the portion
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`of the output section that interfaces with a plurality of system components.” For
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`all other terms, I have assumed plain and ordinary meaning.
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`29.
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`I have performed no analysis as to whether the above constructions
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`are correct under the standard in district court, and consequently, offer no opinion
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`on that subject.
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`VI. ANALYSIS OF WRITTEN DESCRIPTION
`30. The ’389 patent and the ’472 patent share common disclosures from
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`Fig. 1 through Fig. 13, and the corresponding descriptions (SE1001, col. 4:18 –
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`col. 13:17). However, Fig. 14 to Fig. 22, and the corresponding descriptions
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`(SE1001, col. 13:18 – col. 19:28) were newly added in the ’472 patent.
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`31.
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`I note that the portion of the ’856 provisional that describes a media
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`processor is included in a proposal titled “Multi channel system independent media
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`processor.” SE1005 at 27-30. According to the three listed individuals that
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`submitted this proposal (Dave Lockette, Andy Goodman, and Jean Kao), the
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`proposed media processor includes five blocks: system interface, media stream
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`identifier, media stream processor core, multi-channel state engine, and media
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`identification generator. Id. at 27. The system interface provides “a connection or
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`window for media process to [observe] the system bus,” and also provides “a way
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`[to] send back media processed result as well as a programming interface.” Id. at
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`18
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`28. The media stream identifier “[distinguishes] media stream data from other data
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`on the bus.” Id. The media stream processor core “[provides] tivo media
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`streaming function,” where “multiple streams are [processed] simultaneously.” Id.
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`at 28-29. The states of different media streams are saved and reloaded, presumably
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`by the multi-channel state engine. Id. The media identification generator “[uses]
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`information such as source and destination of the stream to identify whether the
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`data on the bus should be processor.” Id. at 28.
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`A. Claim 1
`32. Claim 1 recites a media switch that comprises a media manager. The
`
`media manager includes a host controller, a DMA controller, a bus arbiter, and a
`
`multimedia data stream processor. I find the term “media manager” in several
`
`instances in the’472 patent. SE1001, FIGS. 14, 15, 18, 19B, 20B, and 21B and at
`
`13:39-60, 15:8-65, and 18:18 – 19:21. As described in the ’472 patent, a media
`
`manager includes the following:
`
` an IDE host controller, with data encryption;
` a DMA controller;
` IR receiver/transmitter interface;
` multiple UART's (Universal Asynchronous Receiver/Transmitter);
` multiple I2C (Inter-IC) buses;
` multiple GPIO's (General Purpose I/O's);
` a PCI bus arbiter;
`
`19
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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` an MPEG-2 media stream processor;
` a PCM (Pulse Code Modulation) audio mixer;
` a high-speed transport output interface;
` a fan speed control; and
` front panel keyboard matrix scanner.
`(SE1001 at 15:8-34).
`33. The ’472 patent therefore appears to disclose “a DMA controller.” A
`
`POSITA would have recognized that an IDE (Integrated Drive Electronics) host
`
`controller is a type of a host controller. A POSITA would have recognized that a
`
`PCI (Peripheral Component Interconnect) bus arbiter is a type of a bus arbiter.
`
`34. The ’472 patent discloses that the media manager 1405 includes “an
`
`MPEG-2 media stream processor.” Id. The ’472 patent discloses that “the media
`
`manager also mediates the transfer of media streams between the CPU 1403,
`
`memory 1501, and the hard drive 1505. This is accomplished through the action of
`
`the media stream processor and the high-speed transport output interface.” Id. at
`
`15:43-46. Referring to FIG. 22, the ’472 patent discloses a “multi-channel media
`
`stream processor” that includes:
`
` a system interface 2201;
` a media stream identifier 2202;
` a media stream processor core 2203;
` a multi-channel state engine 2204; and
`
`20
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
`
`
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` a media stream identification generator 2205.
`(Id. at 18:18 – 19:21).
`35. As disclosed in the ’472 patent, the multi-channel media stream
`
`processor upgrades a PVR's media stream processor capability from single-channel
`
`to multi-channel. Id.
`
`36. By contrast, several terms do not appear in the ’389 patent, including
`
`“media manager,” “host controller,” “bus arbiter,” and “multimedia data stream
`
`processor.” These terms are not present anywhere in the ’389 patent specification.
`
`The ’389 patent discloses a media switch, but does not disclose a “media
`
`manager.” As discussed above, the broadest reasonable interpretation for the term
`
`“media manager” encompasses “the portion of the media switch that has a host
`
`processor, DMA controller, bus arbiter and multimedia data stream processor.”
`
`SE1007 at 13. The ’389 patent does not describe a media switch that includes a
`
`bus arbiter.
`
`37.
`
`In the document titled “TIVO'S FOURTH SUPPLEMENTAL
`
`OBJECTIONS AND RESPONSES TO DEFENDANTS' FIRST SET OF
`
`INTERROGATORIES (No. 18)” (SE1011), Patent Owner has stated that the ’389
`
`patent specification supports the claim elements from the ’472 patent. SE1011 at
`
`11.
`
`21
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`
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`
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`38. Patent Owner stated that the term “a host controller” is supported at
`
`least by col 6:59-63, 3:65-4:2, 6:16-25, 7:5-7, Fig 1, Fig 7, Fig 13 of the ’389
`
`patent. Id. at 12. The term “host controller” does not appear in the cited portions
`
`and the cited figures of the ’389 patent. Id. Patent Owner did not explain why a
`
`host controller must necessarily be present in the cited portions of the ’389 patent.
`
`39. Patent Owner stated that the term “bus arbiter” is supported at least by
`
`Abstract, Fig 7, Col. 2:22-33, 6:59-7:4, 3:62-65. SE1011 at 12. The term “bus
`
`arbiter” does not appear in the cited portions of the ’389 patent. The referenced
`
`figures similarly do not show a bus arbiter in the media switch. Patent Owner did
`
`not explain why a bus arbiter must necessarily be present in the cited portions of
`
`the ’389 patent.
`
`40.
`
`In fact, a POSITA would have understood that a function of a “bus
`
`arbiter” is to grant control of a bus among multiple requesters, and a POSITA
`
`would have recognized that a parallel arbitration is one way to control the access to
`
`a bus without using a bus arbiter. SE1010 at 4. Thus, a POSITA would have
`
`understood that a bus arbiter does not necessarily have to be present in a media
`
`switch that may participate in bus arbitration. A POSITA therefore would have
`
`understood that the ’389 patent does not actually or inherently disclose a bus
`
`arbiter.
`
`22
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`
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
`
`
`
`41. Claim 1 recites an output section that includes a media switch. Patent
`
`Owner stated that the term “output section” is supported at least by col. 3:30-60,
`
`4:3-12, 6:25-45, 7:28-45, 11:28-39, Fig 1, Fig 2, Fig 3, claims 1, 2, 30, 32, 33, 60
`
`of the ’389 patent. SE1011 at 12. The ’389 patent discloses that “[i]nput streams
`
`are converted to an MPEG stream and sent to the Media Switch 102. The Media
`
`Switch 102 buffers the MPEG stream into memory. It then performs two
`
`operations if the user is watching real time TV: the stream is sent to the Output
`
`Section 103 and it is written simultaneously to the hard disk or storage device
`
`105.” SE1004 at 3:62 – 4:2. The ’389 patent thus discloses that the media switch
`
`sends a transport stream to the output section, and does not disclose an output
`
`section that includes a media switch. I note that the text of the ’389 patent uses the
`
`term “output section 103” while FIG. 1 shows an output module 103. Thus, I
`
`assume the ’389 patent uses the terms “output section” and “output module”
`
`interchangeably. Referring to annotated FIG. 1 and FIG. 2 below, the ’389 patent
`
`discloses that the output section is connected to the media switch, and do not show
`
`that the media switch as being included in the output section. Moreover,
`
`independent claims 1 and 31 of the ’389 patent do not recite an output section that
`
`includes a media switch. A POSITA therefore would have understood that the
`
`23
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
`
`
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`’389 patent does not actually or inherently disclose an output section that includes
`
`a media switch.
`
`
`
`24
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`
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
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`
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`
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`42. Accordingly, the ’389 patent does not convey with reasonable clarity
`
`to a POSITA that, as of the filing date of the ’389 patent, the inventors of the ’472
`
`patent were in possession of the invention recited in claim 1.
`
`43. The ’856 provisional does not disclose the bus arbiter recited in claim
`
`1 and does not disclose the specific arrangement of components that is recited in
`
`claim 1. In fact, a POSITA would have understood that a function of a “bus
`
`arbiter” is to grant control of a bus among multiple requesters, and a POSITA
`
`would have recognized that a parallel arbitration is one way to control the access to
`
`a bus without using a bus arbiter. SE1010 at 4. Thus, a POSITA would have
`
`25
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`
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`Attorney Docket No. 39843-0038IP2
`IPR of U.S. Patent No. 7,558,472
`Declaration of Dr. Jeffrey J. Rodriguez
`
`
`
`understood that a bus arbiter d
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