United States Patent [19]
`Heller et a1.
`
`[11] Patent Number:
`
`4,563,702
`
`[45] Date of Patent:
`
`Jan. 7, 1986
`
`[54] VIDEO SIGNAL SCRAMBIJNG AND
`DWI} SYSTEMS
`
`[75]
`
`Inventors:
`
`Jerrold A. Heller; Woo H. Pails, both
`of San Diego. Calif.
`
`[73] Assignee: M/A-COM Linkabit, Inc... San
`Diego, Calif.
`
`[21] App]. No; 498,875
`
`[22] Filed:
`
`May 27, 1983
`
`HMN 7/16; H04L 9/00
`Int. CL‘
`[51]
`
`358/119; 178/2105
`[52} US. Cl.
`[58] Field of Search 358/119; 178/2204,
`178/2205, 22.06
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`360/3
`3.8?2,503 3/1975 Shutterly ..
`.. 353/124
`4,0a2,912 5/1971 Pircs ......
`
`4,070,693
`1/1973 Shutterly
`.. 358/123
`4,221,931
`9/1980 Seiler
`179/1.5R
`5/1931 Shutter1y358/121
`4,255,243
`4,405,942 9/1933 Block etal.
`358/119
`
`Primal? Examiner—S. C. Bnczinsici
`Assistant Examiner—Linda J. Wallace
`Attorney, Agent, or Finn—Baker, Muham, Callan £5
`Jester
`
`[57}
`
`ABSTRACT
`
`Systems for scrambling and descrambling video infor-
`mation lines. The scrambling system includes a m-
`ory; a storage system for sequentially storing groups of
`
`four video information lines in the memory; and a re-
`trieval means for forming groups of four scrambled
`video information lines by retrieving the stored video
`information from the memory in a sequence difierent
`from the sequence within the stored group in which the
`mfonnation was stored. The retrieval system forms the
`scrambled video information lines by retrieving a por-
`tion of a first stored video information line from a first
`position therein to form a portion of a first scrambled
`video information line occupying a second position
`therein; retrieving a portion of the first stored video
`information line from the corresponding second posi-
`tion therein to form a portion of a second scrambled
`video information line occupying a position therein
`other than the corresponding second position; and
`forming the portion of the first scrambled video infor-
`mation line occupying the corresponding first position
`therein by retrieving a portion of a stored video infor-
`mation line other than the first stored video information
`line from a position therein other than the correspond-
`ing first position. The sequence of formation of the
`scrambled lines, the respective sizes of the retrieved
`portions, and the combinations of stored video lines
`within the stored groups for forming the first and sec-
`ond scrambled video lines are varied from one group to
`the next in response to a keystream of control bits. The
`descrambling system functions conversely to the scram-
`bling system.
`'
`
`25 Claims, 8 Drawing Figures
`
`
`
`DESCRI‘MBLED SIGNAL.
`
`STORED SIGNfiL
`
`SCRAMBLED SIGN“.
`
`Page 1
`
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`|PR2016-01520
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`Apple v. PMC
`IPR2016-01520
`Page 1
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`

`

`U. S. Patent
`
`Jan. 7,1986
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`IPR2016-01520
`Page 2
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`

`

`Jan. 7, 1986
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`|PR2016-01520
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`Apple v. PMC
`IPR2016-01520
`Page 3
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`

`

`1 US. Patent
`
`Jan. 7,1986
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`PMC Exhibit 2202
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`Apple v. PMC
`|PR2016-01520
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`PMC Exhibit 2202
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`

`U. S. Patent
`
`Jan. 7,1986
`
`Sheet 4 of 6
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`4,563,702
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`
`Apple v. [PMC
`|PR2016-01520
`
`Page 5
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`PMC Exhibit 2202
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`IPR2016-01520
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`

`U. S. Patent
`
`Jan. 7
`
`1986
`
`Sheet 5 of 6
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`4,563,702
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`Apple v. PMC
`IPR2016-01520
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`

`U. 8. Patent
`
`Jan. 7,1986
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`Sheet 6 of6
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`4,563,702
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`PMC Exhibit 2202
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`Apple v. PMC
`|PR2016-01520
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`Page 7
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`PMC Exhibit 2202
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`

`1
`
`VIDEO SIGNAL SCRAMBLING AND
`DESCRAMBLING SYSTEMS
`
`4,563,702
`
`BACKGROUND OF THE INVENTION
`
`I s
`
`2
`control bits for designating the sequence of formation of
`the scrambled video information lines in the formed
`group. Preferably the keystream further includes a third
`set of control bits for designating the respective lengths
`of the retrieved portions in each combination of stored
`video information lines in response to which, the re-
`spective lengths are varied from one combination to the
`next by the retrieval system.
`In another aspect, the present invention provides a
`system for descrambling scrambled video information
`lines. The system includes a memory; a storage system
`for sequentially storing groups of a plural predeter-
`mined number of the scrambled video information lines
`in the memory; and a retrieval system for sequentially
`forming groups of a corresponding number of descram-
`bled video information lines by retrieving the stored
`video information from the memory in a sequence dif-
`ferent from the sequence within the stored group in
`which the information was stored. The retrieval system
`forms the descrambled video information lines by re-
`trieving a portion of a first scrambled video information
`linc'from a first position therein to form a portion of a
`first descrambled video information line occupying a
`second position therein; retrieving a portion of the first
`scrambled video information line from the correspond-
`ing second position therein to form a portion of a sec-
`ond descrambled video information line occupying a
`position therein other than the corresponding second
`position, and forming the portion of the first descram-
`bled video information line occupying the correspond-
`ing first position therein by retrieving a portion of a
`scrambled video information line other than the first
`scrambled video information line from a position
`therein other than the corresponding first position. The
`retrieval system, controls the formation of the descram-
`bled lines in response to a keystream. Each frame of the
`keystream includes a first set of control bits for desig-
`nating combinations of descrambled video information
`lines as destinations for information stored in corre-
`sponding combinations of scrambled video information
`lines in the stored group. The keystream that is used for
`descramng the scrambled video information signal is
`identical to the keystream that is used for scrambling
`the original video information signal. Accordingly, the
`keystresm preferably further includes a second set of
`control bits for designating the sequence of retrieval of
`information from the scrambled video information lines
`in the stored group and a third set of control bits for
`designating the respective lengths of the retrieved por-
`tions in the combinations of descrambled video informa-
`tion lines.
`
`10
`
`15
`
`20
`
`25
`
`35
`
`45
`
`50
`
`The present invention generally pertains to ‘video
`signal processing and is particularly directed to im—
`proved video signal scrambling and descrambling sys-
`tems.
`
`One technique for scrambling video signals is de-
`scribed in US. Pat. No. 4,070,693 to Shutterly. In ac-
`cordance with the technique described therein, video
`information is scrambled by storing a video information
`line in a memory and then forming a scrambled video
`information line by retrieving the video information
`from the memory in a sequence different from the se-
`quence within the line in which the information was
`stored. The portion at the beginning position of the
`stored video information line is retrieved at the last
`position of the scrambled video information line and the
`portion at the last position of the stored video informa-
`tion line is retrieved at the beginning position of the
`scrambled video information line. The respective
`lengths of the retrieved portions are varied from one
`line to the next in response to a randomly generated
`coded control signal.
`SUMMARY OF THE INVENTION
`The present invention provides more complex scram-
`bled video signal
`line formation and thereby better
`scrambles the video signal.
`In one aspect, the present invention provides a system
`for scrambling video information lines. The scrambling
`system includes a memory; a storage system for sequen-
`tially storing groups of a plural predetermined number
`of the video information lines in the memory; and a
`retrieval system for forming a corresponding number of
`scrambled video information lines by retrieving the
`stored video information from the memory in a se-
`quence difierent from the sequence within the stored
`group in which the information was stored. The re-
`trieval system forms the scrambled video information
`lines by retrieving a portion of a first stored video infor-
`mation line from a first position therein to form a por-
`tion ofa first scrambled video information line occupy-
`ing a second position therein; retrieving a portion of the
`first stored video information line from the correspond-
`ing second position therein to form a portion of a sec—
`ond scrambled video information line occupying a posi-
`tion therein other than the corresponding second posi-
`tion; and forming the portion of the first scrambled
`video information line occupying the corresponding
`first position therein by retrieving a portion of a stored
`video information line other than the first stored video
`information line from a position therein other than the
`corresponding first position. Preferably the retrieval
`system varies the sequence of formation of the scram-
`bled lines from one retrieved group to the next; and the
`retrieval system also varies the combinations of stored
`video information lines within the stored groups for
`forming the first and second scrambled video informa-
`tion lines from one group to the next. The retrieval
`system controls the formation of the scrambled lines in
`response to a keystream. Each frame of the kcystream
`includes a first set of control bits for designating combi—
`nations of stored video information lines as sources for
`corresponding combinations of scrambled video infor-
`mation lines in the formed group, and a second set of
`
`55
`
`Additional features of the present invention are de-
`scribed in relation to the description of the preferred
`embodiment.
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`60
`
`65
`
`FIG. 1 is a block diagram of a video signal scrambling
`system in accordance with the present invention.
`FIG. 2 is a diagram showing an explemplary relation-
`ship between stored video signal lines. scrambled video
`signal lines and descrambled video signal lines.
`FIG. 3 is a block diagram of the waveshaping filler
`included in the video processor of FIG. 2.
`FIGS. 40, 4b and 40 illustrates the waveforms of
`various lines of the unscrambled and scrambled video
`signals.
`
`Page 8
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`4,563,702
`
`3
`FIG. 5 is a block diagram of a video signal descram-
`bling system in accordance with the present invention.
`FIG. 6 is a block diagram of the sync detection circuit
`included in the system of FIG. 5.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`4
`field, and the fourth group includes the next four con-
`secutive even-numbered lines from the same video field.
`One group of odd-numbered lines is stored in the mem-
`ory 53 while the information from the previously-stored
`group of odd—numbered lines is retrieved from the mem-
`ory 53 to form a four-line group of odd-numbered
`scrambled video information lines on line 66. Likewise,
`one group of evenwnumbered lines is stored in the mem-
`ory 53 while the information from the previously stored
`group of even-numbered lines is retrieved from the
`memory to form a four-line group of even-numbered
`scrambled video information lines on line 66. Video
`scrambling is accomplished by retrieving the active
`video information from the memory in a sequence dif-
`ferent from that in which it was stored.
`The address counters 54 provide the respective ad-
`dresses on line 67 to the memory 53 for storing and
`retrieving video information. These addresses are pro-
`vided to the address counters 54 on line 68 via the ad-
`dress FIFO queue 55 and line 69 from the control pro-
`cessor 48 in accordance with the unique keystream
`provided to the control processor 48 on line 44.
`The line buffer controller 56 provides clocking and
`control signals on lines 70 for synchronizing the opera-
`tions of the address FIFO queue 55, the address count-
`ers 54 and the memory 53 in accordance with clocking
`and synchronization control signals provided on line 71
`by the control processor 48. The control processor 68
`provides the clocking and synchronization control sig-
`nals on lines 71 in response to the clocking and synchro-
`nization control signals received on lines 64 from the
`sync detection circuit 51.
`FIG. 2 illustrates an exemplary embodiment of
`scrambling video information in accordance with the
`present invention. Scrambling is accomplished within
`four-line groups. Two control bits of the keystream on
`line 44 designate which lines within a given, stored
`four-line group are to be paired for forming a corre-
`sponding pair of scrambled video information lines. In
`the embodiment of FIG. 2, lines 1 and 4 make up one
`pair in the stored group and the other pair in the stored
`group is made up of lines 2 and 3. Although each stored
`active video information line actually contains sixty-
`two twelve-sample segments, in FIG. 2 each stored line
`is shown as having only eight segments for simplicity of
`illustration. In the example of FIG. 2, the segments of
`stored line 1 are designated “a” through “h”, and the
`segments of stored line 4 are designated “m” through
`“t”. The relative lengths of the retrieved portions in
`each pair of scrambled lines is designated by six control
`bits in the keystream, which indicate a cutpoint “X” as
`being after a given number of segments from the begin-
`ning of the line.
`Another five control bits of the keystream On line 44
`designate the sequence within a four-line group in
`which the scrambled lines are formed. Twanty-four
`different sequences are possible. Thus nineteen bits of
`the keystream are used every four video line times to
`select one of 3X62><24=276,768 possible scrambling
`patterns. Descramhling requires local generation of the
`identical keystrearn in the descrambler. In the preferred
`embodiment, the control processor 48 is programmed to
`provide retrieval addresses on line 69 to the address
`FIFO queue 55 in such a sequence that (a) the left por—
`tion on one line of a corresponding scrambled pair is
`retrieved from the right portion of one line of a desig-
`nated stored pair; (b) the right portion of the one line of
`the corresponding scrambled pair is retrieved from the
`
`l0
`
`25
`
`30
`
`35
`
`The preferred embodiments of the video scrambling
`and descrambling systems described hemin are used in
`the preferred embodiment of the subscription television
`system is described in a co-pending U.S. patent applica-
`tion Ser. No. 498,800 by Klein S. Gilhousen and Charles
`F. Newby, Jr. filed May 27, 1983 for “Key Signal En-
`cryption and Distribution System for Controlling
`Scrambling and Selective, Remote Descrambling of 15
`Television Signals," wherein they are referred to as a
`“scrambler signal processor” and a “descrarnbler signal
`processor", respectively. The same reference numerals
`are used for like components described both therein and
`herein.
`Referring to FIG. I, the preferred embodiment of the
`video scrambling system includes a control processor
`48, an audio precessor 49, a video amplifier 5|], a sync
`detection circuit 51, an analog-to—digital (A/D) con-
`verter 52, a video line buffer memory 53, address count-
`ers 54, an address FIFO (first—in/first-out) queue 55, a
`line buffer controller 56, a wave shaping filter 57, a
`burst gerator 58, a sync generator 59, a reference
`pattern generator 60, a multiplier (MUX) 61 and a digi-
`tal-to-analog (D/A) converter 62. The Operation of the
`control processor 48 is controlled by control signals
`provided on line 2|] by a control computer (not shown).
`A video signal on line 45 is scrambled by the Video
`scrambling system of FIG. 2 in accordance with one
`portion of each frame of a unique received keystream
`on line 44 from a scrambler key distribution system (not
`shown). The scrambler key distribution system is de-
`scribed in the aforementioned patent application by
`« Gilhousen et. al. the entire disclosure of which is incor-
`porated herein by reference thereto.
`The video amplifier 50 amplifies the video signal on
`line 45 and filters the same to remove any extraneous or
`harmonic signals. The amplified and filtered video sig-
`nal is provided on line 63 to the A/D converter 52 and
`the sync detection circuit 51. The sync detection circuit
`51 detects the vertical and horizontal synchronization
`signals in the video signal on line 63 and responds
`thereto by providing synchronization control and
`clocking signals on lines 64 to the control processor 48.
`Among these clocking signals is a 14.32 MHz signal,
`which is at four times the color subcarrier frequency of
`an NTSC video signal. and which is also provided. by
`the sync detection circuit 51 on line 64a to clock the
`A/D converter 52.
`The A/D converter 52 converts the amplified video
`signal on line 63 into a digital video information signal
`on line 65 at the sampling rate of 14.32 MHz to provide
`910 8-bit samples per video line. The active video infor-
`mation corresponds to the 744 samples in each line.
`The video line buffer memory 53 stores the digital
`video signal on line 65 in four groups of four video
`information lines each. Each stored video information
`line includes 744 8-bit samples of active video informa-
`tion. A first group includes four consecutive odd-num-
`hered lines from the same video field. A second group
`includes the next four consecutive odd numbered lines
`from the same video field. A third group includes four
`consecutive even-numbered lines from the same video
`
`45
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`50
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`Page 9
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`5
`left portion of the other line of the designated stored
`pair; (c) the left portion of the other line of the corre-
`sponding scrambled pair is retrieved from the right
`portion of the other line of the designated stored pair;
`and (d) the right portion of the other line of the corre-
`sponding scrambled pair is retrieved from the left por—
`tion of the one line of the designated stored pair. ln
`alternative preferred embodiments, the cuntrol proces-
`sor may be programmed to effect alternative retrieval
`combinations between the designated stored line pairs
`and the corresponding scrambled line pairs.
`In the example of FIG. 2, Scrambled lines 2 and 4 are
`formed by (a) retrieving a portion consisting of seg-
`mentsabaudcfromtheleftendofstoredlinelto
`form the right end of scrambled line 2; (b) retrieVing a.
`portion consisting of segments c. d. e, f, g and h from the
`right end of stored line 1 to form the left end of scram-
`bled line 4; (c) retrieving a portion consisting of seg-
`mentsm,nandofrontthelel’tendofstoredline-‘lto
`form the right end of scrambled line 4; and (d) retriev—
`ing a portion consisting of segments 0, p, q, r, s and t
`from the right end of stored line 4 to form the left end
`of scrambled line 2. It is noted that the combinations of
`scrambled lines are formed to include overlapping seg—
`ments from the stored lines, to. segment c from stored
`line 1 and segment 0 from stored line 4. This procedure
`reduces the possibility of overshoot and makes it more
`difficult for a pirate attempting to dmcramble the
`scrambled signal to be able to determine the location of
`the cutpoint X.
`To further obsoure the location of the cutpoint X, the
`waveshaping filter 57 adjusts the values of the adjacent
`extremities of the retrieved portions of each scrambled
`line to smooth over any fast rise-time edges. For exam-
`ple, in scrambled line 2 shown in FIG. 2, the values of
`the adjacent extremities of segments t and a are ad-
`justed.
`Referring to FIG. 3, the waveshaping filter 57 in-
`ciudes an input register 72, an X-address register 73, a
`counter '74, a Y PROM (programmable read only mem-
`ory) 75, an X PROM 1'6, a Y output register 77, an X
`output registet 78, a binary adder 79, a first delay regis-
`ter 80, a second delay register 81, a multiplexer 82 and
`an output register 83.
`The waveshaping filter of FIG. 3 provides a smooth
`transition between two eight-bit samples in a digital
`data stream separated by six clock periods. The process
`involves generating a plurality of interpolated values In
`between the two samples X and Y in different adjacent
`retrieved portions of each scrambled line and inserting
`samples having the interpolated values in the stream of
`data between the X and Y samples.
`These interpolated values In effectively smooth out
`any abrupt differences between the X and Y samples.
`Start values can be greater in value than step values, or
`vice versa.
`The concept involved in accomplishing the wave-
`shaping is the implementation of the algebraic function:
`
`5
`
`10
`
`IS
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`Iu=[(T—n)f?1X+(n/DY
`
`(Eq- 1)
`
`60
`
`“fhere T is the total number of clock cycles between
`start and stop samples; and N is the positional number of
`the inserted interpolated sample. The total number of
`inserted samples is T- l.
`'
`The waveshaping filter of FIG. 3 implements a spe-
`cial case of Equation 1, wherein
`
`65
`
`4,563,702
`
`n=3nx+bnrn
`
`6
`
`(Bq- 2)
`
`Where Yn=the comparison sample value.
`For a specific case with 6 samples.
`
`c,=(6—n)/6. and
`
`6,. =n/6
`
`The resulting L, value is a linearly interpolated value
`based on the difference between the selected X and Y
`sample values. Equation 2 is a special case of the basic
`linear series of values (Equation 1) resulting from taking
`a fractional part of the difference between the X+Y
`sample values, and adding n times this fractional part
`successively to the X sample value to obtain each inter-
`polated sample value I". When the Y value is not the
`stop value Y but the actual Y" sample occurring where
`the interpolated value needs to be inserted the linearity
`of the interpolated value will vary as the Y sample value
`deviates from the stop sample value Y.
`The waveshaping filter 57 inserts the interpolated
`values 1,. to smooth out the scrambled video signal on
`line 66 only during a. fiveosarnple period overlapping the
`transition between adjacent retrieved portions of each
`scrambled line in response to a control signal provided
`on line 84 by the control processor during the five-cycle
`period.
`Referring to FIG. 3, each eight-bit sample on line 66
`is clocked into the input register 72. The eight bits are
`output from the input register 72 onto line 85, from
`which they are routed in through different three chan-
`nels on lines 86, 87 and 88. All eight bits are routed over
`channel 1 (line 86) through the first delay register 80,
`whereby they are delayed by one sample clock period
`and provided on lines 89 to the multiplexer 82.
`The six most significant bits are routed over channel
`2 (line 8'7) to address the six most-significant—bit posi-
`tions of the address of the Y PROM 75. The three least—
`significant—bit positiOns of the address of the Y PROM
`75 are addressed by a count signal provided on line 90
`from the counter 74. The counter 74 is a 0—4 counter
`which is advanced at the sampling rate of 14.32 MHz.
`during the five-sample period indicated by the control
`signal on line 84.
`During the first sample period while the count on
`lines 90 is 000, the Y PROM provides to the Y output
`register ‘77 an 8-bit signal having a value of one-sixth the
`value of Y. as determined by the six bits on line 87. The
`output values from the Y—PROM during the subsequent
`sample periods are twosixths Y2, three-sixths Y3, four-
`sixths Y4 and five-sixths Y5, respectively.
`The six most significant bits of the signal on line 85
`from the output register 72 are provided over channel 3
`(line 88) to the X-address register 73. The six most sig-
`nificant bits of start sample X are stored in the X-
`address register 73 in response to the leading edge of the
`five-sample duration control signal on line 34 and re-
`main stored therein until the trailing edge of the control
`signal on line 84 clears the register 73. The contents of
`the X-address register 73 address the six most-signifi-
`cant-bit positions of the X PROM 76, and the count
`signal on line 90 provides the address for the three least-
`significant-bit positions of the X PROM ‘76.
`During the five sample periods, the values of the
`Output signals provided by the X PROM to the X out-
`put register 78 are five-sixths X, four-sixths X. three-
`sixths X, two-sixths X, and one-sixth X.
`
`Page 10
`
`
`PMC Exhibit 2202
`
`Apple v. PMC
`|PR2016-01520
`
`PMC Exhibit 2202
`Apple v. PMC
`IPR2016-01520
`Page 10
`
`

`

`4,563,702
`
`7
`The binary adder 79 adds the values of the contents of
`the Y output register 77 and the X output register 78.
`The second delay register 81 delays the control signal
`on line 84 to provide a one-sample-period—delayed con-
`trol signal on line 91.
`The multiplexer 82 provides the output from the first
`delay register 80 to the output register 83 at all times
`except during the one-sample-period-delayed control
`signal on line 91. when the multiplexer 82 provides the
`output from the binary adder 79 to the output register
`83.
`The value of the output register signal during the
`transition from the start value X to the stop value Y is
`shown in Table I.
`
`
`
`TABLE 1
`SAMPLE
`CONTROL
`OUTPUT REGISTER
`PERIOD
`SIGNAL
`Xu.1
`—
`0
`X
`000
`l
`Y3/6 + sxzs
`001
`1
`Y2f3 + 21w
`010
`l
`Yy’l + 303
`Bl!
`1
`21w: + xx:
`too
`1
`Sstfi + Kid
`—
`0
`
`
`—0 Y
`
`is provided
`
`The waveshaping filter output signal
`' from the output register 83 on line 92.
`Referring again to FIG. 1, the scrambled video infor-
`mation lines on line 92 are multiplexed by the multi-
`plexer 61 with a six-cycle sync burst data signal on line
`93 from the burst generator 58, a horizontal sync pulse
`data signal on line 94 from the sync generator 59 and
`scrambled digital audio signals and control signals on
`line 95 from the audio processor 49. The operation of
`the multiplexer 61 is controlled by the control processor
`48. The output of the multiplexer 61 is converted to an
`analog signal by the D/A converter 62 to provide a
`scrambled TV signal on line 47.
`The burst generator 58 provides the six-cycle sync
`burst data signal on line 93 in response to a control
`signal on line 96 from the control processor 48. The
`sync burst component of the signal on line 47 is locked
`to and at the same frequency and phase as the color
`burst component of the video signal on line 63 detected
`by the sync detection circuit 51. If the video program
`source is monochrome, data for the phase and fre-
`quency of the six-cycle burst is provided from a mem-
`ory in the control processor 48.
`The sync generator 59 .provides the horizontal sync
`pulse data signal on line 94 in response to a control
`signal on line 97 from the control processor 48. A short-
`ened horizontal sync pulse is retained so that the scram-
`bled signal can pass through telephone company equip—
`ment, which contains circuitry which clamps on this
`pulse. Without any horizontal pulse, the telephone com-
`pany equipment would distort the signal in an unrecov-
`erable manner.
`The control processor ‘8 causes the components of
`the scrambled TV signal on line 47 to occur during the
`intervals shown in FIG. 4b with reference to the begin-
`ning of the scrambled video line as determined in re-
`sponse to the synchronization control signals received
`on lines 64 from the sync detection circuit 51. The se-
`quence of the components in an NTSC video signal line
`are shown in FIG. 40. The front porch occupies the first
`21 sample periods; the horizontal sync pulse occupies
`sample periods 22 through 79; the breezeway occupies
`sample periods 80 through 97; the nine-cycle color burst
`
`8
`occupies sample periods 98 through 133; the back porch
`occupies sample periods 134 through 156; and the active
`video information occupies smnple periods 162 through
`905. The front build-up occupies sample periods 157
`through 161 and the back fall-off occupies sample peri-
`ods 906 through 910.
`In the scrambled TV signal on line 47 shown in FIG.
`4b. the horizontal sync pulse oocupies sample periods 1
`through 18;
`the 6-cycle sync burst occupies sample
`periods 19 through 42; the scrambled audio signal and
`control signals occupy sample periods 43 through 134
`and the scrambled video information lines occupy the
`remaining sample periods. The location of the six-sam-
`ple period waveshaping interval WS depends upon the
`location of the cutpoint X in the stored video informa-
`tion line. The front build-up occupies approximately 21
`sample periods and the back fall-off occupies approxi-
`mately five sample periods, with there being variation
`for a two-sample period shift for scrambling embodi-
`ments in which an odd—numbered video signal line is
`paired with an even-numbered video signal line. Such a
`scrambling scheme requires less capacity in the buffer
`memory 53 in that four consecutive odd and even lines
`can be retrieved while the following four consecutive
`odd and even lines are stored. However, such scheme
`results in a two-cycle phase shift which is compensated
`for to achieve alignment by a two-sample period shift in
`retrieving the video information from the memory 53.
`also the length of the front build-up interval will depend
`in the amount of Overlap in the stored video signal line
`portions retrieved from a gle stored line (as shown in
`FIG. 2).
`Scrambling does not take place during lines 1 through
`9 of each video field. During line 1 of the first video
`field, the multiplexer 61 causes IRE reference level data
`signals and a synchronization sequence data signal to be
`inserted in the scrambled video signal during the sample
`periods otherwise occupied by the active video infor-
`mation. Video line 1 is illustrated in FIG. 4a. The refer-
`ence level data and synchronization sequence data sig-
`nals are provided on line 98 by the reference pattern
`generator 60 in response to control signals on line 99
`from the control processor 48.
`The signals on lines 93. 94 and 98 all are digital sig-
`nals.
`Referring to FIG. 4c, the synchronization sequence
`signal is a 24—bit signal referenced to an IRE reference
`level of 0 for binary “O” and to an IRE reference level
`of 60 for binary l. The synchronization sequce signal
`occupies sample period 1‘79 through 236. An IRE refer-
`ence level signal of 40 occupies sample periods 135
`through 178; and an IRE reference level signal of 100
`occupies sample periods 237 through 284. Sample peri-
`ods 285 through 910 are at an IRE reference level of 0.
`One volt equals I40 IRE units. The synchronization
`sequence signal is used by the descrambler for frame
`and sample synchronization as well as for control of
`AGC (automatic gain control) amplifier gain.
`Sample periods 135 through 910 of lines 2 through 9
`of field one and of lines 1 through 9 of field two are
`referenced to an IRE reference level of zero.
`The audio signal on line 46 is digitized and scrambled
`by the audio processor 49 in accordance with an audio
`encryption portion of the keystream received on line 44
`by the control