Paper No. __
`Filed: July 29, 2016
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`Filed on behalf of: Samsung Electronics Co., Ltd.
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`By: Naveen Modi (PH-Samsung-Flamm-IPR@paulhastings.com)
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`Joseph E. Palys (PH-Samsung-Flamm-IPR@paulhastings.com)
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`Chetan R. Bansal (PH-Samsung-Flamm-IPR @paulhastings.com)
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`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`DANIEL L. FLAMM,
`Patent Owner
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`____________________
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`Patent No. RE 40,264 E
`____________________
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`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. RE 40,264 E
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`

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`Petition for Inter Partes Review
`Patent No. RE40,264
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`TABLE OF CONTENTS
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`INTRODUCTION ........................................................................................... 1
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`I.
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 1
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`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 2
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`IV. GROUNDS FOR STANDING ........................................................................ 2
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`V.
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`PRECISE RELIEF REQUESTED AND GROUNDS RAISED ..................... 2
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`A.
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`B.
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`Claims for Which Review is Requested ................................................ 2
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`Statutory Grounds of Challenge ............................................................ 2
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`VI. LEVEL OF ORDINARY SKILL IN THE ART ............................................. 3
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`VII. OVERVIEW OF THE TECHNOLOGY, ’264 PATENT, AND
`PRIOR ART ..................................................................................................... 4
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`A.
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`B.
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`C.
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`D.
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`Technology Background ....................................................................... 4
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`The ’264 Patent ..................................................................................... 5
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`Priority Date of the Challenged Claims ................................................ 8
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`Kadomura ............................................................................................ 10
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`E. Matsumura ........................................................................................... 13
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`F. Wang I ................................................................................................. 15
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`VIII. CLAIM CONSTRUCTION .......................................................................... 16
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`IX. DETAILED EXPLANATION OF GROUNDS ............................................ 17
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`A. Overview of the Combinations of References .................................... 17
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`B. Ground 1: Kadomura and Matsumura Render Obvious Claims
`27, 32, 37, and 40 ................................................................................ 19
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`1.
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`Claim 27 .................................................................................... 19
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`Petition for Inter Partes Review
`Patent No. RE40,264
`Claim 32 .................................................................................... 33
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`Claim 37 .................................................................................... 35
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`Claim 40 .................................................................................... 46
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`2.
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`3.
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`4.
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`C. Ground 2: Kadomura, Matsumura and Narita Render Obvious
`Claims 31 and 50 ................................................................................. 47
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`1.
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`2.
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`Claim 31 .................................................................................... 47
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`Claim 50 .................................................................................... 49
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`D. Ground 3: Kadomura, Matsumura and Wang I Render Obvious
`Claims 27, 34, 37, 41, 44 ..................................................................... 50
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`1.
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`2.
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`3.
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`4.
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`5.
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`Claim 27 .................................................................................... 51
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`Claim 34 .................................................................................... 58
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`Claim 37 .................................................................................... 59
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`Claim 41 .................................................................................... 65
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`Claim 44 .................................................................................... 65
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`E.
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`Ground 4: Kadomura, Matsumura, Wang I and Wang II Render
`Obvious Claims 47 and 48 .................................................................. 67
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`1.
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`2.
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`Claim 47 .................................................................................... 67
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`Claim 48 .................................................................................... 69
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`X.
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`CONCLUSION .............................................................................................. 70
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`Petition for Inter Partes Review
`Patent No. RE40,264
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`TABLE OF AUTHORITIES
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`Cases Page(s)
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`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) .....................................................................................passim
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`Nike, Inc. v. Adidas AG,
`812 F.3d 1326 (Fed. Cir. 2016) .......................................................................... 28
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`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 16
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`Adminstrative Decisions
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`Cisco Systems, Inc., v. AIP Acquisition, LLC,
`IPR2014-00247, Paper No. 20 (July 10, 2014) .................................................. 16
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`Lam Research Corp. v. Daniel L. Flamm,
`IPR2015–00470, Paper No. 6 (July 1, 2016) ........................................................ 9
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`Lam Research Corp. v. Daniel L. Flamm,
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`IPR2015–01764, Paper No. 7 (Feb. 24, 2016) ............................................. 21, 32
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`Square Inc. v. J. Carl Cooper,
`IPR2014-00156, Paper No. 38 (May 14, 2015) .................................................. 16
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`Toyota Motor Corp. v. Cellport Systems, Inc.,
`
`IPR2014-00633, Paper No. 11 (Aug. 14, 2015) ................................................. 17
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`Kamstrup A/S v. Apator Miitors APS,
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`IPR2015-01403, Paper No. 7 (Dec. 28, 2015) .................................................... 49
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`Statutes
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`35 U.S.C. § 102(b) ..................................................................................................... 3
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`35 U.S.C. § 102(e) ..................................................................................................... 3
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`35 U.S.C. § 103(a) ................................................................................................. 2, 3
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`Petition for Inter Partes Review
`Patent No. RE40,264
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`Regulations
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`37 C.F.R. § 42.8 ......................................................................................................... 1
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`Petition for Inter Partes Review
`Patent No. RE40,264
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`Ex. 1001
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`LIST OF EXHIBITS
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`U.S. Patent No. 40,264 E
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`Ex. 1003
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`Prosecution History of Reissue Patent 40,264
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`Ex. 1004
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`Prosecution History of U.S. Patent Application No. 09/151,163
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`Ex. 1005
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`File History of U.S. Patent Application No. 08/567,224
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`Ex. 1006
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`U.S. Patent No. 6,063,710 to Kadomura et al.
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`Ex. 1007
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`Ex. 1008
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`U.S. Patent No. 5,151,871 to Matsumura et al.
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`U.S. Patent No. 4,913,790 to Narita et al.
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`Ex. 1009
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`U.S. Patent No. 5,219,485 to Wang
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`Ex. 1010
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`European Patent Application No. 87311193.4 to Wang et. al
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`Petition for Inter Partes Review
`Patent No. RE40,264
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`I.
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`INTRODUCTION
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`Samsung Electronics Co., Ltd. (“Petitioner”) requests inter partes review
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`(“IPR”) of claims 27, 31, 32, 34, 37, 40, 41, 44, 47, 48, and 50 of U.S. Patent No.
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`RE 40,264 (“the ’264 patent”) (Ex. 1001), which, on its face, is assigned to Daniel
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`L. Flamm (“Patent Owner”). For the reasons set forth below, the challenged
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`claims should be found unpatentable and canceled.
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: Petitioner identifies the following as the real
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`parties-in-interest: Samsung Electronics Co., Ltd., Samsung Electronics America,
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`Inc., Samsung Semiconductor, Inc., and Samsung Austin Semiconductor, LLC.
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`Related Matters: Patent Owner has asserted the ’264 patent against
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`Petitioner in Daniel L. Flamm v. Samsung Electronics Co., Ltd., et al., No. 1:15-
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`cv-613-LY (WDTX). The case was transferred to the Northern District of
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`California on April 27, 2016 and is now pending under Case No. 5:16-cv-2252-
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`BLF (NDCA). The ’264 patent is at issue in the following IPRs: IPR2015-01764
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`and IPR2015-01768.1 Petitioner is concurrently filing a petition challenging
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`claims 13-26, 64, and 65 of the ’264 patent.
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` The ’264 patent was also at issue in IPR2015-01759, IPR2015-01766, IPR2016-
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`00468, IPR2015-00469, and IPR2016-00470 where the Board denied institution.
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`1
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`Petition for Inter Partes Review
`Patent No. RE40,264
`Counsel and Service Information: Lead counsel is Naveen Modi (Reg. No.
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`46,224), and Backup counsel is (1) Joseph E. Palys (Reg. No. 46,508) and (2)
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`Chetan R. Bansal (Limited Recognition No. L0667). Service information is Paul
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`Hastings LLP, 875 15th St. N.W., Washington, D.C., 20005, Tel.: 202.551.1700,
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`Fax:
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`202.551.1705,
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`email:
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`PH-Samsung-Flamm-IPR@paulhastings.com.
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`Petitioner consents to electronic service.
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`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The PTO is authorized to charge all fees due at any time during this
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`proceeding, including filing fees, to Deposit Account No. 50-2613.
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`IV. GROUNDS FOR STANDING
`Petitioner certifies that the ’264 patent is available for IPR and Petitioner is
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`not barred or estopped from requesting IPR on the grounds identified herein.
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`V.
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`PRECISE RELIEF REQUESTED AND GROUNDS RAISED
`A. Claims for Which Review is Requested
`Petitioner respectfully requests review of claims 27, 31, 32, 37, 40, 41, 44,
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`48, and 50 (“challenged claims”) of the ’264 patent, and cancellation of these
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`claims as unpatentable.
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`Statutory Grounds of Challenge
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`B.
`The challenged claims should be canceled as unpatentable on the following
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`grounds: Ground 1: Claims 27, 32, 37, and 40 are unpatentable under 35 U.S.C. §
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`103(a) in view of U.S. Patent No. 6,063,710 (“Kadomura”) (Ex. 1006) and U.S.
`2
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`Petition for Inter Partes Review
`Patent No. RE40,264
`Patent No. 5,151,871 (“Matsumura”) (Ex. 1007); Ground 2: Claims 31 and 50 are
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`unpatentable under 35 U.S.C. § 103(a) in view of Kadomura, Matsumura, and U.S.
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`Patent No. 4,913,790 (“Narita”) (Ex. 1008); Ground 3: Claims 27, 34, 37, 41, and
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`44 are unpatentable under 35 U.S.C. § 103(a) in view of Kadomura, Matsumura,
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`and U.S. Patent No. 5,219,485 (“Wang I”) (Ex. 1009); and Ground 4: Claims 47
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`and 48 are unpatentable under 35 U.S.C. § 103(a) in view of Kadomura,
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`Matsumura, Wang I, and EP Patent Application No. 87311193.4 (“Wang II”) (Ex.
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`1010).
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`As discussed below in section VII.C, the challenged claims are not entitled
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`to a filing date earlier than September 11, 1997. Kadomura was filed on Feb. 21,
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`1997, and issued May 16, 2000, and is prior art to the ’264 patent at least under
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`pre–AIA 35 U.S.C. § 102(e). Matsumura issued on September 29, 1992, Narita
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`issued on April 3, 1990, Wang I issued on June 15, 1993, and Wang II published
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`on June 22, 1988. Therefore, these references are prior art to the ’264 patent at
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`least under pre–AIA 35 U.S.C. § 102(b).
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`VI. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art at the time of the alleged invention of
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`the ’264 patent would have had (i) a Bachelor's degree in engineering, physics,
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`chemistry, materials science, or a similar field, and three or four years of work
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`experience in semiconductor manufacturing or related fields, or (ii) a Master's
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`Patent No. RE40,264
`degree in engineering, physics, chemistry, materials science, or a similar field and
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`two or three years of work experience in semiconductor manufacturing or related
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`fields (Ex. 1002 at ¶18.)2 More education can supplement work experience and
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`vice versa. (Id.)
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`VII. OVERVIEW OF THE TECHNOLOGY, ’264 PATENT, AND PRIOR
`ART
`A. Technology Background
`By September 1997, plasma techniques for the manufacture, fabrication,
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`and/or production of semiconductor devices had made significant advancements.
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`(Ex. 1002 at ¶26.) For instance, plasma etching (more particularly, dry etching)
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`techniques were known that involved etching different layers of a film at different
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`temperatures. (See id.; see generally Ex. 1006.) Sophisticated mechanisms had
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`already been developed that controlled the temperature of both a substrate and a
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`substrate holder such that the time between temperature changes was preselected
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`and controlled by a processing unit. (See generally Ex. 1007.) (Ex. 1002 at ¶26.)
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`As discussed below, the challenged claims of the ’264 patent recite these well-
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`known techniques, and thus offer no novel advancement in the art. (Ex. 1002 at
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`¶26.)
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` 2
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` Petitioner submits the declaration of Dr. Stanley Shanfield (Ex. 1002), an expert
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`in the field of the ’264 patent. (Ex. 1002 at ¶¶5–14).
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`Petition for Inter Partes Review
`Patent No. RE40,264
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`The ’264 Patent
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`B.
`The ’264 patent reissued April 29, 2008, from U.S. Patent Application No.
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`10/439,245 (“the ’245 application”), filed on May 14, 2003. The ’264 patent is a
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`reissue of U.S. Patent No. 6,231,776 B1 (“the ’776 patent”), which issued May 15,
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`2001, from U.S. Patent Application No. 09/151,163 (“the ’163 application”), filed
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`September 10, 1998. The ’264 patent is directed to a method “for etching a
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`substrate in the manufacture of a device.” (Ex. 1002 at ¶¶19-21; Ex. 1001 at
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`Abstract.) Figure 1 illustrates an etch apparatus used in the method including a
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`chamber 12 and a pedestal 18 (substrate holder). (Ex. 1001 at 3:24-25, 3:32-33,
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`3:40-41.)
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`(Ex. 1001 at Fig. 1.)
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`Figure 6 illustrates a “block diagram of a substrate holder 600 . . . .” (Id. at
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`14:27-28.) The substrate holder 600 includes “a backside surface 608,” which
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`includes a plurality of zones 608A, 608B, 608C, and 608D. (Id. at 14:31-44.)
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`Each of the zones, separated from each other by a baffle 605, has an inlet 613 and
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`outlet 611 for temperature controlled fluid to enter and exit the zones “to heat or
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`cool the upper surface of the substrate holder” that holds an object (e.g., a wafer).
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`(Id. at 14:31-44, 14:62-63, 15:39-40; Ex. 1002 at ¶20.)
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`(Id. at Fig. 6.)
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`Referring to figure 7, the operation of the temperature control system is
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`described. The substrate holder receives fluid heated by heating unit 705 and the
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`fluid transfers energy in the form of heat to the substrate holder. (Id. at 16:5-20.)
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`The fluid can also be cooled using a heat exchanger 723. (Id.; Ex. 1002 at ¶21.)
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`(Id. at Fig. 7.) According to the ’264 patent, “the temperature of the chuck and
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`wafer” are adjusted “to predetermined temperatures within specified time intervals
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`and within specified uniformity limits” by varying the temperature of the fluid.
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`(Id. at 16:36–39, 16:50–67; Ex. 1002 at ¶21.)
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`Priority Date of the Challenged Claims
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`C.
`The challenged claims are not entitled to a priority date earlier than
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`September 11, 1997. The ’224 application, filed on December 4, 1995, is the
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`earliest application in priority chain of the ’264 patent. But the ’224 application
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`Patent No. RE40,264
`does not support the subject matter of the challenged claims. (Ex. 1002 at ¶¶22-
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`24.) Accordingly, the filing date of the challenged claims can be no earlier than
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`September 11, 1997, which is the filing date of the ’650 Provisional.3 This
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`conclusion is consistent with the Board’s decision in Lam Research Corp. v.
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`Daniel L. Flamm, IPR2016-00470, Paper No. 6 at 10-12 (July 1, 2016).
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`Each of the challenged claims of the ’264 patent recites the concept of
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`changing a first substrate temperature to a second substrate temperature in a
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`preselected time interval. (See, e.g., Ex. 1001, claim 27 (“substrate temperature is
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`changed from the selected first substrate temperature to the selected second
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`substrate temperature . . . within a preselected time interval”), claim 36 (“change
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`the substrate temperature from the selected first substrate temperature to the
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`selected second substrate temperature within a preselected time period”).) Claim
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`37 further recites two separate temperature sensors: “a substrate temperature
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`sensor” and “a substrate holder temperature sensor.” (Ex. 1001, claim 37.) These
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`features are not disclosed in the ’224 application. (Ex. 1002 at ¶24.)
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` While Petitioner does not concede that the ’650 Provisional supports the subject
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`matter of the challenged claims, the prior art applied in this petition predate the
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`’650 Provisional filing date.
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`Patent No. RE40,264
`The ’224 application describes transferring a wafer between two chambers
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`in which the pedestals are maintained at different temperatures. (Ex. 1005 at 45-
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`46.) But it does not disclose the substrate temperature is changed from a first
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`substrate temperature to a second substrate temperature in a preselected time
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`interval as required by claims 27 and 37. The ’224 application describes a
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`thermocouple for measuring the temperature of the substrate support but does not
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`describe two separate temperature sensors (“substrate temperature sensor” and
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`“substrate holder temperature sensor”) as required by claim 37. (Ex. 1002 at ¶24.)
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`Nor does the ’224 application suggest such missing features to one of ordinary skill
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`in the art. (Id.)
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`D. Kadomura
`Kadomura generally relates to a dry etching method used primarily for the
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`production of semiconductor devices and, in particular, to a dry etching method
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`and apparatus that provides compatibility for anisotropic fabrication and high
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`selectivity. (Ex. 1002 at ¶27; Ex. 1006 at 1:6–10.) Kadomura discloses applying
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`an etching treatment that includes a plurality of steps to a specimen within the
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`same processing apparatus, wherein the temperature of the specimen is changed
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`between etching in a first step and etching in a second step. (Ex. 1006 at 2:65–
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`3:5.)
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`Patent No. RE40,264
`Kadomura discloses its techniques with reference to an etching apparatus 1
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`(illustrated in figure 4) that includes a diffusion chamber 2 in which a stage 12
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`supports a “specimen W comprising a semiconductor substrate.” (Id. at 11:8-38.)
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`Kadomura discloses controlling the temperature of specimen W by controlling the
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`temperature of stage 12. (Id. at 3:28–37; see also id. at 6:49-51, 7:41-43, 8:36-39,
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`10:8-10, 12:37-40.)
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`(Id. at Fig. 4 (annotated); Ex. 1002 at ¶28.)
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`Kadomura discloses controlling the temperature of stage 12 (orange) (and
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`thereby controlling the temperature of specimen W) by using a combination of a
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`heater and chiller 17 (yellow). (Ex. 1006 at 6:30–35, 7:38-47, 10:8-10.) A bias
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`power source 14 (red) controls incident ion energy on wafer W. (Id. at 11:42-47.)
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`Feed back control device 25 (purple) sends signals to cryogenic valves to obtain a
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`predetermined coolant flow rate from the chiller 17. (Id. at 12:37–48.) Kadomura
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`teaches that the temperature sensed by the thermometer 18 is detected by the feed
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`back control device 25 (purple) that “controls the ON–OFF or ON–OFF degree of
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`the cryogenic valve 21, . . . , 23 so as to obtain a gas coolant flow rate previously
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`determined by experiment or calculation based on the difference between the
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`detected temperature and the predetermined temperature for the specimen W.”
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`(Id.) (Ex. 1002 at ¶29.)
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`Kadomura discloses three embodiments, each of which applies its dry
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`etching method in a different manner. (Ex. 1006 at 5:44–56, Figs. 1A–1C, 2A–2C,
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`3A–3C.) Common amongst these three embodiments is the fact that a first etching
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`step (main etching) is carried out with the specimen W at a first temperature and a
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`second etching step (overetching) is carried out with the specimen W at a second
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`temperature. For example, in the first embodiment, the main etching in the first
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`step is applied at a temperature of 20º C, whereas the overetching in the second
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`step is applied at a temperature of -30º C. (Id. at 6:17–28, 6:63–7:7.) In the third
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`embodiment, the main etching in the first step is applied at a first temperature (-30º
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`C), whereas the overetching in the second step is applied at a second temperature
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`(50º C). (Id. at 9:54–62, 10:17–27.) (Ex. 1002 at ¶30.)
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`Petition for Inter Partes Review
`Patent No. RE40,264
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`E. Matsumura
`Matsumura discloses a “method of heat–processing semiconductor devices
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`whereby temperatures of the semiconductor devices can be controlled at devices–
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`heating and –cooling times so as to accurately control their thermal history curve.”
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`(Ex. 1002 at ¶¶31-35; Ex. 1007 at 2:60–65.) Matsumura discloses applying its
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`method to plasma etching. (Ex. 1007 at 10:3–7.)
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`Matsumura discloses processing a wafer W on a wafer-stage 12, which
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`includes upper plate 13 and conductive thin film 14. (Id. at 5:13–51, Fig. 5A.) As
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`shown below, control system 20 (purple) sends signals (SM) to power supply
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`circuit 19 (red) to heat semiconductor wafer W (blue) on upper plate 13 (orange)
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`by conductive thin film 14; and sends signals (SC) to cooling system 23 (yellow)
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`to control the amount of coolant supplied to jacket 22. (Id. at 5:52–6:32, Figs. 5A
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`and 5B.) Control system 20 outputs heating SM and cooling SC signals responsive
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`to “inputted recipes and temperature detecting signal.” (See, e.g., id. at 5:58–63.)
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`Patent No. RE40,264
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`(Id. at Fig. 5A (annotated); Ex. 1002 at ¶32.)
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`Matsumura provides examples of the “recipes” in figures 8 and 9 for
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`ensuring predetermined wafer temperature changes within predetermined time
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`intervals for processing. (Ex. 1007 at Figs. 8, 9.) For example, figure 9 shows a
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`recipe with a “thermal history curve” showing temperature as a function of time.
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`(Id. at 4:41–42.) This “recipe” has a temperature change from 20° C to 90° C
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`within the first 60 seconds of the process. (Id. at Fig. 8.)
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`Patent No. RE40,264
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`(Id. at Fig. 9.) Based on the input recipe and the detected wafer temperature,
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`Matsumura’s control system 20 controls the heating/cooling of the wafer W. (Id.
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`at 3:10–16, 5:52–6:32, 8:56-9:26, 10:42–63, Figs. 5A and 5B; Ex. 1002 at ¶¶33-
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`35.)
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`F. Wang I
`Wang I generally relates to a process for etching conductive layers used in
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`semiconductor integrated circuits and, in particular, to a method for etching metal
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`silicides, polycrystalline silicon, and composite silicide-polysilicon structures, as
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`well as reactive plasma gas chemistry for use in such methods. (Ex. 1002 at ¶36;
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`Ex. 1009 at 1:13-19.) Wang I discloses that the etch rate of silicides such as WSix
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`can be increased by increasing the substrate temperature. (Ex. 1009 at 2:47-52)
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`Figures 20 and 21 in Wang I show that an increase in the substrate temperature (by
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`virtue of an increase in the substrate holder temperature) increases the silicide etch
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`rate. (Id. at 6:1-5, “FIGS. 20 and 21 illustrate the effect of hexode temperature on
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`polysilicon etch rate and on molybdenum silicide etch rate . . . .”)
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`
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`(Ex. 1009 at Figs. 20, 21.)
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`VIII. CLAIM CONSTRUCTION
`The ’264 patent expired on December 4, 2015. Accordingly, the claims of
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`the ’264 patent should be construed under the standard set forth in Phillips v. AWH
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`Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See, e.g., Square Inc. v. J. Carl
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`Cooper, IPR2014-00156, Paper No. 38 at 7 (May 14, 2015) (citing In re Rambus,
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`Inc., 694 F.3d 42, 46 (Fed. Cir. 2012)). Under Phillips, claim terms are given their
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`ordinary and customary meanings, as would be understood by a person of ordinary
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`skill in the art, at the time of the invention, having taken into consideration the
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`language of the claims, the specification, and the prosecution history of record.
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`See, e.g., Cisco Systems, Inc., v. AIP Acquisition, LLC, IPR2014-00247, Paper No.
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`20 at 2-3 (July 10, 2014). The Board, however, only construes the claims when
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`necessary to resolve the underlying controversy. Toyota Motor Corp. v. Cellport
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`Systems, Inc., IPR2014-00633, Paper No. 11 at 16 (August 14, 2015) (citing Vivid
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`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)).
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`Petitioner submits that for purposes of this proceeding, the terms of the challenged
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`claims should be given their ordinary and customary meaning, and thus no terms
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`require construction.4 (See also Ex. 1002 at ¶25.)
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`IX. DETAILED EXPLANATION OF GROUNDS
`A. Overview of the Combinations of References
`The grounds below rely on combinations of prior art references that are
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`directed to similar technical subject matter, address similar issues in semiconductor
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`processing, and/or material or process characteristics relating to semiconductor
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`processing, among other things. For example, all of the references (Kadomura,
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`Matsumura, Narita, Wang I, Wang II) disclose systems and processes for
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`semiconductor processing, some describing plasma-based film etching techniques.
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`(Ex. 1002 at ¶¶43, 85, 91, 121.) The references also address issues relating to
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`temperature control in semiconductor processing. (Id..) As such, one of ordinary
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`skill in the art would have been motivated to look to the teachings of these
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` Petitioner reserves all rights to raise claim construction and other arguments in
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` 4
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`the pending district court litigation. For example, Petitioner has not necessarily
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`raised all challenges to the ’264 patent, including those under § 112, given the
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`limitations placed by the Rules governing this proceeding.
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`references in the manners discussed below to address issues of etching substrates
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`to manufacture a device such as an integrated circuit. (Id.) For example, as
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`discussed below for claims 27 and 37, one of ordinary skill in the art would have
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`been motivated to combine the teachings of the Kadomura with Matsumura for the
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`purpose of better control of the etching process. (Id. at ¶¶43, 49, 50, 60, 61, 74-
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`77.) Further, as discussed below with respect to claim 37, one of ordinary skill in
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`the art would have found reason to look to Wang I’s teachings of an increased
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`etching rate for a silicide layer at a higher substrate temperature to modify the
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`combined Kadomura-Matsumura system. (Id. at ¶¶91, 104.) Similarly, such a
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`skilled person would have found reason to look to Wang II’s teachings of a better
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`technique for depositing SiO2 to modify the combined Kadomura-Matsumura-
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`Wang I system. (Id. at ¶¶121, 123-125.) Also, given Narita’s disclosure of
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`infrared heating, a skilled artisan would have found reason to modify the combined
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`Kadomura-Matsumura system to provide a more flexible system with alternative
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`heat sources. (Id. at ¶¶85, 87-88.) Thus, the combined teachings of these
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`references, the knowledge of such a skilled person, the nature of the problem(s) to
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`be solved as a whole would have suggested the claimed combinations of claims 27,
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`31, 32, 34, 37, 40, 41, 44, 47, 48, and 50 to one of ordinary skill in the art at the
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`time of the alleged invention for the ’264 patent. Moreover, one skilled in the art
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`would have had the knowledge and capabilities to modify the combined systems
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`and processes discussed below such that they resulted in workable and operable
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`systems and processes.
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`B. Ground 1: Kadomura and Matsumura Render Obvious Claims 27,
`32, 37, and 40
`1.
`Claim 27
`a)
`“A method of etching a substrate in the manufacture of
`a device, the method comprising:”
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`To the extent that the preamble is determined to be limiting, Kadomura
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`discloses this feature. (Ex. 1002 at ¶¶42, 44.) For example, Kadomura discloses
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`“a dry etching method used primarily for the production of semiconductor
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`devices.” (See, e.g., Ex. 1006 at 1:6–10.) Kadomura discloses several examples in
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`which a film on a substrate is etched for manufacturing a semiconductor device.
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`(See, e.g., id. at Figs. 1A–5, 11:5–13, 6:1–7–18, 9:33–10:35.) (See also Section
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`VII.D; citations and analysis below for the remaining elements of this claim.)
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`b)
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`“heating a substrate holder to a first substrate holder
`temperature with a heat transfer device, the substrate
`holder having at least one temperature sensing unit,”
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`Kadomura in combination with Matsumura discloses or suggests this
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`feature. (Ex. 1002 at ¶¶45, 46.) Kadomura discloses heating a specimen stage 12
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`(“substrate holder”) with a heater (“heat transfer device”) so that the specimen
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`temperature changes to 50°C. (See, e.g., Ex. 1006 at 10:7-11; see also Section
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`VII.D.) One of ordinary skill in the art would have understood that the
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`temperature of stage 12 is changed to a temperature corresponding to the new
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`specimen temperature, i.e., the heater heats stage 12 to a “first substrate holder
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`temperature.” One of ordinary skill in the art would have understood that stage 12
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`is a “substrate holder” at least because it is used “for support and fixing the
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`specimen W.” (Id. at 11:36–37.)
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`Kadomura discloses “changing the temperature of a specimen by changing
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`the temperature of a specimen stage supporting the specimen . . .” and further
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`discloses “changing the temperature of the specimen stage to a setting temperature
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`for the specimen . . . .” (Ex. 1006 at 3:28–37, emphases added). Accordingly,
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`when Kadomura heats specimen W to a temperature of 50º C by heating stage 12
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`with a “heater,” the temperature of stage 12 is also changed, i.e., changed to a “first
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`substrate holder temperature.” (Id. at 10:7–11.) Kadomura discloses another
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`example in which stage 12 is heated with a “heater” to change its temperature to
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`20º C, which is a “setting temperature” of the specimen W and also provides an
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`example of heating the stage 12 to a “first substrate holder temperature.” (Id. at
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`7:31–47, 6:17–20, 3:28–37.) (Ex. 1002 at ¶46.)
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`Kadomura also discloses a thermometer 18 (“at least one temperature
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`sensing unit”) “for measuring the temperature of the specimen W.” (Id. at Fig. 4;
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`11:49–50.) Patent Owner may argue that Kadomura does not explicitly disclose
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`the “substrate holder having at least one temperature sensing unit” by contending
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`that Kadomura does not explicitly disclose that thermometer 18 is part of stage 12.
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`But figure 4 of Kadomura would have suggested to one of ordinary skill in the art
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`that thermometer 18 is part of stage 12. (Ex. 1002 at ¶47.) In any event,
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`implementing such a feature in Kadomura would have been obvious in light of
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`Matsumura, which discloses a “substrate holder having at least one temperature
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`sensing unit.” (Id.)
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`Matsumura discloses a “method of heat–processing semiconductor devices
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`whereby temperatures of the semiconductor devices can be controlled at devices–
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`heating and –cooling times so as to accurately control their thermal history curve.”
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`(Ex. 1007 at 2:60–65.) Matsumura discloses an embodiment in which a
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`semiconductor wafer W is heated in an unit 42 by heating a stage 12 on which the
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`wafer is mounted. (Id. at 5:13–20, Fig. 5A.) Stage 12 (“substrate holder”)
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