`
`Samsung Exhibit 10(cid:19)(cid:22)
`Samsung Electronics Co., Ltd. v. Daniel L. Flamm
`
`
`
`TO: Mail Stop 8
`Director of the U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`REPORT ON THE
`FILING OR DETERMINATION OF AN
`ACTION REGARDING A PATENT OR
`TRADEMARK
`
`In Compliance with 35 § 290 and/or 15 U.S.C. § 1116 you are hereby advised that a court action has
`been filed in the U.S. District Court Northern District of California on the following:
`(X ) Patents
`or
`(
`) Trademarks
`
`DOCKET NO:
`5:l6—CV-0157‘)-BLF
`
`DATE FILED:
`April 25, 2016
`
`PLAINTIFF:
`
`Flamm
`
`UNITED STATES DISCTRICT COURT
`Robert F. Peckham Federal Building
`280 South 1st Street
`San Jose, CA 95113
`
`DEFENDANT:
`
`Intel Comoration
`
`PATENT OR
`TRADEMARK NO.
`
`DATE OF PATENT OR
`TRADEMARK
`
`HOLDER OF PATENT OR TRADEMARK
`
`In the above-entitled case, the following patent(s) have been included.
`DATE INCLUDED
`INCLUDED BY:
`
`( ) Amendment
`
`( ) Answer
`
`( ) Cross Bill
`
`( ) Other Pleading
`
`PATENT OR
`TRADEMARK NO
`
`DATE OF PATENT
`OR TRADEMARK
`
`HOLDER OF PATENT OR TRADEMARK
`
`In the above-entitled case, the following decision has been rendered orjudgment issued:
`DECISION/JUDGEMENT:
`
`Susan Y. Soong, Clerk
`
`(by) Deputy Clerk, Sandy Nunes
`
`Copy 1 — Upon initiation of action, mail this copy to Commissioner
`Copy 2 — Upon filing document adding patent(s) mail this copy to Commissioner
`Copy 3 — Upon termination of action, mail this copy to the Commissioner
`Copy 4 — Case file copy
`
`Page 2 of 429
`
`
`
`us to. 0V
`Trials
`571-272-7822
`
`Paper 7
`Entered: February 24, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`LAM RESEARCH CORP.,
`
`Petitioner,
`
`V.
`
`DANIEL L. FLAIVHVI,
`Patent Owner.
`
`Case IPR2015-01768
`
`Patent RE 40,264 E
`
`Before DONNA M. PRAISS, CHRISTOPHER L. CRUIVIBLEY, and
`JO-ANNE M. KOKOSKI, Administrative Patent Judges.
`
`PRAISS, Administrative Patent Judge.
`
`DECISION
`
`Institution of Inter Partes Review
`
`37 C.F.R. § 42.108
`
`Page 3 of 429
`
`
`
`IPR2015—01768
`
`Patent RE 40,264 E
`
`Lam Research Corp. (“Petitioner”) filed a Petition (Paper 1, “Pet.”) to
`
`institute an inter partes review of claims 51, 55-63, 68, 70, and 71 of U.S.
`
`Patent No. RE 40,264 E (Ex. 1001, “the ’264 patent”) pursuant to 35 U.S.C.
`
`§§ 311-319. A Preliminary Response (Paper 6, “Prelim. Resp.”) was filed
`
`by Daniel L. F lamm (“Patent Owner”).
`
`A We have jurisdiction under 35 U.S.C. § 314, which provides that an
`
`_inter partes review may be authorized only if “the information presented in
`
`the petition .
`
`.
`
`. and any [preliminary] response .
`
`.
`
`. shows that there is a
`
`reasonable likelihood that the petitioner would prevail with respect to at
`
`least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`Petitioner challenges claims 51, 55-63, 68, 70, and 71 of the ’264
`
`patent under 35 U.S.C. § l03(a). Pet. 12-60. We institute an inter partes
`
`review as to claims 51, 55-63, 68, 70, and 71 as discussed below.
`
`I.
`
`BACKGROUND
`
`A.
`
`Related Proceedings
`
`The ’264 patent is the subject of concurrently-filed inter partes review
`
`proceedings IPR2015-01759, IPR2015-01764, and IPR2015-01766.
`
`We are informed that the ’264 patent is presently at issue in a
`
`declaratory judgment action captioned Lam Research Corp. v. Daniel L.
`
`Flamm, Case 5:15-cv-01277-BLF (ND. Cal.) and in an infringement action
`
`captioned Daniel L. Flamm v. Samsung Electronics Co., Ltd, et al., Case
`
`1:15-cv-613 (W.D. Tex.). Pet. 3; Paper 4, 1.
`
`Page 4 of 429
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`
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`IPR2015-01768
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`Patent RE 40,264 E
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`B.
`
`The ’264 Patent (Ex. I001)
`
`The ’264 patent, titled “Mu1ti-Temperature Processing,” is directed to
`
`a method “for etching a substrate in the manufacture of a device,” where the
`
`method “provide[s] different processing temperatures during an etching
`
`process or the like.” Ex. 1001, Abstract. The apparatus used in the method
`
`is shown in Figure 1 below.
`
`Figure 1 depicts a substrate (product 28, such as a wafer to be etched) on a
`
`substrate holder (product support chuck or pedestal 18) in chamber 12 of
`
`plasma etch apparatus 10.
`
`Page 5 of 429
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`IPR2015—01768
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`Patent RE 40,264 E
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`Figures 6 and 7, below, depict a temperature-controlled substrate
`
`holder and temperature control systems.
`HG’ VIEW)
`
`Heat
`Transfer
`Fluld
`Reservoir
`
`Pump
`
`8 pass used
`w on em fluid
`must be healed
`
`Single Reservoir System
`
`Figures 6 and 7 depict temperature-controlled fluid flowing through
`
`substrate holder (600, 701), guided by baffles 605, where “the fluid [is] used
`
`to heat or cool the upper surface of the substrate holder.” Id. at 14:62-63;
`
`16:5-67. Figure 6 also depicts heating elements 607 underneath substrate
`
`holder 600 where “[t]he heating elements can selectively heat one or more
`
`zones in a desirable manner.” Id. at 15:10-26. Referring to Figure 7, the
`
`temperature control operation is described as follows:
`
`The desired fluid temperature is determined by comparing the
`desired wafer or wafer chuck set point
`temperature to a
`measured wafer or wafer chuck temperature .
`.
`.
`. The heat
`exchanger,
`fluid flow rate, coolant-side fluid temperature,
`heater
`power,
`chuck,
`etc.
`should
`be
`designed
`using
`conventional means to permit the heater to bring the fluid to a
`
`4
`
`Page 6 of 429
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`Patent RE 40,264 E
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`setpoint temperature and bring the temperature of the chuck and
`wafer to predetermined temperatures within specified time
`intervals and within specified uniformity limits.
`
`Id. at 16:36-39 and 50-67.
`
`An example of a semiconductor substrate to be patterned is shown in
`
`Figure 9, below.
`
`Photoresist
`
`Tungsten Silicide
`
`Polyslllcon
`Silicon dioxide
`
`901
`
`Figure 9 depicts substrate 901 having a stack of layers including oxide layer
`V 903, polysilicon layer 905, tungsten silicideilayer 907, and photoresist
`
`masking layer 909 with opening 911 from the treatment method shown in
`
`Fig. 10 below. Id. at 17:58-18:57.
`
`Page 7 of 429
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`Patent RE 40,264 E
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`8 Temp reduoedi D
`
`520 nm
`
`Resist ashed in 02
`(different wavelength)
`
`EC
`ONIO
`‘[1?
`3‘in
`
`C 9
`
`!5
`
`so
`
`120
`
`150
`
`Time
`
`A. SF; native oxide “breakthrough”
`B. CI: plasma is; ignited
`C. WSI, begins to clba?‘{endpoint)
`0. Polysllioon is exposed
`E. Polysilicon cleared to oxide
`
`H. Plasma extinguished and O2 teed
`gas new is started
`I501‘; plasma is started
`J 02 plasma is extinguished.
`
`Fig. 10
`
`Figure 10 depicts the tungsten silicide layer being etched between points B
`and D at a constant temperature; the polysilicon layer being exposed
`
`between points D and E; the polysilicon layer being etched at a constant
`
`temperature beyond point E; and the resist being ashed beyond point I. Id. at
`
`18:58-19:64. The plasma’s optical emission at 530 nm is monitored to
`
`determine when there is breakthrough to the polysilicon layer (Point D) and
`
`Page 8 of 429
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`IPR2015-01768
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`Patent RE 40,264 E
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`a lower etch temperature is required to etch the polysilicon layer (Point E).
`
`Id. at l9:8—24.
`
`C.
`
`Illustrative Claim
`
`Claims 51, 56, and 60 are the only independent claims of the ’264
`
`patent challenged in the Petition. Claim 51, reproduced below, is illustrative
`
`of the claims at issue:
`
`51. A method of processing a substrate in the manufacture of
`a device, the method comprising:
`
`placing a substrate having a film thereon on a substrate
`holder in a processing chamber; the processing chamber
`comprising the substrate holder, a substrate control circuit
`operable to adjust the substrate temperature, a substrate holder
`temperature sensor, and a substrate holder control circuit
`operable to maintain the substrate holder temperature;
`
`performing a first etching of a first portion of the film at
`a selected first substrate temperature;
`
`performing a second etching of a second portion of the
`film at a selected second substrate temperature, the second
`temperature being different from the first temperature;
`
`wherein at least one of the film portions is etched while
`heat is being transferred to the substrate holder with the
`substrate holder control circuit; and
`'
`
`the substrate temperature control circuit effectuates the
`change from the first substrate temperature to the second
`substrate temperature within a preselected time period.
`
`Ex. 1001, 2424-26.
`
`Claim 56 is directed to a method for processing layers which are
`
`included in a stack of layers positioned on a substrate. Id. at 24:40-61.
`
`Claim 56 recites “wherein the substrate holder is heated to a temperature
`
`operable to maintain at least one of the selected first and the selected second
`
`7
`
`Page 9 of 429
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`IPR2015-01768
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`Patent RE 40,264 E
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`substrate temperatures above 49°C,” and “a preselected time period that is
`
`less than the overall process time associated with the etching the first
`
`silicon-containing layer and the second silicon-containing layer.” Id. at
`
`24:52-55, 24:5 8-61. Claim 60 is directed to a method for manufacturing a
`
`device comprising an integrated circuit. Id. at 25:9-31. Claim 60 recites “a
`M (C
`
`stack of layers including a silicide layer,
`
`processing the substrate .
`
`.
`
`. at a
`
`second substrate temperature to etch at least a portion of the silicide layer,”
`
`and “the first substrate temperature is changed to the second substrate
`
`temperature with a substrate temperature control circuit within a preselected
`
`time to etch the silicide layer.” Id. at 25:11-12, 25:23-25, 25:28-31.
`
`D.
`
`The Prior Art
`
`Petitioner relies on the following prior art:
`
`Reference C
`
`A
`
`W Publication
`
`Date
`
`Exhibit
`
`.
`Flschl
`
`Wang ’391
`
`Etching of Tungsten and Tungsten
`Silicide Films by Chlorine Atoms,
`J. ELECTROCHEM. Soc. 135(8)
`2016-2019
`
`US 4,992,391
`US 5,174,856
`US 4,645,218
`
`Aug 1988
`
`1007
`
`Feb. 12, 1991
`Dec. 29, 1992
`Feb. 24, 1987
`
`1008
`1009
`1013
`
`Petitioner also relies on the Declaration of Joseph L. Cecchi, Ph.D., dated
`
`August 18, 2015 (“Cecchi Declaration” Ex. 1010), American Heritage
`
`Page 10 of 429
`
`
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`IPR2015-01768
`
`Patent RE 40,264 E
`
`Dictionary, Third Edition, 1993 (Ex. 1011), and Merriam-Webster’s
`
`Dictionary, Tenth Edition, 1993 (Ex. 1012).
`
`E.
`
`The Asserted Grounds
`
`Petitioner challenges claims 51, 55-63, 68, 70, and 71 of the ’264
`
`patent on the following grounds:
`
`Yfiéirhsichallénii ed
`56_58
`
`60, 62, 63, and 71
`51, 55, and 68
`
`56 and 59
`
`§ 103(a)
`
`§ 103(a)
`§ 1O3(a)
`
`§ 103“)
`
`§ 103(3)‘
`
`Tegal, Ma::l1:1mv1‘1/1:11;2:1rgt521, Thomas,
`Tegal, Matsumura, arita, Thomas,
`and Fischl
`Tegal, Mats:lr1]p(1)1r1rr1:,sNarita, and
`Tegal, Matsumura, Narita, Thomas,
`Wan ’435, and Wan ’391
`Tegal, Matsumura, Narita, Thomas,
`Fischl, and Ooshio
`
`F
`
`Claim Construction
`
`Before proceeding with claim construction, we must determine the
`
`proper standard to apply. Petitioner contends that the claims of the ’264
`
`patent should be given their broadest reasonable construction. Pet. 9. That
`
`standard, however, is applicable only to unexpired patents. See 37 C.F.R.
`
`§ 42.100(b) (“A claim in an unexpired patent shall be given its broadest
`
`reasonable construction in light of the specification of the patent in which it
`
`appears”).
`
`The term of a patent grant begins on the date on which the patent
`
`issues and ends 20 years from the date on which the application for the
`
`patent was filed in the United States “or, if the application contains a
`
`specific reference to an earlier filed application or applications under section
`
`9
`
`Page 11 of 429
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`IPR2015-01768
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`Patent RE 40,264 E
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`120, 121, or 365(c) of this title, from the date on which the earliest such
`
`application was filed.” 35 U.S.C. § 154(a)(2) (2002). The earliest patent
`
`application referenced for the benefit of priority under 35 U.S.C. § 120, for
`
`the ’264 patent, was filed on December 4, 1995, and the patent has no term
`
`extensions. The term of the ’264 patent, thus, expired no later than
`
`December 4, 2015.
`
`Because, on this record, we conclude that the term of the ’264 patent
`
`expired subsequent to the filing of the Petition and the Preliminary
`
`Response, but prior to the end of an inter partes review, for purposes of this
`
`Decision we treat the patent as expired. For claims of an expired patent, the
`
`Board’s claim interpretation is similar to that of a district court. See In re
`
`Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). “In determining the meaning
`
`of the disputed claim limitation, we look principally to the intrinsic evidence
`
`of record, examining the claim language itself, the written description, and
`
`the prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
`
`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips
`
`v. AWH Corp., 415 F.3d 1303, 1312-17 (Fed. Cir. 2005) (en banc)). There
`
`is, however, a ‘“heaVy presumption”’ that a claim term carries its ordinary
`
`and customary meaning. CCS Fitness, Inc. v. Brunswick Corp, 288 F.3d
`
`1359, 1366 (Fed. Cir. 2002).
`
`Petitioner proposes constructions for the claim terms “portion of the
`
`film” (claims 51 and 68), “portion of. .
`
`. layer” (claims 56, 59, and 60),
`
`“preselected time period” (claims 51, 55, and 56), “preselected time” (claim
`
`60), and “selected time period” (claim 61). Pet. 9-11. Patent Owner does
`
`not dispute the proposed claim constructions.
`
`Page 12 of 429
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`Patent RE 40,264 E
`
`Based on the current record, we are not persuaded that express
`
`construction of any term is necessary in order to resolve the disputes
`
`currently before us. Thus, for purposes of this Decision, we discern no need
`
`to provide any express constructions. Vivid Techs., Inc. v. Am. Sci. & Eng ‘g,
`
`Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those terms need be
`
`construed that are in controversy, and only to the extent necessary to resolve
`
`the controversy.”).
`
`II.
`
`ANALYSIS
`
`We turn now to Petitioner’s asserted grounds of unpatentability under
`
`35 U.S.C. § l03(a) to determine whether Petitioner has met the threshold
`
`standard of 35 U.S.C. § 314(a). We begin with a description of Tegal,
`
`Matsumura, Narita, and Thomas, which are asserted in each ground argued
`
`in the Petition.
`
`A.
`
`Prior Art References
`
`I .
`
`Tegal
`
`Tegal “relates to plasma etch processes for the manufacture of
`
`semiconductor wafers .
`
`.
`
`. .” Ex. 1002, 1:4—5. Figure 1, below, is a
`
`schematic for etching a silicon oxide layer at two temperatures in the same
`
`chamber.
`
`Page 13 of 429
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`Patent RE 40,264 E
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`Figure 1 depicts plasma reactor 10 with a chamber having a substrate (wafer
`
`15) on a substrate holder (electrode 13 with plurality of tines 16). Id. at
`
`2:52—3:7. The plasma reactor “performs different types of etch, requiring
`
`different temperatures, in a single reactor” on the substrate. Id. at 1:43-48.
`
`For example, “a tapered etch can be performed in oxide through a patterned
`
`photoresist” by a first etching at 80°C for an isotropic etch, followed by a
`
`second etching at 10°C—40°C for an anisotropic etch. Id. at 5:5—45.
`
`Figure 1 also depicts two reservoirs of water maintained at 10°C and
`
`80°C to control the temperature of the substrate holder and substrate. The
`
`10°C and 80°C waters are mixed, using taps 47 and 44, and delivered to the
`
`substrate holder (electrode 13 with plurality of tines 16) at the desired
`temperature. The return water from the substrate holder is recirculated back
`
`to the reservoirs, remixed with hot or cold water to the desired temperature,
`
`and recirculated to the substrate holder. The valves that interconnect the
`
`Page 14 of 429
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`Patent RE 40,264 E
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`reservoirs to the substrate holder “may be individually actuated
`
`electronically.” Id. at 3:36-4:32.
`
`Figure 1 further depicts controlling substrate (wafer) temperature
`
`using “an external source of helium gas to the underside of wafer 15 through
`
`one or more channels, not shown, in the upper surface of electrode 13. As
`
`known per se in the art, this provides better thermal coupling between wafer
`
`15 and electrode 13.” Id. at 314-26. The passageways in the substrate
`
`holder (electrode 13 with plurality of tines 16) for water “are separate from
`
`the passageways conveying helium from port 19.” Id. at 3:15-26.
`
`While Tegal provides the example of “etching an oxide layer on a
`
`semiconductor wafer,” Tegal envisions “enhance[d] throughput” by
`
`“performing two different types of etch in the same reactor” and performing
`
`“different types of etch, requiring different temperatures, in a single reactor.”
`
`Id. at 6:43-44, 1:43-48. Tegal also provides an example of “etching an
`
`oxide layer on a semiconductor wafer” at temperatures between 10°C and
`
`80°C, but envisions that “any two temperatures can be used.” Id. at 6:4—13,
`
`6:43-44.
`
`2.
`
`Matsumura
`
`Matsumura discloses a “method of heat-processing semiconductor
`
`devices whereby temperatures of the semiconductor devices can be
`
`controlled at devices-heating and -cooling times so as to accurately control
`
`their thermal history curve.” Ex. 1003, 2:60-65. Matsumura discloses
`
`applying the method to plasma etching when it states that “the present
`
`invention has been applied to the adhesion and baking processes for
`
`semiconductor wafers in the above-described embodiments .
`
`. .,it can also be
`
`Page 15 of 429
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`Patent RE 40,264 E
`
`applied to any of the ion implantation, CVD, etching and ashing processes.”
`
`Id. at 10:3-7.
`
`Figure 5A, below, is a schematic of an embodiment for heat-
`
`processing a substrate (wafer W) on a substrate holder (wafer—stage 12,
`
`which includes upper plate 13 and conductive thin film 14) in chamber 11.
`
`j——_:;
`MIVIIIIIIIIIA M
`n
`'\
`/\
`/I\
`\
`1/ \
`I:‘\
`/\
`xx 1/ \\ ll \\ ll \\ // ‘
`-
`_ ,
`\y \"I
`\:I
`\\-A
`
`/
`..
`\ I
`
`THERMOMETER
`
`KEYBOARD
`
`Figure 5A depicts adhesion unit 42 with control system 20, which measures
`
`the temperature of thin film 14 deposited on the underside of upper plate 13
`
`with thermal sensor 25. Id. at 5:13-17, 5:32-47, 5:67—6:4. CITE? Control
`
`system 20 sends signals (SM) to power supply circuit 19 to heat
`
`semiconductor wafer W on upper plate 13 by conductive thin film 14; and
`
`sends signals (SC) to cooling system 23 to control the amount of coolant
`
`supplied to jacket 22. Id. at 5:52-6:32, Figs. 5A and SB.
`
`Inside the control system is a recipe, such as that shown in Figure 9
`
`below.
`
`Page 16 of 429
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`Patent RE 40,264 E
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`TEMPERATURE(
`
`TIME (SECJ
`
`FIG.
`
`9
`
`Figure 9 depicts a “recipe” with a “thermal history curVe” showing
`
`temperature as a function of time. Id. at 4:42-43. At a given time (or
`
`pulse), the control system measures the substrate holder temperature with
`
`thermal sensor 25, compares thermal sensor 25’s measurement to that of the
`
`recipe shown in Figure 9, and either (1) sends a signal (SM) to power supply
`
`circuit 19 to heat the substrate (wafer W), (2) sends a signal (SC) to cooling
`
`system 23 to cool the substrate (jacket 22 under stage 12 exchanges heat
`
`with thin film 14), or (3) sends no signal and waits for the next measurement
`
`time. Id. at 5:52-6:32, Figs. 5A and 5B.
`
`To further explain the temperature control, Matsumura discloses
`
`Figure 7, shown below.
`
`Page 17 of 429
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`Patent RE 40,264 E
`
`FIG.
`
`7
`
`“FIG. 7 is a chart intended to explain the temperature change (include ripple
`
`of temperature) of a heating plate at a time when its temperature is being
`
`raised, lowered and kept certain.” Id. at 4:36-39.
`
`3.
`
`Narita
`
`Narita discloses a method for treating “a surface of a workpiece while
`
`accurately controlling the temperature of the workpiece.” Ex. 1004, 2:7—10.
`
`Narita further discloses that the method can be applied to plasma etching and
`
`thermal chemical vapor deposition (CVD), among other treatment methods.
`
`Id. at 3:3—5. The disclosed treating method “includes a temperature rise step
`
`in which first temperature control is performed and a treatment step in which
`
`second temperature control is performed.” Id. at Abstr. Figure 1, below, is a
`
`schematic of an embodiment for a CVD process where there is a substrate
`
`(semiconductor wafer 2) on a substrate holder (support member 5).
`
`Page 18 of 429
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`I
`
`Figure 1 depicts control section 23 that controls the temperature using two
`
`temperature detecting mechanisms: thermocouple 6, which contacts
`
`substrate 2, and pyrometer 16, which does not contact the substrate. Id. at
`
`3:13-37, 3:65-4:13, 4:26-31. Narita discloses that two temperature sensors
`
`_ are used because the thermocouple has a thermal mass and
`
`quickly rising
`to
`decreased with respect
`reliability is
`temperatures because it takes a considerably long period of time
`to increase
`the
`temperature of the thermocouple
`itself.
`Therefore, when
`the
`substrate
`is
`quickly
`heated,
`the
`thermocouple cannot follow the temperature rise. As a result,
`the difference between a
`temperature detected by the
`thermocouple and an actual temperature becomes large, and a
`set value to be kept constant after quick rise is greatly overshot.
`
`In contrast to this, if a pyrometer is used for temperature
`control of a substrate, the pyrometer can properly respond to
`quick heating because it has good response characteristics.
`
`Id. at 1:42-54.
`
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`IPR2015-01768
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`Patent RE 40,264 E
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`Figure 2, below, depicts temperature as a function of time when a
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`wafer is quickly heated.
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`TEMPERATURE(‘Cl
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`5
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`.
`‘rIME(min)
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`FIG.
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`2
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`Figure 2 shows (1) overshooting the temperature set value (dashed line)
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`when the control circuit only uses thermocouple 6 measurements to control
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`the process; and (2) not overshooting the temperature set value (solid line)
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`when the control circuit switches from thermocouple 6 to pyrometer 16
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`measurements to control the process, during the time when the temperature
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`is quickly increasing. Id. at 6:18-49.
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`4.
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`Thomas
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`Thomas discloses a method for “dry etching refractory metal
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`silicide/polysilicon structures in the manufacture, for instance, of
`semiconductor integrated circuits.” Ex. 1005, 1:7—10. “Of particular
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`interest are refractory metal silicide materials such as tungsten disilicide .
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`.
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`.
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`.
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`In the preferred embodiment .
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`.
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`. the temperature is approximately 20
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`degrees C.” Id. at 3:35-56. “The second stage process is, according to the
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`preferred embodiment, optimized to rapidly and anisotropically etch the
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`Patent RE 40,264 E
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`polysilicon without significant undercutting and with a high selectivity to the
`underlying dielectric, typically silicon dioxide .
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`. the temperature is
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`approximately 5 degrees C.” Id. at 3:57-4:13. Thomas discloses that the
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`two stage process for etching multiple layer structures “provides rapid,
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`anisotropic etching of the overlying silicide and also provides rapid,
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`anisotropic etching of the underlying polysilicon with a high degree of
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`selectivity to the underlying dielectric.” Id. at 4:57-66.
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`B.
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`Obviousness Grounds
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`_ 1.
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`Tegal, Matsumura, Narita, Thomas, and Wang ’485
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`Based on our review of Petitioner’s analysis and supporting evidence,
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`we are persuaded that Petitioner has shown, on the current record, that there
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`is a reasonable likelihood that it would prevail in its obviousness challenge
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`to claims 56-58 over the combination of Tegal, Matsumura, Narita, Thomas,
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`and Wang ’485.
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`As argued by Petitioner (Pet. 12-29), Tegal discloses the desire for
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`increased throughput in plasma etching by running multiple etches at
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`different temperatures in the same chamber having a substrate and a
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`substrate holder as required by each of the independent claims. Ex. 1002,
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`1:43-45, 4:30-31. Thomas provides a stack of layers to be plasma etched in
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`the same chamber at different temperatures that is substitutable in the Tegal
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`process to benefit from the increased throughput. Ex. 1005, 3:57-68;
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`Ex. 1010 1] 65. Thomas’s stack of layers includes two silicon-containing
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`layers, specifically a silicide layer and a polysilicon layer, as required by
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`claim 56. Ex. 1005, 3:33-47. Wang ‘485 increases processing temperatures
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`to above 49°C during plasma etching of silicides and polysilicon structures,
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`IPR2015-0176.8
`Patent RE 40,264 E
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`as further required by claim 56, in order to increase etch rate or throughput.
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`Ex. 1006, 527-15, 621-5, Fig. 21.
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`Tegal further includes a control system for plasma etching
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`temperatures, but without details. Ex. 1002, 4:28-31. Matsumura provides
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`in detail a temperature control system for use in a plasma etching process,
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`where the control system has the flexibility of being responsive to “inputted
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`recipes and temperature detecting signal.” Ex. 1003, 5:60-63. Therefore,
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`the control system of Matsumura effects temperature changes during the
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`process as required by claim 56 and in accordance with a “predetermined
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`recipe” that has a “time—temperature relationship.” Id. at 3:1-7, 6:36-37. In
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`order to better control temperature during process temperature changes,
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`Narita provides two temperature sensors used in a control system for plasma
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`etching. Ex. 1004, 414-10, 5:30-31, Figs. 1, 4.
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`Regarding claim 57, which depends from claim 56, Petitioner argues
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`that it would have been obvious to change the substrate temperature within a
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`time period less than about 5 percent of the total etching process time in
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`view of Matsumura’s disclosure of a predetermined recipe and also to
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`increase throughput. Pet. 23-24 (citing Ex. 1003, 3:1—7, 6:36-37, Figs. 8, 9;
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`Ex. 1010 111] 77, 78, 80). Regarding claim 58, which depends from claim 56,
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`Petitioner contends that Thomas teaches etching at least one layer in a
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`chlorine-containing ambient as required by the claim. Id. at 24-25 (citing
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`Ex. 1005, 225-8; Ex. 1010 111] 79, 80).
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`Patent Owner responds that Petitioner’s citation to Wang ’485 (Ex.
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`1006, 6:1-S) on page 22 of the Petition (claim chart for claim 56) does not
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`support the proposition of maintaining one of the substrate temperatures
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`above 49°C (claim element 56.e). Prelim. Resp. 6. Patent Owner also
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`Patent RE 40,264 E
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`contends that the Petition improperly segments the elements of claim 56 and
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`fails to show that element 56.g (“operable to effectuate the changing within a
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`preselected time period that is less than the overall process time associated
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`with the etching the first silicon-containing layer and the second silicon-
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`containing layer”) is disclosed in the prior art. Id. at 7~8. According to
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`Patent Owner:
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`Matsumura teaches control of the time for temperature ramp up;
`the time to hold the desired temperature; and the time to cool
`down the temperature. Matsumura does not teach the length of
`the preselected time between the first and second etch,
`i.e.,
`there is no teaching that the preselected time period, let alone a
`preselected time period that is “less than the overall process
`time associated with the etching the first silicon-containing
`layer and the second silicon-containing layer,” as required by
`claim 56, and Tegal has no time interval between temperatures.
`Accordingly, [Petitioner] fails to show this element of claim 56
`in the prior art.
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`Id. at 8.
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`We are not persuaded, at this early stage of the proceeding, that the
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`arguments presented in the Petition are not supported by Wang ’485 and
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`Matsumura. Petitioner contends that Figure 21 of Wang ’485 shows that the
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`etch rate of molybdenum silicide increases from 750 to 1250
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`angstroms/minute over a temperature range from 45°C to 80°C. Pet. 17
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`(citing Ex. 1006, 6: 1-5, Fig. 21). Therefore, the Petition does not rely upon
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`the text of lines 1 to 5 in column 6 of Wang ’485 alone, and Patent Owner
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`does not dispute that Figure 21 indicates increased etch rate over a
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`temperature range of 45°C to 80°C. Regarding Matsumura, the
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`predetermined recipes that depend upon a time and temperature relationship
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`for the heat-processing of semiconductor devices consequently preselect the
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`time and temperature conditions during which processing is conducted. See
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`21
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`Pet. 20 (citing Ex. 1003, 1-7, 6:36-37, Ex. 1010 1] 73); Ex. 1010 11 74.
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`Therefore, the Petition sufficiently shows how independent claim 56 would
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`have been obvious in View of the combination of Tegal, Matsumura, Narita,
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`Thomas, and Wang ’485.
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`In sum, Petitioner shows sufficiently that, on the current record, there
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`is a reasonable likelihood it would prevail in showing that claims 56-58
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`would have been obvious in view of the combination of Tegal, Matsumura,
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`Narita, Thomas, and Wang ’485.
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`2.
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`Tegal, Matsumura, Narita, Thomas, and Fischl
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`Based on our review of Petitioner’s analysis and supporting evidence,
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`we are persuaded that Petitioner has shown, on the current record, that there
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`is a reasonable likelihood that it would prevail in its obviousness challenge
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`to claims 60, 62, 63, and 71 over the combination of Tegal, Matsumura,
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`Narita, Thomas, and Fischl.
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`As argued by Petitioner (Pet. 29-43), Tegal discloses the desire for
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`increased throughput in plasma etching by running multiple etches at
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`different temperatures in the same chamber. Ex. 1002, 1:43-45, 4:30-31.
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`Thomas provides a stack of layers to be plasma etched in the same chamber
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`at different temperatures that is substitutable in the Tegal process to benefit
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`from Tegal’s increased throughput. Ex. 1005, 3:57-68; Ex. 1010 1[ 65.
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`Thomas further teaches a tungsten silicide layer that is etched at 20°C.
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`Ex. 1005, 3:33-47. Fischl teaches that a silicon dioxide layer forms on
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`tungsten silicide when it is exposed to air, which must be removed by
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`etching at 25°C-150°C before etching the disclosed tungsten silicide layer.
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`Ex. 1007, 3; Ex. 1010 11 91. Therefore, plasma etching the tungsten silicide
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`layer of Thomas in View of Fischl means the temperature for etching the
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`Patent RE 40,264 E
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`surface oxide is different from the temperature for etching the tungsten
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`silicide, and the substrate is processed at a second different temperature as
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`required by claim 60. Pet. 33-34. Because Fischl teaches etching at 25°C-
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`150°C, Fischl discloses maintaining a substrate temperature above room
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`temperature while processing the substrate as required by claim 60. See id.
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`at 34-35.
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`Tegal provides a control system for plasma etching temperatures, but
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`lacks details. Ex. 1002, 4:28-31. Matsumura provides, in detail, a
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`temperature control system suitable for plasma etching processes that
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`includes a contact sensor and predetermined recipes which provide process
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`flexibility. Ex. 1003, 5:60-63. Therefore, the control system of Matsumura
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`effects temperature change to a second substrate temperature with a
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`substrate temperature control circuit within a preselected time as required by
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`claim 60 and in accordance with a “predetermined recipe” that has a “time-
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`temperature relationship.” Id. at 321-7, 6:36-37. Narita improves
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`temperature control during temperature changes in plasma etching processes
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`by using two temperature sensors——a non-contact sensor in addition to a
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`contact sensor. Ex. 1004, 424-10, 5:30-31, Figs. 1, 4.
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`Patent Owner responds that the challenge to claim 60 ‘‘fails to identify
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`any prior art that teaches changing the first substrate temperature to the
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`second substrate temperature ‘within a preselected time to etch the silicide
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`layer.’” Prelim. Resp. 9. As discussed above, at this stage in the
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`proceeding, we are not persuaded by Patent Owner’s argument in View of
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`Matsumura’s control system that includes recipes with a time and
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`temperature relationship that can be applied to etching processes.
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`Patent RE 40,264 E
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`We are persuaded, on this record, that Petitioner’s discussion of the
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`particular operations and structures in Tegal, Matsumura, Narita, Thomas,
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`and Fischl together with the explanations in the Petition, are sufficient to
`establish a reasonable likelihood that claim 60 would have been obvious
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`over the combination of the references.
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`Regarding claims 62, 63, and 71, which each depend from claim 60,
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`changing to the second substrate temperature is “by transferring heat using at
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`least a pressure of gas behind the substrate” as recited in claim 62 or “by
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`transferring energy using at least radiation” as recited in claim 63, and the
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`substrate temperature is maintained “at a selected value within 50 to 100
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`degrees centigrade” as recited in claim 71. We have considered Petitioner’s
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`arguments and evidence and are persuaded, on the present record, that
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`Petitioner has established a reasonable likelihood that it would prevail as to
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`those claims as well.
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`. 3.
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`Tegal,iMatsumura, Narita, and Thomas
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`Based on our review of Petitioner’s analysis and supporting evidence,
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`we are persuaded that Petitioner has shown, on the current record, that there
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`is a reasonable likelihood that it would prevail on its obviousness challenge
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`to claims 51, 55, and 68 over the combination of Tegal, Matsumura, Narita,
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`and Thomas.
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`As argued by Petitioner (Pet. 43-48), the same reasons for combining
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`the disclosures of Tegal, Mat