UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`DANIEL L. FLAMM
`Patent Owner
`
`____________________
`
`Patent No. RE 40,264 E
`____________________
`
`DECLARATION OF DR. STANLEY SHANFIELD IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. RE 40,264 E
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`
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`Page 1 of 101
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`Samsung Exhibit 10(cid:19)(cid:21)
`Samsung Electronics Co., Ltd. v. Daniel L. Flamm
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`

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`
`
`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`
`TABLE OF CONTENTS
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`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 3
`
`BACKGROUND AND QUALIFICATIONS ................................................. 3
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`III. MATERIALS REVIEWED ............................................................................ 7
`
`IV. PERSON OF ORDINARY SKILL IN THE ART .......................................... 8
`
`V. OVERVIEW OF THE ’264 PATENT ............................................................ 9
`A.
`The ’264 Patent ..................................................................................... 9
`B.
`Priority Date of the ’264 Patent........................................................... 13
`
`VI. CLAIM CONSTRUCTION .......................................................................... 14
`
`VII. TECHNICAL BACKGROUND & PRIOR ART CONSIDERED ............... 15
`A.
`Technical Background ......................................................................... 15
`Kadomura ............................................................................................ 16
`B.
`C. Matsumura ........................................................................................... 18
`D. Wang I ................................................................................................. 23
`Narita ................................................................................................... 24
`E.
`F. Wang II ................................................................................................ 27
`
`VIII. THE PRIOR ART DISCLOSES OR SUGGESTS ALL OF THE
`FEATURES OF THE CHALLENGED CLAIMS ........................................ 27
`Kadomura and Matsumura Disclose or Suggest the Features of
`A.
`Claims 27, 32, 37, and 40 .................................................................... 27
`1.
`Claim 27 .................................................................................... 29
`2.
`Claim 32 .................................................................................... 45
`3.
`Claim 37 .................................................................................... 47
`4.
`Claim 40 .................................................................................... 61
`Kadomura, Matsumura and Narita Disclose or Suggest the
`Features of Claims 31 and 50 .............................................................. 62
`1.
`Claim 31 .................................................................................... 64
`
`B.
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`Claim 50 .................................................................................... 66
`2.
`Kadomura, Matsumura and Wang I Disclose or Suggest the
`Features of 27, 34, 37, 41, and 44 ....................................................... 67
`1.
`Claim 27 .................................................................................... 69
`2.
`Claim 34 .................................................................................... 78
`3.
`Claim 37 .................................................................................... 79
`4.
`Claim 41 .................................................................................... 86
`5.
`Claim 44 .................................................................................... 86
`Kadomura, Matsumura, Wang I and Wang II Disclose or
`Suggest the Features of Claims 47 and 48 .......................................... 88
`1.
`Claim 47 .................................................................................... 90
`2.
`Claim 48 .................................................................................... 92
`
`C.
`
`D.
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`IX. CONCLUSION .............................................................................................. 94
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`I, Stanley Shanfield, declare as follows:
`
`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
`
`
`I.
`
`INTRODUCTION
`1.
`
`I have been retained by Samsung Electronics Co., Ltd. (“Petitioner”)
`
`as an independent expert consultant in this proceeding before the United States
`
`Patent and Trademark Office (“PTO”).
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`2. My retention is through Rubin/Anders Scientific, Inc. (“Rubin”).
`
`Rubin bills $385 per hour for my services in this matter, which is my regular and
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`customary rate.
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`3. My compensation is in no way contingent on the nature of my
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`findings, the presentation of my findings in testimony, or the outcome of this or
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`any other proceeding. I have no other interest in this proceeding.
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`4.
`
`I have been asked to consider whether certain references disclose or
`
`suggest the features recited in the claims of U.S. Patent No. RE 40,264 E (“the
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`’264 Patent”) (Ex. 1001)1. My opinions are set forth below.
`
`II. BACKGROUND AND QUALIFICATIONS
`5.
`I am an independent consultant. All of my opinions stated in this
`
`declaration are based on my own personal knowledge and professional judgment.
`
`
`1 Where appropriate, I refer to exhibits I understand will be attached to the petition
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`for Inter Partes Review of the ’264 patent.
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`3
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`In forming my opinions, I have relied on my knowledge and experience in
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`designing, developing, and researching plasma processing systems.
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`6.
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`I am over 18 years of age and, if I am called upon to do so, I would be
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`competent to testify as to the matters set forth herein. A copy of my current
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`curriculum vitae, which details my education and professional and academic
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`experience, is attached as an addendum with this declaration. The following
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`provides an overview of some of my experience that is relevant to the matters set
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`forth in this declaration.
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`7.
`
`I received a B.S. in Physics from the University of California, Irvine
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`in 1977. I received the University of California Regents Award for Outstanding
`
`Research Project for my experimental and theoretical work on rotating relativistic
`
`electron beams. Under full ERDA (DOE) scholarship, I received a Ph.D. in
`
`Physics from the Massachusetts Institute of Technology in 1981.
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`8.
`
`After receiving my doctorate degree, I worked at Spire Corporation in
`
`Bedford, Massachusetts from 1981-1984, where I served as a Staff Scientist, and
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`later, a Senior Staff Scientist. At Spire, I developed new methods for low
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`temperature deposition of plasma-assisted CVD epitaxial silicon. In addition, I
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`built, operated, and characterized an ion-assisted deposition system for making
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`coating for semiconductor and machine tool industries.
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`4
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`From 1985-1999, I worked at Raytheon Corporation. As staff and
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`9.
`
`later as Section manager, I developed reactive ion etching (RIE) processes for
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`patterning dielectrics (silicon dioxide, silicon nitride, silicon oxynitride, etc.),
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`conductive layers (aluminum-copper, copper-silicon, W-silicide, TaN, doped
`
`polysilicon, etc.) and organic layers (photoresist, polyimide, etc.). For example, I
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`developed a low damage, high selectivity process as part of the FET gate formation
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`step. I was responsible for purchasing equipment and developing processes for
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`several plasma systems typical of those used in the semiconductor industry,
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`including load-locked RIE, microwave ECR RIE, barrel etchers, single-wafer
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`elevated temperature RIE systems, etc.
`
`10.
`
`In 1996, I became the Manager of Semiconductor Operations at
`
`Raytheon. As Manager, I built and led a 300 employee, $60 million revenue-
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`generating semiconductor development, commercial system design, and electronic
`
`module manufacturing operation. I was responsible for and worked closely with
`
`teams that purchased and process-qualified production dry etching equipment,
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`including high throughput, elevated temperature RIE (Chlorine and Fluorine-based
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`chemistry), low temperature RIE, and high rate barrel etchers. I participated in
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`efforts to increase the productivity of dry etching processes, including the
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`incorporation of gas backside wafer cooling and increased capacity liquid
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`temperature control systems.
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`5
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`11. From 1999-2001, I worked at AXSUN Technologies as part of the
`
`founding team, first as the Director of Manufacturing & Wafer Fab Technology,
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`and later, as the Vice President of Operations. As Director of Manufacturing &
`
`Wafer Fab Technology, I led device and module manufacturing, creating a wafer
`
`fab and circuit board assembly infrastructure; my responsibilities included hiring
`
`over 70 individuals and leading production design efforts. In my role as Vice
`
`President of Operations, I designed, fabricated, and productized AXSUN’s
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`microelectromechanical (MEM) Fabry-Perot optical filter, and managed a new
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`generation of electronics module design. In addition, I established a process and
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`fabrication facility in Belfast, Northern Ireland for producing thick oxide silicon-
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`on-insulator devices. As a result of my work at AXSUN, I was awarded patents on
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`semiconductor processing and control electronics.
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`12.
`
`I have served since 2003 at the Charles Stark Draper Laboratory
`
`(“Draper Laboratory”) in Cambridge, Massachusetts, ultimately becoming a
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`Distinguished Member of Technical Staff and Technical Director in Advanced
`
`Hardware Development. I led the Advanced Hardware Development Division
`
`(approximately 80 staff) in their work on the laboratory’s multi-chip integrated
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`circuit module facility. I directly participated in the development of dry etching
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`processes in this facility for the fabrication of MEM-based gyroscopes, including
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`an adaptation of the Bosch process, and the implementation of other variable-
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`temperature reactive ion etching processes. In addition, I led a team that developed
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`high-selectivity dry etching processes needed in the fabrication of extremely high
`
`density, multi-layer integrated circuit interconnect designs.
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`13.
`
`I have authored more than 25 journal and conference papers; my
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`publications include numerous papers on topics relating to semiconductor
`
`processing, advanced semiconductor devices, electronic circuit design and
`
`packaging. I have been invited to give professional talks at various conferences. I
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`am also a co-inventor of several U.S. Patents.
`
`14.
`
`I am not an attorney and offer no legal opinions, but in the course of
`
`my work, I have had experience studying and analyzing patents and patent claims
`
`from the perspective of a person skilled in the art.
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`III. MATERIALS REVIEWED
`15. The opinions in this Declaration are based on the documents I
`
`reviewed, my knowledge and experience, and professional judgment. In forming
`
`my opinions expressed in this Declaration, I have reviewed the following
`
`materials: U.S. Patent No. RE 40,264 E (Ex. 1001); Prosecution History of U.S.
`
`Patent No. RE 40,264 (Ex. 1003); Prosecution History of U.S. Patent Application
`
`No. 09/151,163 (Ex. 1004); Prosecution History of U.S. Patent Application No.
`
`08/567,224 (Ex. 1005); U.S. Patent No. 6,063,710 (“Kadomura”) (Ex. 1006); U.S.
`
`Patent No. 5,151,871 (“Matsumura”) (Ex. 1007); U.S. Patent No. 4,913,790
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`U.S. Patent No. RE 40,264 E
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`(“Narita”) (Ex. 1008); U.S. Patent No. 5,219,485 (“Wang I”) (Ex. 1009); European
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`Patent Application No. 87311193.4 (“Wang II”) (Ex. 1010), and any other
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`materials I refer to in this declaration in support of my opinions.
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`16. All of the opinions contained in this declaration are based on the
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`documents I reviewed and my knowledge and professional judgment. My opinions
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`have also been guided by my appreciation of how a person of ordinary skill in the
`
`art would have understood the claims and the specification of the ’264 patent at the
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`time of the alleged invention, which I have been asked to initially consider as mid
`
`1997 (September 11, 1997, the filing date of the U.S. Provisional Patent
`
`Application No. 60/058,650 from which the ’264 patent claims priority). My
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`opinions reflect how one of ordinary skill in the art would have understood the
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`’264 patent, the prior art to the patent, and the state of the art at the time of the
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`alleged invention.
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`17. Based on my experience and expertise, it is my opinion that certain
`
`references disclose all the features recited in claims 27, 31, 32, 34, 37, 40, 41, 44,
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`47, 48, and 50 (“challenged claims”) of the ’264 patent, as I discuss in detail
`
`below.
`
`IV. PERSON OF ORDINARY SKILL IN THE ART
`18.
`I was asked to provide my opinion on the level of one of ordinary skill
`
`in the art with respect to the invention of the ’264 patent as of the mid-1997 to
`
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`September 1997 timeframe. Based on my review of the types of problems
`
`encountered in the art, prior solutions to those problems, the rapidity with which
`
`innovations were made, the sophistication of the technology, and the educational
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`level of active workers in the field, I believe a person of ordinary skill in art at that
`
`time would have had at least (i) a Bachelor's degree in engineering, physics,
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`chemistry, materials science, or a similar field, and three or four years of work
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`experience in semiconductor manufacturing or related fields, or (ii) a Master's
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`degree in engineering, physics, chemistry, materials science, or a similar field and
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`two or three years of work experience in semiconductor manufacturing or related
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`fields). More education can supplement practical experience and vice versa.
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`Depending on the engineering background and level of education of a person, it
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`would have taken a few years for the person to become familiar with the problems
`
`encountered in the art and become familiar with the prior and current solutions to
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`those problems. All of my opinions in this declaration are from the perspective of
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`one of ordinary skill in the art as I have defined it here during the relevant
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`timeframe (mid-1997 to September 1997 timeframe).
`
`V. OVERVIEW OF THE ’264 PATENT
`A. The ’264 Patent
`19. The ’264 patent, titled “Multi-Temperature Processing,” is directed to
`
`a method “for etching a substrate in the manufacture of a device.” (Ex. 1001 at
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`9
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`Abstract.) The apparatus used in the method is shown in Figure 1, reproduced
`
`below.
`
`(Ex. 1001 at Fig. 1.)
`
`20. Figure 1 illustrates an etch apparatus including a chamber 12 and a
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`pedestal 18 (substrate holder). (Id. at 3:24-25, 3:32-33, 3:40-41.) Figure 6
`
`illustrates a “block diagram of a substrate holder 600 . . . .” (Id. at 14:27-28.) The
`
`substrate holder 600 includes “a backside surface 608,” which includes a plurality
`
`of zones 608A, 608B, 608C, and 608D. (Id. at 14:31-44.) Each of the zones,
`
`separated from each other by a baffle 605, has an inlet 613 and outlet 611 for
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`Declaration of Dr. Stanley Shanfield
`U.S. Patent No. RE 40,264 E
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`temperature controlled fluid to enter and exit the zones “to heat or cool the upper
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`surface of the substrate holder” that holds an object (e.g., a wafer). (Id. at 14:31-
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`44, 14:62-63, 15:39-40.)
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`(Id. at Fig. 6.) The substrate holder can also include a plurality of heating elements
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`607 that “selectively heat one or more zones . . . .” (Id. at 15:10-15.)
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`21. Referring to figure 7, the operation of the temperature control system
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`is described. The substrate holder receives fluid heated by heating unit 705 and the
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`fluid transfers energy in the form of heat to the substrate holder. (Id. at 16:5-20.)
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`The fluid can also be cooled using a heat exchanger 723. (Id.)
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`
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`(Id. at Fig. 7.) According to the ’264 patent, “[t]he desired fluid temperature is
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`determined by comparing the desired wafer or wafer chuck set point temperature to
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`a measured wafer or wafer chuck temperature . . . . The heat exchanger, fluid flow
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`rate, coolant-side fluid temperature, heater power, chuck, etc. should be designed
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`U.S. Patent No. RE 40,264 E
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`using conventional means to permit the heater to bring the fluid to a setpoint
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`temperature and bring the temperature of the chuck and wafer to predetermined
`
`temperatures within specified time intervals and within specified uniformity limits.
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`(Id. at 16:36–39, 16:50–67.)
`
`B. Priority Date of the ’264 Patent
`22.
`I understand that the ’264 patent claims priority back to U.S. Patent
`
`Application No. 08/567,224 (“the ’224 application”), filed on December 4, 1995
`
`and also claims the benefit of U.S. Provisional Application No. 06/058,650, filed
`
`on September 11, 1997. I have been asked to evaluate the ’224 application and
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`provide my opinion on whether the challenged claims are supported by the ’224
`
`application. In my opinion, the challenged claims are not supported by the ’224
`
`application.
`
`23. Each of the challenged claims of the ’264 application recites the
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`concept of changing a first substrate temperature to a second substrate temperature
`
`in a preselected time interval. (See, e.g., Ex. 1001, claim 27 (“substrate
`
`temperature is changed from the selected first substrate temperature to the selected
`
`second substrate temperature . . . within a preselected time interval”), claim 36
`
`(“change the substrate temperature from the selected first substrate temperature to
`
`the selected second substrate temperature within a preselected time period”).)
`
`Claim 37 further recites two separate temperature sensors: “a substrate
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`temperature sensor” and “a substrate holder temperature sensor.” (Ex. 1001, claim
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`37.)
`
`24.
`
`I have reviewed the ’224 application and determined that these
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`features are not disclosed in the ’224 application. The ’224 application describes
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`transferring a wafer between two chambers in which the pedestals are maintained
`
`at different temperatures. (Ex. 1005 at 45-46.) But it does not disclose the
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`substrate temperature is changed from a first substrate temperature to a second
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`substrate temperature in a preselected time interval as required by claims 27 and
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`37. The ’224 application describes a thermocouple for measuring the temperature
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`of the substrate support but does not describe two separate temperature sensors
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`(“substrate temperature sensor” and “substrate holder temperature sensor”) as
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`required by claim 37. In my opinion, nothing in the specification, drawings, or
`
`elsewhere of the ’224 application discloses or suggests to one of ordinary skill in
`
`the art the above identified missing features.
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`VI. CLAIM CONSTRUCTION
`25.
`I have been asked to give all the claim terms of the challenged claims
`
`for the ’264 patent their plain and ordinary meaning, as would be understood by a
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`person of ordinary skill in the art, at the time of the alleged invention, which I
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`understand is mid-1997 to September 1997 timeframe (e.g., September 11, 1997,
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`the filing date of the ’650 provisional) having taken into consideration the
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`Declaration of Dr. Stanley Shanfield
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`language of the claims, the specification, and the prosecution history of record. I
`
`applied this understanding in my analysis and in forming my opinions in this
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`Declaration.
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`VII. TECHNICAL BACKGROUND & PRIOR ART CONSIDERED
`A. Technical Background
`26. The prior art I considered and discuss in this declaration, and the ’264
`
`patent, generally relates to techniques for the manufacture, fabrication, and/or
`
`production of semiconductor components and devices prior to September 1997.
`
`As I discuss in detail in the sections to follow, the prior art discloses that plasma
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`techniques for the manufacture, fabrication, and/or production of semiconductor
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`components and devices around September 1997 had made significant
`
`advancements. Depending on the application of a device, different etching
`
`processes were used. For instance, techniques were known that performed plasma
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`etching (more particularly, dry etching) such that different layers of a film were
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`etched at different temperatures. (See generally Ex. 1006.) Sophisticated
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`mechanisms had already been developed that controlled the temperature of both
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`the substrate and the substrate holder such that the time between temperature
`
`changes was preselected and controlled by a processing unit. (See generally Ex.
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`1007.) The features in the challenged claims recite these well-known techniques,
`
`which are disclosed and suggested in the prior art.
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`B.
`Kadomura
`27. Kadomura generally relates to a dry etching method used primarily
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`for the production of semiconductor devices and, in particular, to a dry etching
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`method and apparatus that provides compatibility for anisotropic fabrication and
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`high selectivity. (Ex. 1006 at 1:6–10.) Kadomura discloses applying an etching
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`treatment that includes a plurality of steps to a specimen within the same
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`processing apparatus, wherein the temperature of the specimen is changed between
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`etching in a first step and etching in a second step. (Id. at 2:65–3:5.) Because the
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`disclosed dry etching method conducts each of the etching treatments in the same
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`processing apparatus, the time for changing the specimen temperature between the
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`steps may be shortened. (Id. at 4:46–49.) By conducting the change of specimen
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`temperature within a short period of time, dry etching treatment may be applied
`
`without deteriorating the throughput. (Id. at 4:49–54.)
`
`28. Kadomura discloses a dry etching apparatus 1 (illustrated in figure 4)
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`that includes a diffusion chamber 2 in which a stage 12 supports a “specimen W
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`comprising a semiconductor substrate.” (Id. at 11:8-38.) Kadomura discloses
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`controlling the temperature of specimen W by controlling the temperature of stage
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`12. For example, Kadomura discloses “changing the temperature of a specimen by
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`changing the temperature of a specimen stage supporting the specimen . . .” and
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`further discloses “changing the temperature of the specimen stage to a setting
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`temperature for the specimen . . . .” (Id. at 3:28–37; see also id. at 6:49-51, 7:41-
`
`43, 8:36-39, 10:8-10, 12:37-40.)
`
`
`
`(Id. at Fig. 4 (annotated).)
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`29. Kadomura discloses controlling
`
`the
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`temperature of stage 12
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`(highlighted in orange) (and thereby controlling the temperature of specimen W)
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`by using a combination of a heater and chiller 17 (highlighted in yellow). (Id. at
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`6:30–35, 7:38-47, 10:8-10.) A bias power source 14 (highlighted in red) controls
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`incident ion energy on wafer W. (Id. at 11:42-47.) Feed back control device 25
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`(highlighted in purple) sends signals to cryogenic valves to obtain a predetermined
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`coolant flow rate from the chiller 17. (Id. at 12:37–48.) Kadomura teaches that
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`the temperature sensed by the thermometer 18 is detected by the feed back control
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`device 25 (purple) that “controls the ON–OFF or ON–OFF degree of the cryogenic
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`valve 21, . . . , 23 so as to obtain a gas coolant flow rate previously determined by
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`experiment or calculation based on the difference between the detected temperature
`
`and the predetermined temperature for the specimen W.” (Id.)
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`30. Kadomura discloses three embodiments, each of which applies its dry
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`etching method in a different manner. (Id. at 5:44–56, Figs. 1A–1C, 2A–2C, 3A–
`
`3C.) In each of these embodiments, Kadomura discloses using a first etching step
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`(main etching) that is carried out with the specimen W at a first temperature and a
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`second etching step (overetching) that is carried out with the specimen W at a
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`second temperature. For example, in the first embodiment, the main etching in the
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`first step is applied at a temperature of 20º C, whereas the overetching in the
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`second step is applied at a temperature of -30º C. (Id. at 6:17–28, 6:63–7:7.) In
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`the third embodiment, the main etching in the first step is applied at a first
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`temperature (-30º C), whereas the overetching in the second step is applied at a
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`second temperature (50º C). (Id. at 9:54–62, 10:17–27.)
`
`C. Matsumura
`31. Matsumura discloses a “method of heat–processing semiconductor
`
`devices whereby temperatures of the semiconductor devices can be controlled at
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`devices–heating and –cooling times so as to accurately control their thermal history
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`curve.” (Ex. 1007 at 2:60–65.) Matsumura discloses applying the method to
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`plasma etching – “the present invention has been applied to the adhesion and
`
`baking processes for semiconductor wafers in the above–described embodiments . .
`
`. it can also be applied to any of the ion implantation, CVD, etching and ashing
`
`processes.” (Id. at 10:3–7.)
`
`32. Matsumura discloses processing a wafer W on a wafer-stage 12,
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`which includes upper plate 13 and conductive thin film 14. (Ex. 1007 at 5:13–51,
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`Fig. 5A.) Below, I provided an annotated version of figure 5A for illustrative
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`purposes.
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`U.S. Patent No. RE 40,264 E
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`(Ex. 1007 at Fig. 5A (annotated).) Control system 20 (highlighted in purple) sends
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`signals (SM) to power supply circuit 19 (highlighted in red) to heat semiconductor
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`wafer W (blue) on upper plate 13 (highlighted in orange) by conductive thin film
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`14; and sends signals (SC) to cooling system 23 (highlighted in yellow) to control
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`the amount of coolant supplied to jacket 22. (Id. at 5:52–6:32, Figs. 5A and 5B.)
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`Control system 20 outputs heating SM and cooling SC signals responsive to
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`“inputted recipes and temperature detecting signal.” (See, e.g., id. at 5:58–63.)
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`33. Matsumura explains that a “predetermined recipe” is “information
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`showing a time–temperature relationship and applicable for either heating the
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`object to a predetermined temperature for a predetermined period of time or
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`cooling the object from a predetermined temperature over a predetermined period
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`of time, or for both.” (Id. at 3:1–7 (emphasis added), 6:36–37.) Figures 8 and 9 of
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`Matsumura show methods of substrate processing using the Matsumura control
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`system demonstrating predetermined temperature changes within predetermined
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`time intervals for processing. (Id. at Figs. 8, 9.) For example, figure 9 shows a
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`recipe with a “thermal history curve” showing temperature as a function of time.
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`(Id. at 4:41–42.) This “recipe” has a temperature change from 20° C to 90° C
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`within the first 60 seconds of the process. (Id. at Fig. 8.)
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`U.S. Patent No. RE 40,264 E
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`(Ex. 1007 at Fig. 9.) Based on the input recipe and the detected wafer temperature,
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`Matsumura’s control system 20 controls the heating/cooling of the wafer W. (Id.
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`at 3:10–16, 5:52–6:32, 8:56-9:26, 10:42–63, Figs. 5A and 5B.)
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`34. To better explain Matsumura’s disclosure, consider the description of
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`figure 9, which shows a recipe for the “thermal history curve of the wafer W.” (Id.
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`at 8:56-9:26.) The recipe shown in figure 9 including the different temperature and
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`time points (e.g., P10-P19) is input to CPU 201. (Id. at 8:56-68.) The heating of
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`wafer W is controlled such that “the heat condition of the wafer W passes through
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`the point P11 and reaches the point P12.” (Id. at 9:1-15, Fig. 9.) “When the
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`condition of the wafer W reaches the point P12, the duty cycle of signal SM
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`applied from the PID controller 203 is made equal to 50% to hold the temperature
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`of the wafer W . . . for 30 seconds.” (Id. at 9:16-19.) When the heat condition of
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`U.S. Patent No. RE 40,264 E
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`the wafer reaches P13, “the duty cycle of signal SM . . . is changed . . . to raise the
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`temperature of the wafer . . . .” (Id. at 9:20-23.)
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`35. Matsumura’s process of controlling the temperature of wafer W is
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`summarized here:
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`a stage having a conductive thin film for heating the
`object; a detecting means for detecting temperatures of
`the object; a storing means for previously storing as a
`predetermined recipe, information showing a time-
`temperature relationship and applicable for either heating
`the object
`to a predetermined
`temperature for a
`predetermined period of time or cooling the object from a
`predetermined temperature over a predetermined period
`of time, or for both, and a control means for reading the
`information in the storing means, and for receiving signal
`relating to the temperatures of the object detected by the
`detecting means, and for controlling a period of heat up
`and cool down responsive to the information and signal
`while heating the object by said conductive thin film.
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`(Id. at 3:17-33; see also id. at 2:66-3:16.) One of ordinary skill in the art would
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`have understood that “the object” refers to the semiconductor wafer W and
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`“stage” refers to stage 12 (including upper plate 13 and conductive film 14).
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`U.S. Patent No. RE 40,264 E
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`D. Wang I
`36. Wang I generally relates to a process for etching conductive layers
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`used in semiconductor integrated circuits and, in particular, to a method for etching
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`metal silicides, polycrystalline silicon, and composite silicide-polysilicon
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`structures, as well as reactive plasma gas chemistry for use in such methods. (Ex.
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`1009 at 1:13-19.) Wang I discloses that the etch rate of silicides such as WSix can
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`be increased by increasing the substrate temperature. (Id. at 2:47-52, “Polycide is
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`a layer of metal silicide over a layer polysilicon. Of primary interest here are the
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`refractory metal silicides . . . tungsten silicide, WSix.”) Figures 20 and 21 in Wang
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`I show that an increase in the substrate temperature (by virtue of an increase in the
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`substrate holder temperature) increases the silicide etch rate. (Id. at 6:1-5, “FIGS.
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`20 and 21 illustrate the effect of hexode temperature on polysilicon etch rate and
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`on molybdenum silicide etch rate . . . .”)
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`(Id. at Figs. 20, 21.)
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`E. Narita
`37. Narita discloses a method for treating “a surface of a workpiece while
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`accurately controlling the temperature of the workpiece.” (Ex. 1008 at 2:7–10.)
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`Narita further discloses that the method can be applied to plasma etching and
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`thermal chemical vapor deposition (CVD), among other treatment methods. (Id. at
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`3:3–5.) The disclosed treating method “includes a temperature rise step in which
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`first temperature control is performed and a treatment step in which second
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`temperature control is performed.” (Id. at Abstr.) Figure 1, below, is a schematic
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`of an embodiment for a CVD process where there is a substrate (semiconductor
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`wafer 2) on a substrate holder (support member 5).
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`
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`(Id. at Fig. 1.)
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`38. Figure 1 depicts control section 23 that controls the temperature using
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`two temperature detecting mechanisms: thermocouple 6, which contacts substr