Page 1 of 6
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`Samsung Exhibit 1009
`Samsung Electronics Co., Ltd. v. Daniel L. Flamm
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`U.S.‘ Patent
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`Jul.‘ 14, 1987
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`Sheetl of2
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`4,680,086
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`GAS
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`SUPPLY
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`Page 2 of 6
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`Page 3 of 6
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`1
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`4,680,086
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`2
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`chemistry etch in which the lower electrode of the
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`chamber is grounded. This etch removes unmasked
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`portions of the silicide layer and also etches the upper
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`portions of the polysilicon layer. The edge profile is
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`basically that of an anisotropic etch. A second stage,
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`which is carried out in a second chamber, comprises a
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`high frequency, chlorine chemistry etch in which the
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`RF power is applied to the lower electrode. This pro-
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`cess removes the remaining polysilicon rapidly and
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`anisotropically, without significant undercutting, and
`has a very high selectivity to the underlying silicon
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`dioxide.
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`These and other objects and advantages of the pres-
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`ent invention will be apparent to one skilled in the art
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`from the detailed description below taken together with
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`the drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a simplified cross-sectional view of an appa-
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`ratus suitable for practicing the present invention; and
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`FIGS. 2A—2C are cross-sectional views illustrating
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`various stages during etching according to the princi-
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`ples of the present invention.
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`DETAILED DESCRIPTION OF THE
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`INVENTION
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`5
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`DRY ETCHING OF MULTI-LAYER STRUCTURES
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`FIELD OF THE INVENTION
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`The present invention relates, in general, to the dry
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`etching of multi-layer structures. More particularly, the
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`invention relates to a method useful for dry etching
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`refractory metal silicide/polysilicon structures in the
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`manufacture, for instance, of semiconductor integrated
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`circuits.
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`BACKGROUND OF THE INVENTION
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`Dry etching, as that term is used in the semiconduc-
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`tor industry, encompasses a number of related pro-
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`cesses. The common feature of these processes is the
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`presence of a gas or plasma which contains at least one
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`reactive specie and which is. energized by the applica-
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`tion of RF energy. The gas or plasma is placed in
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`contact with the structure being etched, a reaction takes
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`place at the surface of the material and reacted material
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`is removed in gaseous form.
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`The various distinct dry etching processes include
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`reactive ion etching (RIE) and plasma etching. While
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`the precise definition of these terms is not completely
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`settled, the different processes are typically character- 25
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`ized by the pressure of the gas or plasma, the frequency
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`of the RF energy supplied thereto, the configuration of
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`the chamber in which the reaction takes place, the
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`method of applying the RF energy to the gas or plasma
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`and the chemistry of the gas or plasma. The generic
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`term dry etching will be used throughout to refer to all
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`of these related processes.
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`A structure which is of increasing interest in the field
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`of integrated circuit manufacturing comprises a two
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`layer “sandwich” of polysilicon underlying a refractory
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`metal silicide. Such a structure typically overlies a thin
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`layer of silicon dioxide dielectric, for example, and
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`comprises the gate of an insulated-gate field effect tran-
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`sistor (IGFET) device. It has been found that such a
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`structure is quite difficult to etch using dry etching 40
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`techniques because of the differences in the response of
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`the silicide and polysilicon materials to the etching
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`processes.
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`For small geometry devices, it is necessary to care-
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`fully control the edge profile of the structure being
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`etched. In addition, since the underlying dielectric is
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`often quite thin, a process with a very high selectivity to
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`silicon dioxide is required. Despite numerous attempts,
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`the prior art does not disclose a dry etching process
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`which can effectively etch a silicide/polysilicon struc-
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`ture with good edge profile control and high selectivity
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`to an underlying dielectric.
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`SUMMARY OF THE INVENTION
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`Accordingly, it is an object of the present invention
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`to provide a method for dry etching of multi-layer
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`structures which provides adequate edge profile control
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`and high selectivity to underlying layers.
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`It is a further object of the present invention to pro-
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`vide a method for dry etching of refractory metal silici-
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`de/polysilicon structures which provides adequate
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`edge profile control and high selectivity to underlying
`dielectric layers.
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`These and other objects and advantages of the pres-
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`ent invention are provided by a dry etching process of 65
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`two stages which is carried out in a two chamber dry
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`etching apparatus. A first stage, which proceeds in a
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`first chamber, comprises a low frequency,
`fluorine
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`FIG. 1 is a simplified cross-sectional view of a multi-
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`chamber dry etching apparatus which is suitable for use
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`in practicing the present invention. A similar commer-
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`cial etcher, although having three chambers instead of
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`two, is available from the Zylin Corporation. The appa-
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`ratus comprises a first etch chamber 10 and a second
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`etch chamber 11. Wafers to be etched are loaded into
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`first chamber 10 by means of an access door 12. Etched
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`wafers are removed from second chamber 11 by means
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`of an access door 13. Wafers are transported from first
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`chamber 10 to second chamber 11 by means of a wafer
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`transport 14 which carries the wafers through a passage
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`15 which joins first chamber 10 to second chamber 11.
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`Inside first chamber 10 are a lower electrode 18 and
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`an upper electrode 19. Electrodes 18 and 19 have gener-
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`ally planar surfaces and are parallel to one another.
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`Both upper electrode 19 and lower electrode 18 are
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`electrically isolated from the walls of chamber 10. Simi-
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`larly, a lower electrode 20 and an upper electrode 21 are
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`within second chamber 11, have generally planar, paral-
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`lel surfaces and are electrically isolated from the walls
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`of chamber 11. As is familiar, lower electrodes 18 and
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`20 are adapted to hold a wafer during the etching pro-
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`cess. Upper electrodes 19 and 21 are of the “shower
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`hea ” type. That is, both are adapted to dispense the
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`reactive gases into the space between the two elec-
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`trodes by means of a plurality of openings 22 in their
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`lower surfaces.
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`A first gas supply and flow control apparatus 25 is
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`coupled to upper electrode 19 in order to supply a con-
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`trolled flow of the chosen process gases to first chamber
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`10. Similarly, a second gas supply and flow control
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`apparatus 26 is coupled to upper electrode 21 in order to
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`supply a controlled flow of the chosen process gases to
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`second chamber 11. For purposes of the present inven-
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`tion, it is important that each chamber have a dedicated
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`gas supply and flow control apparatus. Similarly, a first
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`vacuum system 27 is coupled through a pressure control
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`valve 28 to first chamber 10 to control the pressure
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`therein and to remove reaction products therefrom. A
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`second vacuum system 32 is coupled through a second
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`Page 4 of 6
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`4,680,086
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`3
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`pressure control valve 33 to second chamber 11 to con-
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`trol the pressure therein and to remove reaction prod-
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`ucts therefrom.
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`First chamber 10 is energized, in the preferred em-
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`bodiment of the present invention, by means of a 50
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`KHz power supply 30 which is electrically coupled to
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`upper electrode 19. Lower electrode 18 is preferrably
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`grounded. Second chamber 11 is energized, in the pre-
`ferred embodiment, by means of a 13.56 MHz power
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`supply 31 which is electrically coupled to lower elec-
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`trode 20. Upper electrode 21 is preferrably grounded.
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`In operation, a wafer is loaded into first chamber 10
`via access door 12 and placed on lower electrode 18.
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`Access door 12 is closed and vacuum system 27 re-
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`moves the atmosphere from chamber 10 and and vac-
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`uum system 32 removes the atmosphere from chamber
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`11. Once the internal pressure is at a predetermined
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`level, gas supply and flow control apparatus 25 and 50
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`KHz power supply 30 are activated and the first stage
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`of the etching process commences. When an endpoint
`of the first stage is reached, which is determined either
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`by time or other well known means, gas supply and
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`flow control apparatus 25 and 50 KHz power supply 30
`are de-activated, wafer transport 14 is operated to trans-
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`fer the wafer from lower electrode 18 to lower elec-
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`trode 20 and the second stage of the etch process is
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`commenced. Gas supply and flow control apparatus 26
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`and 13.56 MHz power supply 31 are activated. When an
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`endpoint is reached, these are deactivated, the internal
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`pressure is equalized with external atmospheric pres-
`sure, and the wafer is removed from lower electrode 20
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`by means of access door 13.
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`In the preferred embodiment of the present invention,
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`the first stage of the etch process is designed to rapidly
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`and anisotropically etch a silicide material. Of particular
`interest are refractory metal silicide materials such as
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`tungsten disilicide,
`titanium disilicide, molybdenum
`disilicide and tantalum disilicide. It is also possible to
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`alter the first stage process slightly in order to optimally
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`etch a refractory metal layer. In the preferred embodi-
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`ment,
`the process gases supplied are tetrafluorome-
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`thane, CF4, (at a flow rate of approximately 190 SCCM)
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`and oxygen (at a flow rate of approximately 5 SCCM).
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`The pressure maintained in chamber 10 is approxi-
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`mately 1 torr, the power supplied is approximately 80
`watts, and the temperature is approximately 20 degrees
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`C. The preferred electrode spacing is approximately 1
`inch. For tungsten silicide, this process produces an
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`etch rate of approximately 2500 angstroms per minute
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`and a relatively anisotropic edge profile. End point
`detection is achieved simply by timing the reaction,
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`since it is simply required that the silicide be cleared and
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`some portion of the polysilicon be etched. In addition to
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`CF4, it is believed that CFCI3, CF2Cl2, CF3Cl, NF3,
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`SF5, C2F5Cl and C2F¢ might be suitable for the first
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`stage of the process.
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`The second stage process is, according to the pre-
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`ferred embodiment, optimized to rapidly and anisotrop-
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`ically etch the polysilicon without significant undercut-
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`ting and with a high selectivity to the underlying dielec-
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`tric, typically silicon dioxide. The process gases chosen
`are helium (flow rate approximately 466 SCCM), hy-
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`drogen chloride (flow rate approximately 143 SCCM)
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`and hydrogen iodide (flow rate approximately 17
`SCCM). The pressure in chamber 11 is maintained at
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`approximately 1.75 Torr, the temperature is approxi-
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`mately 5 degrees C. and the power applied is approxi-
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`mately 200 watts. The preferred electrode spacing is
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`approximately 0.5 inch. End point detection is by means
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`of monitoring changes in the DC bias between the
`upper and lower electrode, as is familiar in the art. To
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`ensure complete removal of the polysilicon, a 100%
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`overetch is preferrably used after the endpoint is de-
`tected. This process produces very good etch charac-
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`teristics and has a selectivity to silicon dioxide of ap-
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`proximately 100:1. No observable undercut is apparent
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`in photomicrographs of samples etched according to
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`this process and the overall edge profile is substantially
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`anisotropic. In addition to HCl, it is believed that C12,
`BCI3, CCI4 and SiCl4 might be suitable for the second
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`stage of the process.
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`FIGS. 2A—2C more completely illustrate the various
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`stages involved in the practice of the present invention.
`FIG. 2A illustrates a structure immediately prior to
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`etching. An underlying substrate 40, such as a silicon
`wafer or the like, forms the base for the structure. Im-
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`mediately overlying substrate 4[) is a relatively thin
`dielectric layer 41. For instance, layer 41 may comprise
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`a gate oxide layer of approximately 250 angstroms
`thickness. Overlying dielectric layer 41 is a polysilicon
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`layer 42 which may comprise, for instance, a portion of
`a multi-level gate electrode structure. Polysilicon layer
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`42 is typically heavily doped for good conductivity and
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`may be approximately 2500 angstroms thick. Overlying
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`polysilicon layer 42 is a silicide layer 43 which may
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`comprise, for instance, a tungsten disilicide layer form-
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`ing a portion of a multi-layer gate electrode structure
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`and having a thickness of approximately 2500 ang-
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`stroms. Overlying silicide layer 43 is a patterned photo-
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`resist layer 44 which is used to create the pattern in the
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`underlying layers.
`Photoresist layer 44 may be any of a large number of
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`well known photoresist materials whose properties and
`used are familiar. Photoresist layer 44 is preferrably
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`pre-treated with a 125 degree C. bake for approximately
`30 minutes and exposed with deep UV for stabilization
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`purposes.
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`FIG. 2B illustrates the structure after the first stage of
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`the etch process. Except under patterned photoresist
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`layer 44, all of silicide layer 43 has been removed in a
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`substantially anisotropic fashion. In addition, the first
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`stage etch has proceeded slightly into polysilicon layer
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`42. In the preferred embodiment, approximately 500
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`- angstroms of polysilicon are removed.
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`FIG. 2C illustrates the structure after the final stages
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`of the etch process. The second stage etch has carried
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`the pattern down through the remainder of polysilicon
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`layer 42 and stopped at dielectric layer 41. In addition,
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`a subsequent resist strip operation has removed the
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`patterned photoresist. The edge profile illustrated in
`FIG. 2C, substantially anisotropic throughout with no
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`observable undercut, is consistent with actual photomi-
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`crographs of samples etched according to the detailed
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`process description given above.
`As will be apparent to one skilled in the art, the dis-
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`closed process provides an improved method for etch-
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`ing multiple layer structures and, particularly, an im-
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`proved method for etching silicide/polysilicon struc-
`tures for use in semiconductor integrated circuit manu-
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`facture. The two stage process provides rapid, aniso-
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`tropic etching of the overlying silicide and also pro-
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`vides rapid, anisotropic etching of the underlying
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`polysilicon with a high degree of selectivity to the un-
`derlying dielectric.
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`While the present invention has been described with
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`reference to a preferred embodiment thereof, various
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`Page 5 of 6
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`4,680,086
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`6
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`5
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`removing said substrate from said second dry etch
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`modifications and changes thereto will be apparent to
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`chamber after exposed portions of said polysilicon
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`one skilled in the art and are within the spirit and scope
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`have been completely removed wherein the lower
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`of the present invention.
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`I claim:
`energy of the first RF frequency and the support of
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`the substrate on the grounded electrode are such
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`1. A method for dry etching a rnulti-layer structure
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`that the silicide is etched rapidly and anisotropi-
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`comprising a refractory metal silicide overlying a
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`cally, while the higher energy of the second RF
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`polysilicon material overlying a dielectric material
`frequency and the support of the substrate on the
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`comprising the steps of:
`powered electrode are such that the polysilicon is
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`forming a patterned photoresist layer overlying said
`eteched rapidly and anisotropically without sub-
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`refractory metal silicide layer of said multi-layer
`stantially etching the dielectric material.
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`structure to protect portions of said silicide layer;
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`2. A method according to claim 1 wherein said first
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`supporting a substrate bearing said multi-layer struc-
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`reactive gas mixture comprises tetrafluormethane and
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`ture on a grounded electrode in a first parallel
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`oxygen and said first frequency RF energy is at approxi-
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`plate-type dry etch chamber;
`mately 50 KHz.
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`energizing a first reactive gas mixture comprising at
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`3.. A method according to claim 1 wherein said sec-
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`least one fluorine-containing compound in said first
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`ond_reactive gas mixture comprises hydrogen chloride
`dry etch chamber with energy of a‘ first RF fre-
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`and hydrogen iodide and said second frequency RF
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`quency coupled to a power electrode in said first
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`energy is at approximately 13.56 MHz.
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`chamber to completely remove unprotected por-
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`4. A method according to claim 2 wherein a pressure
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`tions of said refractory metal silicide;
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`in said first dry etch chamber is maintained at approxi-
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`transporting said substrate from said first dry etch
`mately one Torr.
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`chamber to a second parallel plate-type dry etch
`5. A method according to claim 3 wherein a pressure
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`chamber after unprotected portions of said refrac-
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`in said second dry etch chamber is maintained at ap-
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`tory metal silicide have been completely removed
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`25 proximately 1.75 Torr.
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`to expose portions of said polysilicon;
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`6. A method according to claim 1 wherein:
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`said first
`reactive gas mixture comprises tetra-
`supporting said substrate on a powered electrode in
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`fluoromethane and oxygen at a pressure of approxi-
`said second parallel plate-type dry etch chamber;
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`mately l Torr;
`energizing a second reactive gas mixture comprising
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`at least one chlorine-containing compound in said
`said first frequency is approximately 50 KHz;
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`said second reactive gas mixture comprises hydrogen
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`second dry etch chamber with energy of a second
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`chloride and hydrogen iodide at a pressure of ap-
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`RF frequency higher than said first RF frequency
`. proximately 1.75 Torr; and
`coupled to said powered electrode to completely
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`said second frequency is approximately 13.56 MHz.
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`III
`*
`It
`I!
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`remove unprotected portions of said polysilicon;
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`and
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`Page 6 of 6