Page 1 of 29
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`Samsung Exhibit 1001
`Samsung Electronics Co., Ltd. v. Daniel L. Flamm
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`Apr. 29,2008
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`US RE40,264 E
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`US RE40,264 E
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`US RE40,264 E
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`US RE40,264 E
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`U.S. Patent
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`Apr. 29, 2008
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`Sheet 12 of 15
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`US RE40,264 E
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`Page 13 of 29
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`Fluid at
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`Sheet 14 of 15
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`US RE40,264 E
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`Photoresist
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`Tungsten Silicida
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`Poiysiticon
`Silicon dioxide
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`Sheet 15 of 15
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`Us RE40 264 E
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`B Temp reduced
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`Intensityat520nm
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`Resist ashed in 02
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`Constant Temperature
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`A. SF6 native oxide "breakthrough"
`B. Clg plasma is ignited
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`0. wet, begins to clear (endpoint)
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`D. Polysilicon is exposed
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`E. Polysilicon cleared to oxide
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`H. Plasma extinguished and O2 teed
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`IJOQ plasma is started
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`J 02 plasma is extinguished.
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`Fig. 10
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`Page 16 of 29
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`1
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`MULTI-'l'EMPERA'l‘URE PROCESSING
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`Matter enclosed in heavy brackets [ ] appears in the
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`original patent but forms no part of this reissue specifi-
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`cation; matter printed in italics indicates the additions
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`made by reissue.
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`CROSS-REFER E NC E TO R ET ATED
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`APPI ICATIONS
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`This present application is a continuation-in-part of US.
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`application Ser. No. 60/058,650 filed Sep. 11, 1997, and a
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`continuation—in-part of U.S. application Ser. No. 08/567,224
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`filed Dec. 4, 1995, now abandoned which are hereby incor-
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`porated by reference for all purposes.
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`BACKGROUND OF THE INVENTION
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`This invention relates generally to p asma processing.
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`More particularly, one aspect of the invention is for greatly
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`improved plasma processing of devices using an in-situ
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`temperature application technique. Another aspect of the
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`invention is illustrated in an example with regard to plasma
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`etcl1ir1g or resist stripping used in tlie manufacture of semi-
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`conductor devices. The invention is also of benefit in plasma
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`assisted chemical vapor deposition (CVD) for the manufac-
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`ture of semiconductor devices. But it will be recognized that
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`the invention has a wider range of applicability. Merely by
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`way of example, the invention also can be applied in other
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`plasma etching applications, and deposition of materials
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`such as silicon, silicon dioxide, silicon nitride, polysilicon,
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`among others.
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`Plasma processing techniques can occur in a variety of
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`semiconductor manufacturing processes. Examples of
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`plasma processing techniques occur in chemical dry etching
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`(CDE),
`ion-assisted etching (IAE), and plasma enhanced
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`chemical vapor deposition (PECVD),
`including remote
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`plasma deposition (RPCVD) and ion-assisted plasma
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`enhanced chemical vapor deposition (IAPECVD). These
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`plasma processing techniques often rely upon radio fre-
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`quency power (rf) supplied to ar1 inductive coil for providing
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`power to produce with the aid of a plasma.
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`Plasmas can be used to form neutral species (i.e.,
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`uncharged) for purposes of removing or forming films in the
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`manufacture of integrated circuit devices. For instance,
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`chemical dry etching is a technique which generally depends
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`on gas-surface reactions involving these neutral species
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`without substantial ion bombardment.
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`In a number of manufacturing processes, ion bombard-
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`ment to substrate surfaces is often undesirable. This ion 7
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`bombardment, however, is known to have harmful eifects on
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`properties of material layers in devices and excessive ion
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`bombardment flux and energy can lead to intermixing of
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`materials in adjacent device layers, breaking down oxide
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`in the processing environment into substrate material layers,
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`harmful changes in substrate morphology (e.g.
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`amophotization), etc.
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`Ion assisted etching processes, however, rely upon ion
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`bombardment to the substrate surface in defining selected
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`have a lower selectivity relative to conventional CDE pro-
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`cesses. Hence, CDE is often chosen when high selectivity is
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`desired and ion bombardment to substrates is to be avoided.
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`In generally most,
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`maintain temperature in a “batch” mode. That is, the tem-
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`perature of surfaces in a chamber and of tlie substrate being
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`US RE40,264 E
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`2
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`processed in such chamber are controlled to be at a sub-
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`stantially a single value of temperature during processing.
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`From the above it is seen that an improved tecl1r1ique,
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`including a method and apparatus, for alasma processing is
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`often desired.
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`SUMMARY OF THE INVENTION
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`The present invention provides a technique, including a
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`method and apparatus, for fabricating a product using a
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`plasma discharge. One aspect of the present technique relies
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`upon r11ulti-stage etching processes for selectively removing
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`a film on a workpiece using di ering temperatures.
`It
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`overcomes serious disadvantages of prior art methods in
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`which throughput and etching rate were lowered in order to
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`avoid excessive device damage to a workpiece. In particular,
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`this teclmique is extremely beneficial for removing resist
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`masks which have been used to effect selective ion implan-
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`tation of a substrate in some embodiments. In general,
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`implantation of ions into a resist masking surface causes the
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`upper surface of said resist to become extremely cross-
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`li11ked and contaminated by materials from the ion bom-
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`bardment. If the cross-linked layer is exposed to excessive
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`temperature, it is prone to rupture a11d forms contarninative
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`particulate matter. Hence, the entire resist layer is often
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`processed at a low temperature to avoid this particle prob-
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`lem. Processing at a lower temperature often requires exces-
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`sive time which lowers throughput. Accordingly, the present
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`invention overcomes these disadvantages of conventional
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`processes by rapidly removing a majority of resist at a higher
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`temperature after an ion implanted layer is removed without
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`substantial particle generation at a lower temperature.
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`In another aspect, the present invention provides a process
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`which utilizes temperature changes to achieve high etch
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`rates wl1ile simultaneously maintaining high etch selectivity
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`between a layer which is being pattered or removed other
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`material layers. An embodiment of this process advanta-
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`geously employs a sequence of temperature changes as an
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`unexpected means to avoid various types of processing
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`damage to the a device and material layers. A novel inven-
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`tive means for effecting a suitable controlled change in
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`temperature as part of a process involves the use of a
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`workpiece support which has low thermal mass ir1 compari-
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`son to the heat transfer means. In an aspect of this invention,
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`a fluid is utilized to change the temperature of a workpiece.
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`In another aspect, the thermal capacity of a circulating fluid
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`is sufiiciently greater than the thermal capacity of the
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`workpiece support that it pemiits maintaining the workpiece
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`at a substantially uniform temperature.
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`Still another aspect of the invention provides an apparatus
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`for etching a substrate in the manufacture of a device using
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`diiferent
`temperatures during etching. The apparatus
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`includes a chamber and a substrate holder disposed in the
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`chamber. The substrate holder has a selected thermal r11ass to
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`facilitate changing the temperature of the substrate to be
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`etched. That is, the selected thermal mass of the substrate
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`holder allows for a change from a first temperature to a
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`second temperature within a characteristic time period to
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`process a film. The present apparatus can, for example,
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`provide different processing temperatures during an etching
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`process or the like.
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`invention achieves these benefits in the
`The present
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`context of known process technology. However, a further
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`understanding of the nature and advantages of the present
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`invention may be realized by reference to the latter portions
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`of the specification and attached drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a simplified diagram of a plasma etching
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`apparatus according to the present invention;
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`Page 17 of 29
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`3
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`FIGS. 2A—23 are simplified configurations using wave
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`adjustment circuits according to the present invention;
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`FIG. 3 is a simplified diagram of a chemical vapor
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`deposition apparatus according to the present invention;
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`FIG. 4 is a simplified diagram of a stripper according to
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`the present invention;
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`FIGS. 5A—5C are more detailed simplified diagrams of a
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`helical resonator according to the present invention:
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`FIG. 6 is a simplified block diagram of a substrate holder
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`according to the present invention:
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`FIG. 7 is a simplified diagram of a temperature control
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`tion‘3
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`FIG. 8 is a simplified diagram of a fluid reservoir system
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`according to an embodiment of the present invention;
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`FIG. 9 is a [simplified diagram of a] simplified diagram of
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`a semiconductor substrate according to an embodiment of
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`the present invention; and
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`FIG. 10 is a simplified [flow diagram ofa heating] process
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`according to the present invention.
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`DETAILED DESCRIPTION OF THE
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`INVENTION
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`V
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`FIG. 1 is a simplified diagram ofa plasma etch apparatus
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`10 according to the present invention. This etch apparatus is
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`provided with an inductive applicator. e.g.. inductive coil.
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`This etch apparatus depicted; however;
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`illustration, and should not limit the scope of the claims as
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`defined herein. One of ordinary skilled in the art may
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`implement the present invention with other treatment cham-
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`bers and the like.
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`The etch apparatus includes a chamber 12, a feed source
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`14; ar1 exhaust 16; a product support check or pedestal 18,
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`an inductive applicator 20; a radio frequency (“rt”) power
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`source 22 to the inductive applicator 20, wave adjustment
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`circuits 24, 29 (WACS), a radio frequency power source 35
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`to the pedestal 18, a controller 36, an agile temperature
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`control means [19], and other elements. Optionally, the etch
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`apparatus includes a gas distributor 17.
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`The chamber 12 can be any suitable chamber capable of
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`housing a product 28, such as a wafer to be etched, and for
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`providing a plasma discharge therein. The chamber can be a
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`domed chamber for providing a uniform plasma distribution
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`over the product 28 to be etched; but the chamber also car1
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`be configured in other shapes or geometries, e.g., flat ceiling,
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`truncated pyramid, cylindrical, rectangular, etc. Depending
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`upon the application, the chamber is selected to produce a
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`uniform entity density over the pedestal 18, providing a high
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`density of entities (i.e., etchant species) for etching unifor-
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`mity.
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`The product support chuck can rapidly change its tern-
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`perature in ways defined herein as well as others. The wafer
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`is often thermally coupled to the support check which
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`permits maintaining the wafer temperature in a known
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`relationship with respect to the chuck. Coupling will often
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`comprise an electrostatic chuck or mechanical clamps,
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`which apply a pressure to bring the product
`into close
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`proximity with the support check, which enables a relatively
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`good thermal contact between the wafer and support chuck.
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`The support chuck and wafer are often maintained at a
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`substantially equal temperature. A pressure of gas is often
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`applied through small openings in the support chuck behind
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`the wafer in order to improve thermal contact and heat
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`transfer between the wafer and support chuck.
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`The present chamber includes a dome 25 having an
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`interior surface 26 made of quartz or other suitable materi-
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`US RE40,264 E
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`10
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`4
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`als. The exterior surface of the chamber is typically a
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`dielectric material such as a ceramic or the like. Chamber 12
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`also includes a process kit with a focus ring 32, a cover (not
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`shown), and other elements. Preferably,
`the plasma dis-
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`charge is derived from the inductively coupled plasma
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`source that is a de—coupled plasma source (“DPS”) or a
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`helical resonator; although other sources car1 be employed.
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`The de—coupled source originates from rf power derived
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`fron1 the inductive applicator 20. Inductively coupled power
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`is derived from the power source 22. The rf signal frequen-
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`cies ranging from 800 kHz to 80 MHZ can be provided to the
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`inductive applicator 20. Preferably, the rf signal frequencies
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`range from 5 MHz to 60 MHz. The inductive applicator
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`(e.g., coil, antenna, transmission line, etc.) overlying the
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`chamber ceiling can be made using a variety of shapes and
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`ranges of shapes. For example, the inductive applicator can
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`be a single integral conductive film, a transmission line, or
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`multiple coil windings. The shape ofthe inductive applicator
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`and its location relative to the chamber are selected to
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`~ provide a plasma overlying the pedestal to improve etch
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`uniformity.
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`The plasma discharge (or plasma source) is derived from
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`the inductive applicator 20 operating with selected phase 23
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`ar1d ar1ti-pl1ase 27 potentials (i.e., voltages) that substantially
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`cancel each other. The controller 36 is operably coupled to
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`the wave adjustment circuits 24, 29. In one embodiment,
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`wave adjustment circuits 24, 29 provide an inductive appli-
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`cator operating at full-wave multiples 21. This embodiment
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`of full-wave multiple operation provides for balanced
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`capacitance ofphase 23 and anti-phase voltages 27 along the
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`inductive applicator (or coil adjacent to the plasma). This
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`full-wave multiple operation reduces or substantially elimi-
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`nates the amount of capacitively coupled power from the
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`plasma source to chamber bodies (e.g.; pedestal, walls,
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`wafer, etc.) at or close to ground potential. Alternatively, the
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`wave adjustment circuits 24, 29 provide an inductive appli-
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`cator that
`is elfectively made shorter or longer than a
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`full-wave length multiple by a selected amount,
`thereby
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`operating at selected phase and anti-phase voltages that are
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`not full-wave multiples. Alternatively, more than two, one or
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`even no wave adjustment circuits can be provided in other
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`embodiments. But ir1 all of these above embodiments, the
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`phase and anti-phase potentials substantially cancel each
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`thereby providing substantially no capacitively
`other,
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`coupled power from the plasma source to the chamber
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`bodies.
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`In alternative embodiments. the wave adjustment circuit
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`ca11 be configured to provide selected phase and anti-phase
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`coupled voltages coupled from the inductive applicator to
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`the plasma that do not cancel. This provides a controlled
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`potential between the plasma and the chamber bodies, e.g.,
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`the substrate, grounded surfaces. walls, etc.
`In one
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`embodiment; the wave adjustment circuits can be used to
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`selectively reduce current (i.e., capacitively coupled current)
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`to the plasma. This can occur when certain high potential
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`diiference regions of the inductive applicator to the plasma
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`are positioned (or kept) away from the plasma region (or
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`inductor-containing-the-plas111a region) by making them go
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`into the wafer adjustment circuit assemblies, which are
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`typically configured outside of the plasma region. In this
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`embodiment, capacitive current is reduced and a selected
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`degree of synunetry between the phase and anti-phase of the
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`coupled voltages is maintained, thereby provided a selected
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`potential or even substantially ground potential. In other
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`embodiments, the wave adjustment circuits can be used to
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`selectively increase current
`(i.e., capacitively coupled
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`current) to the plasma.
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`Page 18 of 29
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`US RE40,264 E
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`5
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`As shown, the wave adjustment circuits are attached (e.g.,
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`connected, coupled, etc.) to ends of the inductive applicator.
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`Altematively, each of these wave adjustment circuits can be
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`attached at an intermediate position away from the inductive
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`application ends. Accordingly, upper and lower tap positions
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`for respective wave adjustment circuits can be adjustable.
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`But both the inductive applicator portions below and above
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`cach tap position are activc. That is, they both can interact
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`with the plasma discharge.
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`A sensing apparatus can be used to sense plasma voltage
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`which is used to provide automatic turning of the wave
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`adjustment circuits a11d any rf matching circuit between the
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`rf generator and the plasma treatment chamber. This sensing
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`apparatus can maintain the average AC potential at zero or
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`a selected value relative to ground or any other reference
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`value. This wave adjustment circuit provides for a selected
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`potential difference between the plasma source and chamber
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`bodics. Thcsc chambcr bodics may be at a ground potential
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`or a potential supplied by another bias supply, e.g., See FIG.
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`1 reference numeral 35. Examples of wave adjustment
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`circuits are described by way of the FIGS. below.
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`For instance, FIGS. 2A to 2E are simplified configurations
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`using the wave adjustment circuits according to the present
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`invention. These simplified configurations should not limit
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`the scope of the claims herein. In an embodiment, these ,
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`wave adjustment circuits employ substantially equal circuit
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`elements (e.g.,
`inductors, capacitors,
`transmission li11e
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`sections, and others) such that the electrical length of the
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`wave adjustmcnt circuits in scrics with thc inductivc appli-
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`cator coupling power to the plasma is substantially an
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`integral multiple of one wavelength. In other embodiments,
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`the circuit elements provide for inductive applicators at
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`other wavelength multiples, e.g., one-sixteenth-wave, one-
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`eighth—wave, quarter—wave, half—wave, three—quarter wave,
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`etc. In these embodiments (e.g., full-wave multiple, half-
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`wave, quarter-wave, etc.), tl1e phase and anti -phase relation-
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`ship between the plasma potentials substantially cancel each
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`other. In further cmbodimcnts, the wave adjustmcnt circuits
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`employ circuit elements that provide plasma applicators
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`with phase and anti-phase potential relationships that do not
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`cancel each other out using a variety of wave length por-
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`tions.
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`FIG. 2A is a simplified illustration ofa plasma source 50
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`using wavc adjustmcnt circuits and an agile tcmpcraturc
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`chuck 75 according to an embodiment of the present inven-
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`tion. This plasma source 50 includes a discharge tube 52, an
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`inductive applicator 55, an exterior shield 54, an upper wave
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`adjustment circuit 57, a lower wave adjustment circuit 59, an
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`rf power supply 61, and other elements. The upper wave
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`adjustment circuit 57 is a helical coil transmission line ,
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`portion 69, outside of the plasma source region 60. Lower
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`wave adjustment circuit 59 also is a helical coil transmission
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`line portion 67 outside of the plasma source region 60. The
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`power supply 61 is attached 65 to this lower helical coil
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`portion 67, and is grounded 63. Each of the wave adjustment
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`circuits also are shielded 66, 68.
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`In this embodiment.
`the wave adjustment circuits are
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`adjusted to provide substantially zero AC voltage at one
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`point on the inductive coil (refer to point 00 in FIG. 2A).
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`This embodiment also provides substantially equal phase 70
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`and anti-phase 71 voltage distributions in directions about
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`this point (refer to 00-A and 00-C ir1 FIG. 2A) and provides
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`substantially equal capacitance coupling to the plasma from
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`physical inductor clcmcnts (00-C) and (00-A), carrying the
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`phase and anti-phase potentials. Voltage distributions 00—A
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`and 00-C are combined with C-D and A-B (shown by the
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`phantom lines) to substantially comprise a full-wave voltage
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`6
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`distribution in this embodiment where the desired configu-
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`ration is a selected phase/anti-phase portion of a full-wave
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`inductor (or helical
`resonator) surrounding the plasma
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`source discharge tube.
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`In this embodiment. it is desirable to reduce or minimize
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`capacitive coupling current from the inductive element to
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`the plasma discharge in the plasma source. Since the capaci-
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`tive current increases monotonically with the magnitude of
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`thc dilfcrcncc of pcak phasc and anti-phasc voltagcs, which
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`occur at points A and C in FIG. 2A, this coupling can be
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`lessened by reducing this voltage dilference. In FIG. 2A, for
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`example,
`it
`is achieved by way of two wave adjustment
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`circuits 57, 59. Coil 55 (or discharge source) is a helical
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`resonator and the wave adjustment circuits 57, 59 are helical
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`resonators.
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`The discharge source helical resonator 53 can be con-
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`structed using conventional design formulae. Generally. this
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`helical resonator includes an electrical
`length which is a
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`selected phase portion “X” (A to 00 to C) of a full-wave
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`~ helical resonator. The helical resonator wave adjustment
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`circuits are each selected to jointly comprise a portion (2J1:—x)
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`of full-wave helical resonators. Physical parameters for the
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`wave adjustment helical resonators can be selected to realize
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`practical physical dimensions and appropriate Q, 7.0, etc
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`values. In particular, some or even all of the transmission
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`line parameters (Q, Z0, etc.) of the wave adjustment circuit
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`sections may be selected to be substantially tl1e sa111e as the
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`transmission line parameters of the inductive applicator. The
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`portion of the inductive plasma applicator hclical rcsonator,
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`on the other hand, is designed and sized to provide selected
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`uniformity values over substrate dimensions within an eco-
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`nomical equipment size and reduced Q.
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`The wave adjustment circuit provides for external rf
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`power coupling, which can be used to control and match
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`power to the plasma sourcc, as comparcd to conventional
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`teclmiques used in helical resonators and the like.
`In
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`particular, conventional techniques often match to, couple
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`power to, or match to tl1e impedance of tlie power supply to
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`the helical resonator by varying a tap position along the coil
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`above the grounded position, or selecting a fixed tap position
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`relative to a grounded coil end and matching to the i1nped—
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`ance at this position using a conventional r11atchir1g network,
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`e.g., LC network, :1 network, etc. Varying this tap position
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`along the coil within a plasma source is oftcn cumbersome
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`and generally imposes difficult mechanical design problems.
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`Using the fixed tap and external matching network also is
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`cumbersome and can cause unanticipated changes in the
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`discharge Q, and therefore influences its operating mode and
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`stability. In the present embodiments, the wave adjustment
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`circuits can be positioned outside of the plasma source (or
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`constrained ir1 space containing the inductive coil, e.g., See
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`FIG. 2A. Accordingly, the mechanical design (e.g., means
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`for varying tap position, change in the effective rf power
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`coupling point by electrical means, etc.) of the tap position
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`are simplified relative to those conventional techniques.
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`In the present embodiment, rf power is fed into the lower
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`wave adjustment circuit 59. Alternatively, rf power can be
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`fed into tl1e upper wave adjustment circuit (not shown). The
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`rf power also can be coupled directly into the inductive
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`plasma coupling applicator (e.g., coil, etc.) in the wave
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`adjustment circuit design, as illustrated by FIG. 2B.
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`Alternatively, other applications will use a single wave
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`adjustment circuit, as illustrated by FIG. 2C. Power can be
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`couplcd into this wave adjustmcnt circuit or by conventional
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`techniques such as a tap in the coil phase.
`In some
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`embodiments, this tap in the coil phase is positioned above
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`tl1e grounded end. An external impedance matching network
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`Page 19 of 29
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`US RE40,264 E
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`7
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`may then be operably coupled to the power for satisfactory
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`power transfer eifrciency from, for example, a conventional
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`coaxial cable to impedances (current to voltage rations)
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`existing between the wave adjustment circuit terminated end
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`of the applicator and the grounded end.
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`A further embodiment using multiple inductive plasma
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`applicators also is provided, as shown in FIG. 2D. This
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`embodiment includes multiple plasma applicators (PA 1,
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`. PAn). These plasma applicators respectively provide
`PA2. .
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`selected combinations of inductively coupled power and
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`capacitively coupled power from respective voltage poten-
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`tials (V1, V2.
`. Vn). Each of these plasma applicators
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`. PSn)
`derives power from its power source (PS1, PS2.
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`either directly through an appropriate matching or coupling
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`network or by coupling to a wave adjustment circuit as
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`described. Alternatively, a single power supply using power
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`splitters and impedance matching networks can be coupled
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`to each (or more than two) of the plasma applicators.
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