Network Timing Reference for Frequency
`Synchronization in xDSL based Access
`Networks
`
`Dr. Rudi Frenzel
`
`Dublin, Nov. 4, 2010
`
`Dish
`Exhibit 1039, Page 1
`
`
`Synchronization in xDSL based Access
`Networks
`
`Dr. Rudi Frenzel
`
`Dublin, Nov. 4, 2010
`
`Dish
`Exhibit 1039, Page 1
`
`
`
`Frequency & Time Distribution in xDSL End-to-End Networks
`
`ILEC National Telephony Network
`
`S P
`
`DSL
`
`MDU
`
`FTTB/FTTC
`
`PON
`
`Central Office
`
`Access
`Switch, OLT
`
`PSTN Network
`
`SS7
`PRI
`
`V5.2
`
`GR-303
`
`SS7
`PRI
`
`FTTB
`
`ISDN, POTS
`
`fixed wireless
`
`WLL
`
`WLL
`
`DSL
`
`Splitter
`
`DSLAM
`
`Street
`Cabinet
`
`PON,
`SONET
`
`ISP,
`National
`Service
`Provider
`
`TGW
`
`RAS
`
`Voice Switch
`
`Voice Switch
`
`V5.2
`
`GR-303
`
`Voice
`Concentrator
`„Voice Switch“
`
`MDF/Splitter
`
`ATM or IP
`DSLAM
`
`NGN/
`IP-DSLAM
`
`Access
`Switch, OLT
`
`Operator
`Access-
`Network
`
`Operator Core-Network
`IP/MPLS
`
`Gateway
`
`IP
`
`IP
`
`Router
`
`IP
`
`1st/2nd Level
`Aggregation
`
`IP
`
`IP-VPN
`Concentrator
`
`BAS
`Broadband
`Access Server
`
`…
`
`Web
`Cache
`
`Video
`Server
`
`Service Aggregation
`
`Grand
`Master
`
`"Public Internet"
`
`2010/11/04
`
`POTS
`
`Femto
`
`PTP Slave
`
`CPE
`
`Ethernet, WLAN
`
`Ethernet, WLAN
`
`POTS
`
`Ethernet, WLAN
`
`Ethernet, WLAN
`
`IAD
`
`SFU/
`HGU
`
`IAD
`
`CPE
`
`Ethernet, WLAN
`
`Ethernet, WLAN
`
`IAD
`
`POTS
`
`CPE
`
`Ethernet, WLAN
`
`S P
`
`S P
`
`NGN/
`DSLAM
`
`DSL
`
`Ethernet, WLAN
`
`IAD
`
`POTS
`
`PTP Slave
`
`BS
`
`Mobile Base-Station,
`Backhaul: DSL
`
`Customer
`Premise
`
`Local Loop
`
`Logical Interface;
`realized e.g. as
`SONET/SDH,
`10G Ethernet
`
`Fiber in Access
`Network
`
`Copper in Access
`Network
`
`In-House Copper
`
`Dish
`Exhibit 1039, Page 2
`
`
`
`History and Future of Clock Synchronization over DSL
`
`As of today…
`Γ ADSL, VDSL for data services, residential customers
` no requirements for frequency & time synchronization
`Γ SHDSL mostly for business (symmetrical) data-services
` Rather limited use for frequency synchronization
`Γ Backhaul of Base-Stations over copper addressed with T1/E1
` high precision frequency & clock distribution through TDM framing
`with native baud-rate (2.048MHz, 1.536MHz)
`
`Future:
`Γ Mobile evolution demands frequency synchronization till the
`edge of the access network
` Pico/Femto-Cell architectures for mobile networks, operated in
`customer's premise
` Bandwidth demand, exceeding T1/E1 capacity
` Backhaul of 3G/4G Base-Stations partially through (bonded-) DSL
`
`2010/11/04
`
`3
`
`Dish
`Exhibit 1039, Page 3
`
`
`
`xDSL Technology Overview
`
`SHDSL
`
`ADSL2+
`
`VDSL2
`
`Γ DS data rate
`
`Γ US data rate
`
`Γ Typ. loop length
`
`5.7 Mbps
`
`5.7 Mbps
`
`24 kft
`
`Γ Layer 2 Transp.
`
`PTM, ATM,TDM
`
`Γ Typ. Deployment
`
`Ex
`
`Γ Max. Signal BW
`
`Γ Modulation
`
`Γ Transmit Power
`
`Γ Frequency Sync
`
`1.4 MHz
`
`PAM 16/32
`
`14.5 dBm
`
`NTR sync
`
`2010/11/04
`
`28Mbps
`
`1~3 Mbps
`
`12…20 kft
`
`ATM, PTM
`
`Ex, Cab
`
`2.2 MHz
`
`100 Mbps
`
`100 Mbps
`
`6...10 kft
`
`PTM, (ATM)
`
`Ex, Cab, Bld.
`
`30 MHz
`
`DMT
`512 /32 carriers
`
`DMT
`4096/4096 carriers
`
`20.5 dBm
`
`14.5, 20.5 dBm
`
`NTR
`inband,sync
`
`NTR
`inband, sync
`
`Dish
`Exhibit 1039, Page 4
`
`
`
`Time and Clock Syncronisation for DSL – Overview
`
`Legacy DSL NTR
`
`Reference
`
`G.991.2 (SHDSL)
`
`G.992.1 (ADSL)
`
`G.992.3, G.992.5 (ADSL2, ADSL2+)
`G.993.2 (VDSL2)
`
`Future (Proposed)
`Time-of-Day Transmission
`Convergence Layer for DSL
`
`ITU-T Contribution
`10MB-054R1 (and others) for VDSL2
`
`Maturity
`
`available/mature
`
`basic idea; principle based on IEEE1588
`
`Frequency Sync
`
`Phase Sync
`
`Abs. Time Sync
`
`Yes
`
`---
`
`---
`
`Yes
`
`Yes
`
`Yes
`
`Working
`Principle
`
`NTR ib-bits (indicator bits),
`exchanged every superframe
`(≤20ms)
`
`1588 PTP-style exchange of 4 timestamps;
`time events coupled to DSL-loop timing
`
`2010/11/04
`
`Dish
`Exhibit 1039, Page 5
`
`
`
`Clock & Time in a DSL DSLAM - LTR and NTR
`Generic View of Today's Systems (Simplified)
`
`DSL Linecard
`
`Central Card
`
`LTR (typ.: 35.328MHz)
`
`DSL
`PHY
`
`DSL
`PHY
`
`DSL
`PHY
`
`DSL
`PHY
`
`Local
`XO
`
`NTR
`
`1G Eth.
`PON
`SONET
`
`Backhaul
`PHY
`
`Clock
`Management
`(PLL/TCXO)
`
`8KHz NTR Distribution across Backplane
`
`2010/11/04
`
`Dish
`Exhibit 1039, Page 6
`
`
`
`Clock & Time in a DSLAM - Advanced Architectures
`Generic View (Simplified)
`
`DSL Linecard
`
`LTR (typ.: 35.328MHz)
`
`DSL
`PHY
`
`DSL
`PHY
`
`DSL
`PHY
`
`DSL
`PHY
`
`Local
`VCXO
`
`NTR/PPS
`
`Central Card
`
`Backhaul
`PHY
`
`PTP
`
`Time
`Events
`
`CPU
`
`Clock
`Management
`(PLL/TCXO)
`
`Clock and Time Event Distribution across Backplane
`
`Managemet Interface with Time Messages
`
`2010/11/04
`
`PMD or
`IEEE1588v2
`derived
`Clock/Time
`
`Dish
`Exhibit 1039, Page 7
`
`
`
`Working Principle of NTR:
`Frequency Synchronization across xDSL Links
`
`Γ The well known xDSL technologies ADSL, VDSL and SHDSL include
`Transmission Convergence Layers which decouple data streams
`timing from transmission timing due to its focus on ATM or PTM
`framed data
`Γ In order to support frequency synchronization across the xDSL link
`the xDSL standards define methods to transport a Network Timing
`Reference (NTR) across the DSL link
`
`I00 10
`
`TC-
`Layer
`
`xDSL
`
`PMD
`
`xDSL
`
`PMD
`
`I00 10
`
`TC-
`Layer
`
`Decoupling
`
`of data clock
`
`from link clock
`
`synchronous transmission
`
`across the wireline channel
`
`Decoupling
`
`Of data clock
`
`from link clock
`
`2010/11/04
`
`8
`
`Dish
`Exhibit 1039, Page 8
`
`
`
`Network Timing Reference for Frequency Synchronization –
`SHDSL
`
`Data I/F
`
`SHDSL
`
`SHDSL
`
`Data I/F
`
`Transceiver CO
`
`STU-C
`
`Transceiver RT
`
`STU-R
`
`Tx symbol clk
`
`Tx symbol clk
`
`CLK Gen
`
`CLK Rec
`
`NTR In
`
`NTR out
`
`Γ SHDSL supports Network Timing Reference from STU-C to STU-R
`Γ In NTR mode frame and symbol clock are locked to the NTR time
`marker (8kHz or a multiple thereof, e.g. 1544 kHz or 2048 kHz,)
`Γ At the STU-R the NTR is extracted from the recovered Frame or
`symbol and provided to the data layer
`
`2010/11/04
`
`9
`
`Dish
`Exhibit 1039, Page 9
`
`
`
`Network Timing Reference for Frequency Synchronization –
`ADSL, VDSL2 – NTR – In-band Transport
`
`Γ NTR – In-band Transport
` NTR and xDSL clock need not be synchronous
` NTR information is transported by differential phase offset values between
`the NTR and the Local Timing Reference (LTR)
` The LTR is derived by dividing the ADSL / VDSL2 sampling clock by the xDSL
`flavor specific factor
` The phase offset is expressed in cycles of the sampling clock at Nyquist rate
`as a 2-complement number
`
`Γ Generic Architecture
`
`NTR (8kHz)
`
`register
`
`register
`
`Δ2φn
`
`Δ2φ
`
`Clock
`fsample
`
`count
`mod C0
`
`MC
`
`count
`mod C0
`
`MC
`
`register
`
`Δ2φn-1
`
`2010/11/04
`
`10
`
`Dish
`Exhibit 1039, Page 10
`
`
`
`Network Timing Reference for Frequency Synchronization –
`ADSL, VDSL2 - NTR – In-band Transport
`
`Γ Properties
` NTR information is transmitted with every Overhead Channel Period
`of the actual DSL link, i.e.
`(cid:173) 15-20ms in ADSL2+
`(cid:173) < 20ms for VDSL2
` NTR updates are protected by CRC check sum
` Intermittent outages do not result in accumulating errors
` At CPE side NTR is recovered based on recovered loop timing and
`received NTR information
`
`xDSL Receiver
`
`Loop
`Timing
`
`NTR
`Rec
`
`xDSL Transmitter
`
`Recovered NTR (8kHz)
`
`2010/11/04
`
`11
`
`Dish
`Exhibit 1039, Page 11
`
`
`
`Network Timing Reference for Frequency Synchronization
`Measurements
`
`Γ MTIE / TDEV Measurement:
` NTR across a VDSL2 link
`
`2010/11/04
`
`12
`
`Dish
`Exhibit 1039, Page 12
`
`
`
`Network Timing Reference for Frequency Synchronization –
`ADSL, VDSL2 - NTR synchronous to loop timing ?
`
`Is it possible to have the VDSL2 loop timing synchronized to the NTR clock ?
`
`YES – but there are Challenges
`
`Pilot Tone
`
`θe
`
`Phase
`Error
`
`Loop Filter
`
`DCXO /NCO
`
`DMT symbol timing
`
`discrete ntr
`Bytes always 0
`(unused)
`
`DSL Copper Loop
`
`LTR
`35.328MHz
`+/- 50ppm
`
`CPE
`Modem
`
`modem timing recovery
`
`NTR Pin
`8KHz
`
`NTR
`8KHz +/- 32ppm
`
`PLL
`
`LTR
`35.328MHz +/- 50ppm
`
`NTR Pin unused
`
`CO Modem
`
`2010/11/04
`
`13
`
`Dish
`Exhibit 1039, Page 13
`
`
`
`Network Timing Reference for Frequency Synchronization –
`ADSL, VDSL2 - NTR synchronous to loop timing ?
`
`Γ Implication of synchronous NTR transport with ADSL, VDSL2
` ADSL and VDSL2 utilize complex (dense) QAM constellations compared
`to legacy communication schemes
`very low tolerance on clock jitter and wander for error free
`communication
`
` Clock requirements for xDSL systems are not specified in MTIE or
`TDEV tolerance schemes but in ppm frequency offset – not covering
`any jitter, wander or frequency drift limits
` Potential interoperability issues with installed base as there is no
`specification on clock tolerances for xDSL implementations
` DSLAMs require sophisticated clock regeneration techniques, if DSL LTR is
`to be synchronized with an NTR source
` Holdover and fallback modes without phase jump needed to avoid link
`drops
`
`2010/11/04
`
`14
`
`Dish
`Exhibit 1039, Page 14
`
`
`
`Phase Jitter Impact on dense xDSL Constellation QAM
`Constellations per Carrier as per ADSL / VDSL2
`
`ΓSquare constellations for
`Γb=2,4,6,8,10,12,14 bits per symbol
`4, …, 16384 constellation points.
`
`ΓCross constellations for
`Γb=3,5,7,9,11,13,15 bits per symbol
`8 … 32768 constellation points.
`
`Example: b=6, K=64 points
`2010/11/04
`
`Example: b=7, K=128 points
`
`04.11.
`2010
`
`Y
`
`X
`
`Y
`
`X
`
`Dish
`Exhibit 1039, Page 15
`
`
`
`Phase Jitter Impact on dense xDSL Constellation
`15 Bit VDSL2 Constellation – 32768 points
`
`Γ Measurement of a 15 bit constellation at the VDSL2 receiver
`
`φ
`
`Γ Phase errors start causing false detections
`for values as little as φ=0.3°
`Γ Phase errors affect all carriers of a DMT
`symbol at the same time
`
`2010/11/04
`
`16
`
`Dish
`Exhibit 1039, Page 16
`
`
`
`Phase Jitter Impact on dense xDSL Constellation
`Symbol Error Rate, Error Free Phase Offset Range
`
`Γ Phase jitter RMS σφ for Error Probability Perr=10-10
`(cid:173) 14 Bits: σφ = 1.303*10-3 rad, i.e., σφ = 7.463*10-2 deg
`(cid:173) 15 Bits: σφ = 8.541*10-4 rad, i.e., σφ = 4.894*10-2 deg
`
`2010/11/04
`
`04.11.
`2010
`
`Dish
`Exhibit 1039, Page 17
`
`
`
`NTR synchronous to loop timing - Conclusion
`
`PRO
`
` Continuous frequency synchronization, free of drift
` Very low phase error due to robustness of DSL loop timing
`
`Challenges
` needs synchronized CO clock-source (35.328MHz, industry standard
`clock for DSL)
` DSL performance may become dependent on jitter and wander of
`the network clock
` low-wander CO clocks required, eg. by narrow band PLLs
`frequency drift (wander) limit of 0.08ppm/s found to be marginal
`
`2010/11/04
`
`18
`
`Dish
`Exhibit 1039, Page 18
`
`
`
`Why Not Run IEEE1588 across DSL ?
`Limitations in QoS
`
`Γ Applying the IEEE1588 concept of Boundary Clocks to
`DSL is of limited accuracy:
` Unlike Ethernet, there is no clearly defined "Start-Of-
`Packet", "End-Of-Packet" for a PTP protocol frame
`traversing a DSL link
` 1588 PTP payload can be treated with priority, but… the
`DSL PHY is carrying payload in a bursty fashion of
`unpredictable nature (see box)
`
`Γ Asymmetrical delays up- and downstream limit the
`overall PTP accuracy
`
`Γ Discussion & papers at ITU-T SG15/Q4:
` no phase sync over DSL using plain 1588 methods possible
` Started definition of a “xDSL enabled PTP”
`
`Some contributors to
`DSLs "Burstiness"
` DMT symbol
`processing (4/8KHz)
` Reed-Solomon
`Codeword Length
`(variable)
` Retransmission at
`Physical Layer
`(G.998.4)
` Periodic Sync Symbol
` Flow-Control
`towards Network-
`Processor
` Online
`Reconfiguration
`(Rate Changes)
`
`2010/11/04
`
`19
`
`Dish
`Exhibit 1039, Page 19
`
`
`
`What is next – IEEE1588 like PTP for VDSL2
`
`Γ ITU-T proposal for IEEE1588 like PTP for VDSL2
`
` At VTU-O, time stamps are taken at a dedicated time domain reference sample of particular
`downstream DMT symbols at the U-O interface
` At VTU-R, time stamps are taken at the reception of the same time domain reference sample
`of particular DMT symbols at the U-R interface
` Time stamp information is transmitted from VTU-O to VTU-R in the EOC (embedded operation
`channel) of the VDSL link
`
`
`
`Same mechanisms to be used in upstream direction, i.e. from VTU-R to VTU-O
`
` By linking the time stamp collection to the VDSL2 loop timing, it is possible to achieve
`almost jitter free time stamp pairs on VTU-O and VTU-R similar to the “start of packet”
`concept of IEEE1588 for Ethernet systems
`
`2010/11/04
`
`20
`
`Central Office (VTU-O) Location
`
`Remote (VTU-R) Location
`
`ToD_mc_value
`
`fmc
`
`ToD_mc_edge
`
`ToD-TC
`
`VDSL2
`PHY
`
`Master
`Clock
`
`fmc
`
`t1
`
`t4
`
`U-O
`
`Subscriber Line
`
`t2
`
`t3
`
`U-R
`
`ToD_sc_value
`
`VDSL2
`PHY
`
`ToD-TC
`
`ToD_sc_edge
`
`fsc
`
`fsc
`
`Slave
`Clock
`
`g-O
`
`fs
`
`Sample
`Clock
`
`a
`
`Recovered
`Sample
`Clock
`
`fs
`
`b
`
`(Loop
`Timing)
`
`g-R
`
`Dish
`Exhibit 1039, Page 20
`
`
`
`Time Stamp Trigger based on xDSL time domain samples
`
`Block Processing (eg. 25000 bit/block @ 100Mbps)
`
`Cyclic Suffix
`
`I00 10
`
`Data In
`
`Per
`subcarrier
`QAM
`
`IFFT
`
`Time Domain
`DMT Symbol
`
`DMT Symbol
`(~250µs – 8832 samples)
`
`Cyclic Prefix
`
`time stamp trigger event
`
`2010/11/04
`
`Signal samples to the channel
`(35.328 MHz sample rate)
`
`21
`
`Dish
`Exhibit 1039, Page 21
`
`
`
`Summary
`
`Γ ADSL and VDSL support frequency synchronization across the physical
`layer already since early versions of the standards
`
`Γ The NTR concept allows to recover clocks at the remote side of DSL
`links within well known MTIE / TDEV masks as defined in ITU-T G.823
`
`Γ Synchronous NTR transport may be utilized in ADSL and VDSL2 systems.
`Since ADSL and VDSL2 use high modulation complexities, the accuracy
`requirements for the DSL clock generation from of the network clock
`scheme need careful attention
`
`Γ At ITU-T – the main standardization body for xDSL transceiver
`technology– new standards are in definition to allow PTP based ToD
`transport across xDSL links
`
`2010/11/04
`
`22
`
`Dish
`Exhibit 1039, Page 22
`
`
`
`2010/11/04
`
`23
`
`Dish
`
`Exhibit 1039, Pae 23
`
`Dish
`Exhibit 1039, Page 23
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