`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`
`
`Cisco Systems, Inc.,
`Petitioner
`
`vs.
`
`TQ Delta, LLC
`Patent Owner
`
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 8,611,404
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`TABLE OF CONTENTS
`
`PETITIONER’S EXHIBIT LIST ......................................................................... iv
`
`I.  Mandatory Notices ............................................................................................. 1 
`
`A.  Real Party-in-Interest ................................................................................. 1 
`
`B.  Related Matters .......................................................................................... 1 
`
`C.  Lead and Back-up Counsel and Service Information ............................... 2 
`
`II.  Grounds for Standing ......................................................................................... 2 
`
`III.  Requested Relief ................................................................................................ 2 
`
`IV.  Reasons for the Requested Relief ...................................................................... 2 
`
`A.  Summary of the ’404 Patent ...................................................................... 3 
`
`B.  Prosecution History ................................................................................... 7 
`
`C.  Summary of the Petition ............................................................................ 8 
`
`D.  Challenged Claims ..................................................................................... 9 
`
`V.  Claim Construction ............................................................................................ 9 
`
`A. 
`
`B. 
`
`“store/storing, in a/the low power mode” (claims 6, 11, 16) .................... 9 
`
`“synchronization signal” (claims 6, 11, 16) ............................................ 11 
`
`VI.  Statutory Grounds for Challenges ................................................................... 12 
`
`VII.  Level of Ordinary Skill in the Art ................................................................... 13 
`
`VIII. Note Regarding Page Citations ........................................................................ 13 
`
`IX.  Identification of How the Claims are Unpatentable ........................................ 13 
`
`A.  Summary of Bowie .................................................................................. 14 
`
`ii
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`B.  Summary of Yamano ............................................................................... 16 
`
`C.  Modem States in Bowie and Yamano ..................................................... 19 
`
`D.  Summary of ANSI T1.413 ...................................................................... 23 
`
`E.  Reasons to Combine Bowie and Yamano ............................................... 25 
`
`F.  Reasons to Combine Bowie/Yamano with ANSI T1.413 ....................... 27 
`
`G.  Claims 6, 10, 11, 15, 16, and 20 are obvious under 35 U.S.C.
`§ 103(a) over Bowie in view of Yamano and ANSI T1.413 .................. 29 
`
`1.  Claim 6 ............................................................................................ 29 
`
`2.  Claim 10 .......................................................................................... 44 
`
`3.  Claim 11 .......................................................................................... 46 
`
`4.  Claim 15 .......................................................................................... 59 
`
`5.  Claim 16 .......................................................................................... 59 
`
`6.  Claim 20 .......................................................................................... 60 
`
`X.  Conclusion ....................................................................................................... 62 
`
`XI.  Certificate of Word Count ............................................................................... 63 
`
`
`
`
`
`iii
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`PETITIONER’S EXHIBIT LIST
`
`July 20, 2016
`
`1001 U.S. Patent No. 8,611,404 to Greszczuk et al.
`
`1002 Prosecution File History of U.S. Patent No. 8,611,404
`
`1003 Declaration of Sayfe Kiaei under 37 C.F.R. § 1.68
`
`1004 Curriculum Vitae of Dr. Sayfe Kiaei
`
`1005 U.S. Patent No. 5,956,323 to Bowie
`
`1006 U.S. Patent No. 6,075,814 to Yamano et al.
`
`1007 ANSI T1.413-1995
`
`1008 Declaration of David Bader
`
`1009 U.S. Patent No. 6,084,881 to Fosmark et al.
`
`
`iv
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`I. MANDATORY NOTICES
`
`A. Real Party-in-Interest
`
`The Petitioner and real party in interest is Cisco Systems, Inc.
`
`B. Related Matters
`
`To the best knowledge of the Petitioner, U.S. Patent No. 8,611,404 (“the
`
`’404 Patent”) is involved in the following litigations:
`
`Name
`
`Number
`
`Court Filed
`
`TQ Delta LLC v. ADTRAN Inc.
`
`1-14-cv-00954
`
`DED
`
`Jul. 17, 2014
`
`TQ Delta LLC v. Comcast Cable
`Comms. LLC
`
`1-15-cv-00611
`
`DED
`
`Jul. 17, 2015
`
`TQ Delta LLC v. CoxCom, LLC
`
`1-15-cv-00612
`
`DED
`
`Jul. 17, 2015
`
`TQ Delta LLC v. DIRECTV
`
`1-15-cv-00613
`
`DED
`
`Jul. 17, 2015
`
`TQ Delta LLC v. DISH Network Corp. 1-15-cv-00614
`
`DED
`
`Jul. 17, 2015
`
`TQ Delta LLC v Time Warner Cable
`Inc.
`
`1-15-cv-00615
`
`DED
`
`Jul. 17, 2015
`
`TQ Delta LLC v. Verizon Comms., Inc. 1-15-cv-00616
`
`The ’404 Patent is also involved in the following related matter:
`
`DED
`
`Jul. 17, 2015
`
`Name
`
`Petition for Inter Partes Review of the
`’404 Patent by ARRIS Group, Inc.
`
`
`Number
`
`Court Filed
`
`IPR2016-01160 PTAB
`
`Jun. 6, 2016
`
`1
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`C. Lead and Back-up Counsel and Service Information
`
`Lead Counsel
`David L. McCombs
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`Back-up Counsel
`Theodore M. Foster
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`Michael S. Parsons
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`
`214-651-5533
`Phone:
`214-200-0853
`Fax:
`
`david.mccombs.ipr@haynesboone.com
`USPTO Reg. No. 32,271
`
`
`972-739-8649
`Phone:
`972-692-9156
`Fax:
`
`ipr.theo.foster@haynesboone.com
`USPTO Reg. No. 57,456
`
`972-739-8611
`Phone:
`972-692-9003
`Fax:
`
`michael.parsons.ipr@haynesboone.com
`USPTO Reg. No. 58,767
`
`II. GROUNDS FOR STANDING
`
`Petitioner certifies that the ’404 Patent is available for inter partes review
`
`and that Petitioner is not barred or estopped from requesting inter partes review
`
`challenging the patent claims on the grounds identified in this Petition.
`
`III. REQUESTED RELIEF
`
`Petitioner asks that the Board review the accompanying prior art and
`
`analysis, institute a trial for inter partes review of claims 6, 10, 11, 15, 16, and 20
`
`of the ’404 Patent, and cancel these claims as unpatentable.
`
`IV. REASONS FOR THE REQUESTED RELIEF
`
`As explained below and in the declaration of Cisco Systems’ expert, Dr.
`
`2
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`Sayfe Kiaei, the concepts described and claimed in the ’404 Patent were not novel.
`
`This Petition and Dr. Kiaei’s declaration explain where each element is found in
`
`the prior art and why the claims would have been obvious to a person of ordinary
`
`skill in the art prior to the earliest effective priority date.
`
`A.
`
`Summary of the ’404 Patent
`
`The ’404 patent relates to a multicarrier transceiver “with a sleep mode in
`
`which it idles with reduced power consumption.” Ex. 1001, Abstract. The ’404
`
`patent states that “[t]he full transmission and reception capabilities of the
`
`transceiver are quickly restored when needed, without requiring the full (and time-
`
`consuming) initialization commonly needed to restore such transceivers to
`
`operation after inactivity.” Ex. 1001, Abstract. This transceiver, according to the
`
`’404 patent, may be included in the “DSL” systems, such as “xDSL”, “ADSL,”
`
`and “HDSL.” Ex. 1001 at 1:42-47.
`
`According to the ’404 patent, data communication in DSL systems occur
`
`using a “first transceiver located at the site of a customer’s premises” and a
`
`“second transceiver located at the central telephone office.” Ex. 1001 at 3:63-66.
`
`The ’404 patent refers to the “first transceiver” as the “CPE transceiver,” and the
`
`“second transceiver” as the “CO transceiver.” Ex. 1001 at 3:65-67. During normal
`
`operation, the CPE transceiver and the CO transceiver exchange data using
`
`“superframes.” Ex. 1001 at 5:11-12. Each “superframe” includes “a sequence of
`
`3
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`data frames” followed “by a synchronization frame.” Ex. 1001 at 5:6-9. Also
`
`during normal operation “[t]he timing reference signal 62a is transmitted to the
`
`[CPE] transmitter from the transmitter with which the receiver 16 communicated
`
`(e.g., the CO transmitter)” which “is synchronized with the Master Clock in the
`
`transmitter” and whose “frequency defines the frame rate of the transceivers.” Ex.
`
`1001 at 5:39-45.
`
`In the ’404 patent, the CO and CPE transceiver can enter a low power
`
`consumption mode. Ex. 1001 at 6:27-30. While the description of the ’404 patent’s
`
`low power mode is described below in terms of the CPE transceiver, the ’404
`
`patent states that the process is the same for the CO transceiver. Ex. 1001 at 4:11-
`
`13.
`
`To enter the low power mode, the CPE transceiver first transmits an “Intend
`
`To Enter Sleep Mode” notification to the CO transceiver. Ex. 1001 at 6:41, 62-63.
`
`If sleep mode is permissible, the CO transceiver responds to the notification “by
`
`transmitting an ‘Acknowledge Sleep Mode’ notification.” Ex. 1001 at 6:52-54. The
`
`CPE then transmits an “Entering Sleep Mode” notification to the CO, which is
`
`reciprocated by the CO. Ex. 1001 at 6:61-67. Upon receiving the “Entering Sleep
`
`Mode” notification from the CO, the CPE then enters the sleep mode state. Ex.
`
`1001 at 7:33-35. In the sleep mode state, the CPE “stores its state” in connection
`
`with CO transceiver, including “the transmission fine gains” and “the Bit
`
`4
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`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
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`Allocation Tables” parameters in the “state memory.” Ex. 1001 at 7:33-42. The
`
`CPE then “reduces power to the digital modulator/demodulator circuitry
`
`comprising IFFT 20 and FFT 56, as well as to and transmitter data line drivers 26”
`
`but “continues to advance the frame counter 34 in accordance with the received
`
`synchronizing signal 62a.” Ex. 1001 at 7:44-49.
`
`Likewise, upon receiving the “Entering Sleep Mode” notification, the CO
`
`transceiver enters sleep mode. Ex. 1001 at 6:65-67. The CO transceiver then
`
`“stores its state in its own state memory corresponding to the state memory 36 of
`
`CPE transceiver 10.” Ex. 1001 at 6:67-7:2. The CO transceiver also “continues to
`
`advance the frame count and superframe count during the period of power-down in
`
`order to ensure synchrony with the remote CPE transceiver when communications
`
`are resumed.” Ex. 1001 at 7:9-12.
`
`To exit the low power mode, the CPE “receives an ‘Awaken’ indication.”
`
`Ex. 1001 at 7:59-62. “In response to the ‘Awaken’ signal, the CPE transceiver
`
`retrieves its stored state from the state memory 38; restores full power to its
`
`circuitry.” Ex. 1001 at 7:64-66. The CPE also transmits an “Exiting Sleep Mode”
`
`to the CO transceiver, which upon “detecting the ‘Exit Sleep Mode’ notification
`
`from the CPE transceiver . . . exits sleep mode by restoring its state and restoring
`
`its power.” Ex. 1001 at 8:1-4.
`
`The purported invention of the ’440 patent is the CPE transceiver’s ability to
`
`5
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`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`“begin transmitting immediately or after only a few frames delay” because “it need
`
`not repeat the initialization . . . to establish the requisite parameters.” Ex. 1001 at
`
`8:4-7.
`
`Independent claims 6 and 11 are representative of the Challenged Claims:
`
`6. An apparatus comprising a transceiver operable to:
`receive, in a full power mode, a plurality of superframes, wherein
`the superframe comprises a plurality of data frames followed by
`a synchronization frame;
`receive, in the full power mode, a synchronization signal;
`transmit a message to enter into a low power mode;
`store, in a low power mode, at least one parameter associated with
`the full power mode operation wherein the at least one
`parameter comprises at least one of a fine gain parameter and a
`bit allocation parameter;
`receive, in the low power mode, a synchronization signal; and
`exit from the low power and restore the full power mode by using
`the at least one parameter and without needing to reinitialize the
`transceiver.
`
`Ex. 1001 at 10:29-43.
`
`11. A method of multicarrier communications comprising:
`transmitting, by a transceiver, in a full power mode, a plurality of
`superframes, wherein the superframe comprises a plurality of
`data frames followed by a synchronization frame;
`transmitting, in the full power mode, a synchronization signal;
`receiving a message to enter into a low power mode;
`
`6
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`low power mode by reducing a power
`the
`into
`entering
`consumption of at least one portion of a transmitter;
`storing, in the low power mode, at least one parameter associated
`with the full power mode operation wherein the at least one
`parameter comprises at least one of a fine gain parameter and a
`bit allocation parameter;
`transmitting, in the low power mode, a synchronization signal; and
`exiting from the low power and restoring the full power mode by
`using the at least one parameter and without needing to
`reinitialize the transceiver.
`
`Ex. 1001 at 10:54-11:5.
`
`B.
`
`Prosecution History
`
`The ’404 Patent was filed as Application No. 13/887,889 (the ’889
`
`application) on May 6, 2013. See Ex. 1001. The ’889 application claims its earliest
`
`priority to U.S. Provisional Application No. 60/072,447 filed on January 26, 1998.
`
`See Ex. 1001. On August 21, 2013, a preliminary amendment was filed canceling
`
`claims 1-17 and adding new claims 18-37. See Ex. 1002 at 77-80.
`
`On September 6, 2013, the Patent Office issued a first Office Action that
`
`rejected claims 18-37 under 35 U.S.C. § 112, first paragraph, for failing to comply
`
`with enablement requirement. Ex. 1002 at 58.The Examiner also indicated that the
`
`independent claims (18, 23, 28, and 33) would otherwise be allowable if amended
`
`to overcome the § 112 rejection. Ex 1002 at 58. The Applicants filed a Response
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`on September 12, 2013, making minor amendments to claims 18-19, 23-24, 28-29,
`
`and 33-24 to overcome the § 112 rejection. Ex. 1002 at 48-52.
`
`The Patent Office issued a Notice of Allowability on October 23, 2013,
`
`allowing claims 18-37. In the Allowance, the Examiner stated that:
`
`[N]one of the prior art discloses or suggests that An apparatus and a
`method, comprising a transceiver operable to: comprises a plurality of
`data frames followed by a synchronization frame; transmit, in the full
`power mode, a synchronization signal; receive a message to enter into
`a low power mode; enter into the low power mode by reducing a
`power consumption of at least one portion of a transmitter; store, in
`the low power mode, at least one parameter associated with the full
`power mode operation wherein the at least one parameter comprises at
`least one of a fine gain parameter and a bit allocation parameter;
`transmit, in the low power mode, a synchronization signal; and exit
`from the low power and re-enter into restore the full power mode by
`using the at least one parameter and without needing to reinitialize the
`transceiver
`
`Ex. 1002 at 38.
`
`Thus, it appears that the claims where allowed without the Examiner
`
`applying or even citing any prior art against the claims.
`
`C.
`
`Summary of the Petition
`
`DSL transceivers capable of entering a low-power mode were not new as of
`
`the ’404 Patent’s earliest effective filing date in 1998. Specifically, the prior art
`
`8
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`recognized that DSL transceivers could enter a sleep mode or low-power mode
`
`when not sending or receiving data. The prior art also recognizes that DSL
`
`transceivers could have separate transmit and receive circuits that could be
`
`individually powered so that individual components could be powered-down when
`
`not in use. Because the ’404 Patent claims the use of this prior-art technology, the
`
`claims are unpatentable and should be canceled.
`
`D. Challenged Claims
`
`Claims 6, 10, 11, 15, 16, and 20 of the ’404 Patent are challenged in this
`
`Petition.
`
`V. CLAIM CONSTRUCTION
`
`This Petition analyzes the claims consistent with the broadest reasonable
`
`interpretation in light of the specification. See 37 C.F.R. § 42.100(b). All claim
`
`terms not discussed below are to be given their broadest reasonable interpretation,
`
`as understood by one of ordinary skill in the art consistent with the disclosure.
`
`Cuozzo Speed Techs., LLC v. Lee, 579 U.S. ___, slip op. at 17 (2016).
`
`A.
`
`“store/storing, in a/the low power mode” (claims 6, 11, 16)
`
`The ’404 Patent specification does not use this term, but the specification
`
`does disclose a CO transceiver and a CPE transceiver that store their respective
`
`states in memory upon “Entering Sleep Mode” and retain these states in memory
`
`9
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`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`while in sleep mode. Ex. 1001 at 6:67-7:9; 7:35-42. Ex. 1003 at p. 18-19. Once the
`
`parameters are stored, the CO and CPE transceivers enter a low power mode by
`
`reducing power to their respective circuitry. Ex. 1001 at 7:15-20; 7:44-47; Ex.
`
`1003 at p. 19.
`
`With respect to the CO transceiver, the specification states that the CO
`
`transceiver “enters sleep mode (90)” and then “stores its state in its own state
`
`memory corresponding to the state memory 36 of CPE transceiver 10.” Ex. 1001 at
`
`6:65-7:2. The CO then “perform[s] its own power reduction.” Ex. 1001 at 7:15-16.
`
`Upon exiting sleep mode, the CO transceiver “restor[es] its state and restor[es]
`
`power.” Ex. 1001 at 8:1-4.
`
`With respect to the CPE transceiver, the specification states that “the CPE
`
`transceiver enters the sleep mode (step 92)” and then “stores its state (step 94) in
`
`state memory 38.” Ex. 1001 at 7:33-40. The CPE transceiver then “reduces power
`
`to the digital modulator/demodulator circuitry comprising IFFT 20 and FFT 56, as
`
`well as to and transmitter data line drivers 26.” Ex. 1001 at 7:44-47. Upon exiting
`
`sleep mode, the CPE transceiver can “retrieves its stored state from the state
`
`memory 38” and “restores full power to its circuitry.” Ex. 1001 at 7:65-66. Thus,
`
`while the CO and the CPE both store their respective states while entering sleep
`
`mode, they also retain these states during sleep mode such that they can be restored
`
`upon waking up. Ex. 1003 at p. 20.
`
`10
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`Accordingly, consistent with the specification’s description and for the
`
`purposes of this proceeding, a POSITA would have understood that the broadest
`
`reasonable interpretation of this term to include “maintaining in memory while in a
`
`reduced power consumption mode.” Ex. 1003 at p. 20.
`
`B.
`
`“synchronization signal” (claims 6, 11, 16)
`
`The ’404 Patent does not provide an express definition for the term
`
`“synchronization signal.” Ex. 1003 at p. 20. Rather, the ’404 Patent’s specification
`
`describes that during normal (non-sleep mode) operations, a “timing reference
`
`signal 62[] is transmitted from the transmitter with which the receiver 16
`
`communicates (e.g., the CO transmitter).” Ex. 1001 at 5:39-41. The signal may be
`
`“a pure tone of fixed frequency and phase which is synchronized with the Master
`
`Clock in the transmitter,” though “[o]ther forms of timing signal may, of course, be
`
`used.” Ex. 1001 at 41-45. In one example, the ’404 patent describes a
`
`“synchronizing pilot tone 62 a” which is used “to maintain synchronization during
`
`the power down or idle state” between a CO transceiver and CPE transceiver. Ex.
`
`1001 at 7:13-15.
`
`Fig. 1B, reproduced below illustrates an example “timing signal used in
`
`accordance with the invention.” Ex. 1001 at 3:52-53.
`
`11
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`
`Ex. 1001, Fig. 1B.
`
`Accordingly, consistent with the specification’s description and for the
`
`purposes of this proceeding, a POSITA would have understood the broadest
`
`reasonable interpretation of “synchronization signal” to include “a signal used to
`
`maintain timing between transceivers.” Ex. 1003at p. 21.
`
`VI. STATUTORY GROUNDS FOR CHALLENGES
`
`Challenge #1: Claims 6, 10, 11, 15, 16, and 20 are obvious under 35 U.S.C.
`
`§ 103(a) over U.S. Patent No. 5,956,323 to Bowie (“Bowie”) (Ex. 1005) in view of
`
`U.S. Patent No. 6,075,814 to Yamano et al. (“Yamano”) (Ex. 1006), further in
`
`view of American National Standards Institute (ANSI) T1.413-1995 Standard,
`
`entitled “Network and Customer Installation Interfaces—Asymmetric Digital
`
`Subscriber Line (ADSL) Metallic Interface,” (“ANSI T1.413”) (Ex. 1007).
`
`Bowie was filed on July 30, 1997, and Yamano was filed on May 9, 1997.
`
`Both Bowie and Yamano are thus prior art at least under § 102(e). ANSI T1.413
`
`was approved on August 18, 1995, published shortly thereafter, and is prior art
`
`under § 102(b). Ex. 1003 at p. 31; Ex. 1008 (Bader Decl.) ¶ 2.
`
`12
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`VII. LEVEL OF ORDINARY SKILL IN THE ART
`
`The level of ordinary skill in the art may be reflected by the prior art of
`
`record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re
`
`GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Here, the person of ordinary skill
`
`in the art is someone knowledgeable concerning multicarrier communications.
`
`That person would have (i) a Master’s degree in Electrical and/or Computer
`
`Engineering, or equivalent training, and (ii) approximately five years of experience
`
`working in digital telecommunications. Ex. 1003 at p. 17. Lack of work experience
`
`can be remedied by additional education, and vice versa. Ex. 1003 at p. 17.
`
`VIII. NOTE REGARDING PAGE CITATIONS
`
`Petitioner’s citations to Ex. 1002 and Ex. 1007 use the page numbers added
`
`for compliance with 37 C.F.R. § 42.63(d)(2)(ii). Petitioner’s citations to the
`
`remaining exhibits use the page numbers in their original publication.
`
`IX.
`
`IDENTIFICATION OF HOW THE CLAIMS ARE UNPATENTABLE
`
`Claims 6, 10, 11, 15, 16, and 20 of the ’404 Patent are obvious under 35
`
`U.S.C. § 103(a) over Bowie in view of Yamano and ANSI T1.413. Ex. 1003 at p.
`
`34.
`
`
`
`13
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`

`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`A.
`
`Summary of Bowie
`
`Bowie is directed to a system for “conserving power in a terminal unit
`
`having a transmitter and receiver for modulated data communication over a
`
`communications loop.” Ex. 1005 at 2:10-12. A person of ordinary skill in the art
`
`would appreciate that another term for a transmitter and receiver is a “transceiver.”
`
`Ex. 1003 at p. 23. Like the ’404 patent, Bowie’s terminal unit “may include
`
`Asymmetric Digital Subscriber Line [ADSL] transmit and receive circuitry.” Ex.
`
`1005 at 2:41-43; Ex. 1003 at p.23. And, like the ’404 patent, Bowie is directed to
`
`“reducing power consumption of certain of the electronic circuits in the terminal
`
`unit upon detection of a shut-down condition” and “detect[ing] a resume signal”
`
`and “restoring power to the electronic circuits when the resume signal is detected.”
`
`Ex. 1005 at 2:13-20; Ex. 1003 at p.23.
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`Bowie describes “an ADSL unit” that “can send and receive modulated
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`digital data.” Ex. 1005 at 3:34-35. A first ADSL unit “located at the subscriber
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`premises . . . is referred to as a customer premises equipment (CPE) ADSL unit”
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`and “a second ADSL unit . . . typically located at a telephone company central
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`office . . . is known as the central office terminal (COT) unit 232.” Ex. 1005 at
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`3:53-57. A POSITA would appreciate that Bowie’s CPE ADSL unit and COT
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`ADSL unit are similar to the CPE transceiver and a CO transceiver of the ’404
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`patent. Ex. 1003 at p. 23-24. Also, just like in the ’404 patent, “[d]ata to be
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`transmitted by an ADSL unit is arranged in a structure known as a ‘frame’.” Ex.
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`1005 at 3:66-67; Ex. 1003 at p. 24. An example of Bowie’s ADSL unit is provided
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`below:
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`
`
`
`
`
`
`ADSL unit comprising
`Transmit and Receive circuitry
`
`
`
`Ex. 1003 at p. 24; Ex. 1005, Fig. 1 (annotated).
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`Bowie also describes that “[t]o reduce power requirements, the ADSL units
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`232 and 242 may enter low power mode.” Ex. 1005 at 5:6-7. For example, if “the
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`CPE unit 242 initiates low power mode, it does so by sending a shut-down signal
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`to the COT unit 232.” Ex. 1005 at 5:8-10. Then, like the ’404 patent, Bowie also
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`describes that “[u]pon receipt of the shut down signal, the COT unit 232 optionally
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`stores in memory 117 characteristics of the loop 220.” Ex. 1005 at 5:17-19; Ex.
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`1003 at p. 25. Importantly, just like the ’404 patent Bowie teaches that “[s]toring
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`loop characteristics enables rapid resumption of user data transmission when the
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`units are returned to full power mode.” Ex. 1005 at 5:22-24, Ex. 1003 at p. 25.
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`Like the ’404 patent, “[t]o return a unit that is in low power mode to full
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`power operation, a resume signal is sent to the unit” in Bowie. Ex. 1005 at 5:48-49,
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`Ex. 1003 a p. 25. “Upon receipt of the resume signal, the receiving ADSL unit”
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`such as the CPE unit 242, “returns the signal processing 111, transmitting, and
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`receiving 113 circuitry to full power mode.” Ex. 1005 at 5:5:60-62. Bowie
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`describes that loop transmission characteristics “are retrieved from memory 117
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`and used to enable data transmission to resume quickly by reducing the time
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`needed to determine loop transmission characteristics.” Ex. 1005 at 5:62-66; Ex.
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`1003 at p. 25.
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`Thus Bowie describes a transmitter and receiver system that operates in full
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`and low power modes, and which switches between the full and low power modes
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`by storing and retrieving transmission parameters in memory. Ex. 1003 at p. 25.
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`B.
`
`Summary of Yamano
`
`Just like Bowie, Yamano also teaches modems that transfer “packet-based
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`data or other information . . . on a communication channel.” Ex. 1006 at 1:10-13;
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`Ex. 1003 at p. 26. These modems include a transmitter circuit and a receiver
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`circuit, which are components of a transceiver. Ex. 1006, Figs. 1, 3. And just like
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`an ADSL unit in Bowie, the modems in Yamano may be “xDSL modems [that] are
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`collected together in a central office to provide data communications to a number
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`of remote locations.” Ex. 1006 at 2:17-20; Ex. 1003 at p. 26.
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`Yamano, however, differs from Bowie in that it teaches that transmit and
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`receive circuitry can be powered separately; that is, the transmit and receive
`
`circuitry can enter into a reduced processing mode independent of one another. Ex.
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`1003 at p. 26. For example, Yamano teaches that receive circuitry in a modem can
`
`operate in both a “full processing mode” and a “reduced processing mode.” Ex.
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`1006 at 14:25-33. The receiver is in its full processing mode “[u]pon detecting the
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`easily detected signal” where it “perform[s] full demodulation on the incoming
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`RECEIVE signal,” and the receiver is in its reduced processing mode in “the
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`absence of the easily detected signal.” Ex. 1006 at 14:25-33. When in reduced
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`processing mode, the receive circuit disables a number of components because
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`“there is no packet data being received.” Ex. 1006 at 14:33-42. This disabling of
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`components results in reduced power consumption. Ex. 1006 at 15:51-55. An
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`example receiver circuit taught in Yamano is reproduced below:
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`
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`Ex. 1006, Fig. 3.
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`While Yamano’s receive circuit is in its reduced processing mode, the
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`corresponding transmit circuit can continue to operate. Ex. 1003 at p. 27. This is
`
`indicated in Yamano in two ways. First, Yamano teaches that its transmit and
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`receive circuitry operate in full-duplex mode where each can transmit and receive
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`independent of the other. Ex. 1003 at p. 27. Second, Yamano teaches that “the
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`local transmitter circuit associated with receiver circuit 400 will not be
`
`continuously transmitting” and as a result, the echo canceler in the receive circuit
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`can be reduced, “thereby further reducing the processing requirements of the
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`receiver circuit.” Ex. 1003 at 15:63-16:5. Based on these descriptions, a POSITA
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`would understand that Yamano’s transmit circuit can continue to transmit while its
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`corresponding receive circuit is not receiving, and thus is in its reduced processing
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`mode. Ex. 1003 at p. 27.
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`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
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`To facilitate its reduced power mode, Yamano teaches that the transmit and
`
`receive circuitry can continue to transmit and receive signals with a remote system
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`in order to indicate that data is about to be sent. Ex. 1003 at p. 28. For example,
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`“the transmitter circuit transmits a predetermined non-idle state signal to indicate
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`that packet data is about to be transmitted, and then transmits the packet data.” Ex.
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`1006 at 13:53-62. “Upon detecting the easily detected signal, non-idle detector 401
`
`enables the full processing mode of receiver circuit 400, thereby causing receiver
`
`circuit 400 to perform full demodulation on the incoming RECEIVE signal.” Ex.
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`1006 at 14:25-29. This signal can sent based on a “periodic poll or some other
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`timing signal . . . to maintain synchronization of these time intervals between
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`receiver circuit 400 and the remote transmitter circuit.” Ex. 1006 at 15:29-32.
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`Thus, Yamano describes transmit and receive circuitry in a modem that can
`
`operate in a reduced power consumption mode while a synchronization signal is
`
`transmitted and received during this reduced processing mode. Ex. 1003 at p. 28.
`
`C. Modem States in Bowie and Yamano
`
`The diagrams below illustrate the various modem states based on the
`
`teaching of Bowie and Yamano. As discussed above, Bowie teaches that a modem
`
`can either be operating in a full-power mode or a low-power mode. Ex. 1003 at p.
`
`28. In the full-power mode, the transmit and receive circuitry in the modem are
`
`active and the link between the COT and CPE modems transmitting and receive
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`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
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`data. Ex. 1003 at p. 28. In the low-power mode, the transmit and receive circuitry
`
`are shut down and the link between modems is actively transmitting or receiving
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`data. Ex. 1003 at p. 28-29. The diagram below illustrates these two states:
`
`Modem States in Bowie
`
`Receive Circuit
`
`Transmit Circuit
`
`COT Modem
`
`Full Power
`
`Full Power
`
`Transmit Circuit
`
`Receive Circuit
`
`CPE Modem
`
`Full Power Mode
`(Transmitters and Receivers are active)
`
`Receive Circuit
`
`Transmit Circuit
`
`COT Modem
`
`Low Power
`
`Low Power
`
`Transmit Circuit
`
`Receive Circuit
`
`CPE Modem
`
`Low Power Mode
`(Transmitters and Receivers are inactive)
`
`
`
`Ex. 1003 at p. 29.
`
`Yamano differs from Bowie in that the transmit circuitry of a modem is shut
`
`down when not transmitting data and the receive circuitry of the modem is shut
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`down when not receiving data. Ex. 1003 at p. 29. This is possible because the
`
`transmit and receive circuitry in Yamano operate independently in a full-duplex
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`mode where transmitting and receiving can be performed simultaneously. Ex. 1003
`
`at p. 29. Based on these teachings, Yamano’s modem can operate in four states as
`
`illustrated in the diagram below:
`
`Modem States in Yamano
`
`Receive Circuit
`
`Transmit Circuit
`
`COT Modem
`
`Full Power
`
`Full Power
`
`Transmit Circuit
`
`Receive Circuit
`
`CPE Modem
`
`Full Power Mode
`(Transmitters are active and transmitting data)
`(Receivers are active and receiving data)
`
`Receive Circuit
`
`Trans