UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`
`
`
`
`Cisco Systems, Inc.,
`Petitioner
`
`———————
`
`Case IPR2016-_____
`
`U.S. Patent No. 8,611,404
`
`_____________________
`
`
`
`DECLARATION OF DR. SAYFE KIAEI, UNDER
`37 C.F.R. § 1.68 IN SUPPORT OF PETITION FOR
`INTER PARTES REVIEW OF U.S. PATENT NO. 8,611,404
`
`
`1
`
`CSCO-1003
`
`
`
`
`
`
`
`Cisco v. TQ Delta
`Page 1 of 79
`
`

`
`
`
`
`I. 
`
`II. 
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`TABLE OF CONTENTS
`
`Introduction ...................................................................................................... 3 
`
`Background and Qualifications ....................................................................... 5 
`
`III.  Understanding of Patent Law .......................................................................... 7 
`
`IV.  The ’404 Patent .............................................................................................. 10 
`
`A.  Overview ............................................................................................. 10 
`
`B. 
`
`Prosecution History ............................................................................. 14 
`
`V. 
`
`Level of Ordinary Skill in the Pertinent Art .................................................. 16 
`
`VI.  Broadest Reasonable Interpretation ............................................................... 18 
`
`A. 
`
`B. 
`
`“store/storing, in a low power mode” (claims 6, 11, 16) .................... 18 
`
`“synchronization signal” (claims 6, 11, 16) ........................................ 20 
`
`VII.  Detailed Invalidity Analysis .......................................................................... 21 
`
`A. 
`
`Background on Prior Art References .................................................. 23 
`
`1. 
`
`2. 
`
`3. 
`
`4. 
`
`Background on Bowie ............................................................. 23 
`
`Background on Yamano .......................................................... 26 
`
`Modem States in Bowie and Yamano ..................................... 28 
`
`Background on ANSI T1.413-1995 ......................................... 32 
`
`B. 
`
`Claims 6, 10, 11, 15, 16, and 20 are Obvious over Bowie,
`Yamano, and ANSI T1.413 ................................................................. 34 
`
`1. 
`
`2. 
`
`Reasons to Combine Bowie and Yamano ............................... 34 
`
`Reasons to Combine Bowie/Yamano with ANSI T1.413 ....... 37 
`
`C. 
`
`Analysis of Claims .............................................................................. 38 
`
`VIII.  Conclusion ..................................................................................................... 79
`
`
`
`2
`
`Ex. 1003
`
`Page 2 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`I, Sayfe Kiaei, do hereby declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained as an independent expert witness on behalf of
`
`Cisco Systems, Inc. (“Cisco”) for the above-captioned Petition for Inter Partes
`
`Review (“IPR”) of U.S. Patent No. 8,611,404 (“the ’404 patent”). I am being
`
`compensated at my usual and customary rate of $400 per hour for the time I spend
`
`in connection with this IPR. My compensation is not affected by the outcome of
`
`this IPR.
`
`2.
`
`I have been asked to provide my opinions regarding whether claims 6,
`
`10, 11, 15, 16, and 20 (“the Challenged Claims”) of the ’404 patent are
`
`unpatentable as they would have been obvious to a person having ordinary skill in
`
`the art (“POSITA”) at the time of the alleged invention. It is my opinion that all of
`
`the limitations of these claims would have been obvious to a POSITA after
`
`reviewing the Bowie, Yamano, and ANSI T1.413 references, as discussed further
`
`below.
`
`3.
`
`The ’404 patent issued on December 17, 2013, from U.S. Patent Appl.
`
`No. 13/152,558, filed Jun. 3, 2011, now U.S. Pat. No. 8,437,382, which is a
`
`continuation of U.S. Patent Appl. No. 12/615,946, filed Nov. 10, 2009, now U.S.
`
`Pat. No. 7,978,753, which is a continuation of U.S. Patent Appl. No. 11/425,507,
`
`filed Jun. 21, 2006, now U.S. Pat. No. 7,697,598, which is a continuation of U.S.
`
`
`
`3
`
`Ex. 1003
`
`Page 3 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`Patent Appl. No. 11/289,516, filed Nov. 30, 2005, which is a continuation of U.S.
`
`Patent Appl. No. 11/090,183, filed Mar. 28, 2005, which is a continuation of U.S.
`
`Patent Appl. No. 10/778,083, filed Feb. 17, 2004, which is a continuation of U.S.
`
`Patent Appl. No. 10/175,815, filed Jun. 21, 2002, which is a continuation of U.S.
`
`Patent Appl. No. 09/581,400, filed Jun. 13, 2000, now U.S. Pat. No. 6,445,730,
`
`which is a 371 of International Application No. PCT/US99/01539, filed Jan. 26,
`
`1999, which claims the benefit of and priority to U.S. Application No. 60/072,447,
`
`filed Jan. 26, 1998.
`
`4.
`
`The face of the ’440 patent names John A. Greszczuk, Richard W.
`
`Gross, Halil Padir N., Michale A. Tzannes, as the inventors. Further, the face of the
`
`’404 patent identifies TQ Delta, LLC, as the assignee of the ’404 patent.
`
`5.
`
`In preparing this Declaration, I have reviewed:
`
`a)
`
`b)
`
`c)
`
`the ’404 patent, Ex. 1001;
`
`the file history of the ’404 patent, Ex. 1002; and
`
`the prior art references discussed below: Ex. 1005 (Bowie), Ex.
`
`1006 (Yamano), and Ex. 1007 (ANSI T1.413), and
`
`d)
`
`prior art relevant DSL technology: Ex. 1009 (Fosmark).
`
`6.
`
`In forming the opinions expressed in this Declaration, I have relied
`
`upon my education and experience in the relevant field of art, and have considered
`
`the viewpoint of a POSITA, as of January 26, 1998. I have also considered:
`
`
`
`4
`
`Ex. 1003
`
`Page 4 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`the documents listed above,
`
`the additional documents and references cited in the analysis
`
`a)
`
`b)
`
`below,
`
`c)
`
`the relevant legal standards, including the standard for
`
`obviousness provided in and any additional authoritative
`
`documents as cited in the body of this declaration, and
`
`d) my knowledge and experience based upon my work in this area
`
`as described below.
`
`7.
`
`I understand that claims in an IPR are given their broadest reasonable
`
`interpretation in view of the patent specification and the understandings of a
`
`POSITA. I further understand that this is not the same claim construction standard
`
`as one would use in a District Court proceeding.
`
`II. BACKGROUND AND QUALIFICATIONS
`
`8. My qualifications are set forth in my curriculum vitae, a copy of
`
`which is included as Exhibit 1004. As set forth in my curriculum vitae:
`
`9.
`
`I earned my B.S. in Computer and Electrical Engineering from
`
`Washington State University-Northeastern in 1982, a M.S. in Electrical and
`
`Computer Engineering from Washington State University in 1984, and a PhD. in
`
`Electrical and Computer Engineering from Washington State University in 1987.
`
`
`
`5
`
`Ex. 1003
`
`Page 5 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`I have been a Professor at Arizona State University (ASU) since 2001.
`
`10.
`
`In this capacity, I have served as a Motorola Endowed Professor and Chair in
`
`analog and RF integrated circuits. I am also Director of ASU’s Center on Global
`
`Energy Research and Director of NSF Connection One Research Center with a
`
`focus on integrated communication systems.
`
`11. From 2009 to 2012, and concurrent with my position at ASU, I was
`
`the Associate Dean of Research at the Ira A. Fulton Schools of Engineering.
`
`12. From 1993 to 2001, I was a senior member of technical staff with the
`
`Wireless Technology Center and Broadband Operations at Motorola. In that
`
`capacity, I was responsible for the development of RF and transceiver integrated
`
`circuits, GPS RF IC and digital subscriber lines (DSL) transceivers.
`
`13. From 1987 to 1993, I served as an Associate Professor at Oregon
`
`State University.
`
`14.
`
`In addition to the above noted positions, I was the Co-Director of the
`
`Industry-University Center for the Design of Analog/Digital ICs (CDADIC). Also,
`
`I am an IEEE Fellow, and have been the Chair and on the Technical Program
`
`Committee of several IEEE conferences including RFIC, MTT, ISCAS and other
`
`international conferences.
`
`15.
`
`In total, I have more than thirty years of experience in research,
`
`development, design, commercialization, evaluation, and testing, of wireless
`
`
`
`6
`
`Ex. 1003
`
`Page 6 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`technologies, products, and systems. My research interests include wireless
`
`transceiver design, RF, and mixed-signal IC’s in CMOS and SiGe.
`
`16.
`
`I have published more than 100 journal and conference papers and
`
`have been awarded several U.S. patents.
`
`17.
`
`I have organized and chaired international conferences on
`
`electrochemical capacitor technology and taught short courses at Electrochemical
`
`Society and IEEE meetings.
`
`III. UNDERSTANDING OF PATENT LAW
`
`18.
`
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law was provided to me by Cisco’s attorneys.
`
`19.
`
`I understand that prior art to the ’404 patent includes patents and
`
`printed publications in the relevant art that predate the priority date of the alleged
`
`invention recited in the ’404 patent. I have applied the date of January 26, 1998,
`
`the filing date of the earliest provisional application in the chain of continuing
`
`applications resulting in the ’404 patent, as the priority date. I understand,
`
`however, that the ’404 patent claims may not be entitled to this earlier date, and
`
`that the actual entitled priority date may be later.
`
`20.
`
`I understand that a claim is invalid if it would have been obvious.
`
`Obviousness of a claim requires that the claim would have been obvious from the
`
`
`
`7
`
`Ex. 1003
`
`Page 7 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`perspective of a POSITA at the time the alleged invention was made. I understand
`
`that a claim could have been obvious from a single prior art reference or from a
`
`combination of two or more prior art references.
`
`21.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged
`
`invention and the prior art, and the level of ordinary skill in evaluating the
`
`pertinent art.
`
`22.
`
`I further understand that certain factors may support or rebut the
`
`obviousness of a claim. I understand that such secondary considerations include,
`
`among other things, commercial success of the patented invention, skepticism of
`
`those having ordinary skill in the art at the time of invention, unexpected results of
`
`the invention, any long-felt but unsolved need in the art that was satisfied by the
`
`alleged invention, the failure of others to make the alleged invention, praise of the
`
`alleged invention by those having ordinary skill in the art, and copying of the
`
`alleged invention by others in the field. I understand that there must be a nexus—a
`
`connection—between any such secondary considerations and the alleged invention.
`
`I also understand that contemporaneous and independent invention by others is a
`
`secondary consideration tending to show obviousness.
`
`23.
`
`I further understand that a claim would have been obvious if it unites
`
`old elements with no change to their respective functions, or alters prior art by
`
`
`
`8
`
`Ex. 1003
`
`Page 8 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`mere substitution of one element for another known in the field and that
`
`combination yields predictable results. Also, I understand that obviousness does
`
`not require physical combination/bodily incorporation, but rather consideration of
`
`what the combined teachings would have suggested to persons of ordinary skill in
`
`the art at the time of the alleged invention.
`
`24. While it may be helpful to identify a reason for this combination,
`
`common sense should guide and no rigid requirement of finding a teaching,
`
`suggestion, or motivation to combine is required. When a product is available,
`
`design incentives and other market forces can prompt variations of it, either in the
`
`same field or different one. If a POSITA can implement a predictable variation,
`
`obviousness likely bars its patentability. For the same reason, if a technique has
`
`been used to improve one device and a POSITA would recognize that it would
`
`improve similar devices in the same way, using the technique would have been
`
`obvious. I understand that a claim would have been obvious if common sense
`
`directs one to combine multiple prior art references or add missing features to
`
`reproduce the alleged invention recited in the claims.
`
`25.
`
`I am not aware of any allegations by the named inventor of the ’404
`
`patent or any assignee of the ’404 patent that any secondary considerations tend to
`
`rebut the obviousness of any Challenged Claim of the ’404 patent.
`
`
`
`9
`
`Ex. 1003
`
`Page 9 of 79
`
`

`
`
`
`
`26.
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`27. The analysis in this declaration is in accordance with the above-stated
`
`legal principles.
`
`IV. THE ’404 PATENT
`
`A. Overview
`
`28. The ’404 patent relates to a multicarrier transceiver “with a sleep
`
`mode in which it idles with reduced power consumption.” Ex. 1001, Abstract. The
`
`’404 patent states that “[t]he full transmission and reception capabilities of the
`
`transceiver are quickly restored when needed, without requiring the full (and time-
`
`consuming) initialization commonly needed to restore such transceivers to
`
`operation after inactivity.” Id. This transceiver, according to the ’404 patent, may
`
`be included in the “DSL” systems, such as “xDSL”, “ADSL,” and “HDSL.” Id.,
`
`1:42-47.
`
`29. The ’404 patent states that in the DSL systems the data
`
`communication occurs using a “first transceiver located at the site of a customer’s
`
`premises” and the “second transceiver located at the central telephone office.” Id.,
`
`3:63-66. The ’404 patent refers to the “first transceiver” as the “CPE transceiver,”
`
`and to the “second transceiver” as the “CO transceiver.” Id. 3:65-67. During
`
`
`
`10
`
`Ex. 1003
`
`Page 10 of 79
`
`

`
`
`
`
`normal operation, the CPE transceiver and the CO transceiver exchange data using
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`“superframes.” Id., 5:11-12. Each “superframe” includes “a sequence of data
`
`frames” followed “by a synchronization frame.” Id., 5:6-9. Also during normal
`
`operation “[t]he timing reference signal 62a is transmitted to the [CPE] transmitter
`
`from the transmitter with which the receiver 16 communicated (e.g., the CO
`
`transmitter)” which “is synchronized with the Master Clock in the transmitter” and
`
`whose “frequency defines the frame rate of the transceivers.” Id., 5:39-45.
`
`30.
`
`In the ’404 patent, the CO and CPE transceiver can enter a low power
`
`consumption mode. Id., 6:27-30. While the description of the ’404 patent’s low
`
`power mode is described below in terms of the CPE transceiver, the ’404 patent
`
`acknowledges that the process is the same for the CO transceiver. Id., 4:11-13.
`
`31. To enter the low power mode, the CPE transceiver first transmits an
`
`“Intend To Enter Sleep Mode” notification to the CO transceiver. Id., 6:41, 62-63.
`
`If sleep mode is permissible, the CO transceiver responds to the notification “by
`
`transmitting an ‘Acknowledge Sleep Mode’ notification.” Id., 6:52-54. The CPE
`
`transceiver then transmits an “Entering Sleep Mode” notification to the CO
`
`transceiver, which is reciprocated by the CO transceiver. Id., 6:61-67. Upon
`
`receiving the “Entering Sleep Mode” notification from the CO transceiver, the
`
`CPE transceiver then enters the sleep mode state. Id., 7:33-35. In the sleep mode
`
`state, the CPE transceiver “stores its state” in connection with CO transceiver,
`
`
`
`11
`
`Ex. 1003
`
`Page 11 of 79
`
`

`
`
`
`
`including “the transmission fine gains” and “the Bit Allocation Tables” parameters
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`in the “state memory.” Id., 7:33-42. The CPE transceiver then “reduces power to
`
`the digital modulator/demodulator circuitry comprising IFFT 20 and FFT 56, as
`
`well as to and transmitter data line drivers 26” but “continues to advance the frame
`
`counter 34 in accordance with the received synchronizing signal 62a.” Id., 7:44-49.
`
`32. Likewise, upon receiving the “Entering Sleep Mode” notification, the
`
`CO transceiver enters sleep mode. Id., 6:65-67. The CO transceiver then “stores its
`
`state in its own state memory corresponding to the state memory 36 of CPE
`
`transceiver 10.” Id., 6:67-7:2. The CO transceiver also “continues to advance the
`
`frame count and superframe count during the period of power-down in order to
`
`ensure synchrony with the remote CPE transceiver when communications are
`
`resumed.” Id., 7:9-12.
`
`33. To exit the low power mode, the CPE “receives an ‘Awaken’
`
`indication.” Id., 7:59-62. “In response to the ‘Awaken’ signal, the CPE transceiver
`
`retrieves its stored state from the state memory 38; restores full power to its
`
`circuitry.” Id., 7:64-66. The CPE also transmits an “Exiting Sleep Mode” to the CO
`
`transceiver, which upon “detecting the ‘Exit Sleep Mode’ notification from the
`
`CPE transceiver . . . exits sleep mode by restoring its state and restoring its power.”
`
`Id., 8:1-4.
`
`
`
`12
`
`Ex. 1003
`
`Page 12 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`34. The purported invention of the ’440 patent is the CPE transceiver’s
`
`ability to “begin transmitting immediately or after only a few frames delay”
`
`because “it need not repeat the initialization … to establish the requisite
`
`parameters.” Id. 8:4-7.
`
`35.
`
`Independent claims 6 and 11 are representative of the Challenged
`
`Claims:
`
`6. An apparatus comprising a transceiver operable to:
`
`receive, in a full power mode, a plurality of superframes,
`
`wherein the superframe comprises a plurality of data frames
`followed by a synchronization frame;
`
`
`
`
`
`receive, in the full power mode, a synchronization signal;
`
`transmit a message to enter into a low power mode;
`
`store, in a low power mode, at least one parameter
`
`associated with the full power mode operation wherein the at
`least one parameter comprises at least one of a fine gain
`parameter and a bit allocation parameter;
`
`receive, in the low power mode, a synchronization signal;
`
`and
`
`exit from the low power and restore the full power mode
`
`by using the at least one parameter and without needing to
`reinitialize the transceiver.
`
`11. A method of multicarrier communications comprising:
`
`
`
`13
`
`Ex. 1003
`
`Page 13 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`transmitting, by a transceiver, in a full power mode, a
`plurality of superframes, wherein the superframe comprises
`a plurality of data frames followed by a synchronization
`frame;
`
`transmitting, in the full power mode, a synchronization
`signal;
`
`receiving a message to enter into a low power mode;
`
`entering into the low power mode by reducing a power
`consumption of at least one portion of a transmitter;
`
`storing, in the low power mode, at least one parameter
`associated with the full power mode operation wherein the at
`least one parameter comprises at least one of a fine gain
`parameter and a bit allocation parameter;
`
`transmitting, in the low power mode, a synchronization
`signal; and
`
`exiting from the low power and restoring the full power
`mode by using the at least one parameter and without
`needing to reinitialize the transceiver.
`
`B.
`
`36.
`
`Prosecution History
`
`I have reviewed the prosecution history of the ’404 patent.
`
`37. Application No. 13/887,889 (“the ’889 application”)—that issued as
`
`the ’404 patent—was filed on May 6, 2013. The specification of the ’889
`
`application was amended to include a cross reference section to related
`
`
`
`14
`
`Ex. 1003
`
`Page 14 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`applications that appear to claim priority to U.S. Provisional Application No.
`
`60/072,447 filed on January 26, 1998. On August 21, 2013, a preliminary
`
`amendment was filed that cancelled claims 1-17 and added new claims 18-37.
`
`38. On September 6, 2013, the Patent Office issued a non-final rejection.
`
`The non-final rejection rejected claims 18-37 under 35 U.S.C. § 112, first
`
`paragraph, for failing to comply with enablement requirement. The Examiner also
`
`indicated that the independent claims (18, 23, 28, and 33) would be allowable if
`
`amended to overcome the § 112 rejection. On September 12, 2013, the Applicants
`
`filed a response amending claims 18-19, 23-24, 28-29, and 33-24.
`
`39. On October 23, 2013, the Patent Office issued a Notice of
`
`Allowability, indicating claims 18-37 recite allowable subject matter. In the
`
`Allowance, the Examiner indicated that:
`
`none of the prior art discloses or suggests that An apparatus and a
`method, comprising a transceiver operable to: comprises a plurality of
`data frames followed by a synchronization frame; transmit, in the full
`power mode, a synchronization signal; receive a message to enter into
`a low power mode; enter into the low power mode by reducing a
`power consumption of at least one portion of a transmitter; store, in
`the low power mode, at least one parameter associated with the full
`power mode operation wherein the at least one parameter comprises at
`least one of a fine gain parameter and a bit allocation parameter;
`transmit, in the low power mode, a synchronization signal; and exit
`from the low power and re-enter into .restore the full power mode by
`
`
`
`15
`
`Ex. 1003
`
`Page 15 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`using the at least one parameter and without needing to reinitialize the
`transceiver
`
`Ex. 1002 at 38.
`
`40. Thus, it appears that the claims where allowed without the Examiner
`
`applying or even citing any prior art against the claims.
`
`V. LEVEL OF ORDINARY SKILL IN THE PERTINENT ART
`
`41.
`
`I understand that the level of ordinary skill may be reflected by the
`
`prior art of record, and that a POSITA to which the claimed subject matter pertains
`
`would have the capability of understanding the scientific and engineering
`
`principles applicable to the pertinent art. I understand that one of ordinary skill in
`
`the art has ordinary creativity, and is not a robot.
`
`42.
`
`I understand there are multiple factors relevant to determining the
`
`level of ordinary skill in the pertinent art, including (1) the levels of education and
`
`experience of persons working in the field at the time of the invention; (2) the
`
`sophistication of the technology; (3) the types of problems encountered in the field;
`
`and (4) the prior art solutions to those problems. There are likely a wide range of
`
`educational backgrounds in the technology field pertinent to the ’404 patent.
`
`43.
`
`I am very familiar with the knowledge and capabilities that a POSITA
`
`of multicarrier communication systems (such as digital subscriber line (DSL)
`
`communications) would have possessed during the late 90s and early 2000s,
`
`especially as it pertains to testing lines for their support of multicarrier
`
`
`
`16
`
`Ex. 1003
`
`Page 16 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`communications. Specifically, my experience in the industry, with colleagues from
`
`academia, and with engineers practicing in the industry during the relevant
`
`timeframe allowed me to become personally familiar with the knowledge and
`
`capabilities of a person of ordinary skill in the area of multicarrier
`
`communications. Unless otherwise stated, my testimony below refers to the
`
`knowledge of one of ordinary skill in the art in the field of multicarrier
`
`communications during the time period around the priority date of the ’404 patent.
`
`44.
`
`In my opinion, the level of a POSITA needed to have the capability of
`
`understanding multicarrier communications and engineering principles applicable
`
`to the ’404 patent is (i) a Master’s degree in Electrical and/or Computer
`
`Engineering, or equivalent training, and (ii) approximately five years of experience
`
`working in digital telecommunications. Lack of work experience can be remedied
`
`by additional education, and vice versa. Such academic and industry experience
`
`would be necessary to appreciate what was obvious and/or anticipated in the
`
`industry and what a POSITA would have thought and understood at the time. For
`
`example, an understanding of the ’404 patent requires an appreciation of xDSL
`
`modems and communications between transceivers. Such knowledge would be
`
`within the level of skill in the art. I believe I possess such experience and
`
`knowledge, and am qualified to opine on the ’404 patent.
`
`
`
`17
`
`Ex. 1003
`
`Page 17 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`45. For purposes of this Declaration, in general, and unless otherwise
`
`noted, my statements and opinions, such as those regarding my experience and the
`
`understanding of a POSITA generally (and specifically related to the references I
`
`consulted herein), reflect the knowledge that existed in the field as of January
`
`1998.
`
`VI. BROADEST REASONABLE INTERPRETATION
`
`46.
`
`It is my understanding that in order to properly evaluate the ’404
`
`patent, the terms of the claims must first be interpreted. It is my understanding that
`
`the claims are to be given their broadest reasonable interpretation in light of the
`
`specification. It is my further understanding that claim terms are given their
`
`ordinary and accustomed meaning as would be understood by a POSITA, unless
`
`the inventor, as a lexicographer, has set forth a special meaning for a term.
`
`47.
`
`In order to construe the claims, I have reviewed the entirety of the
`
`’404 patent along with its prosecution history.
`
`A.
`
`“store/storing, in a low power mode” (claims 6, 11, 16)
`
`48. The term “store, in a low power mode” appears in claim 6. The term
`
`“storing, in a low power mode” appears in claims 11 and 16.
`
`49. The ’404 patent specification does not use this term, but the
`
`specification does disclose a CO transceiver and a CPE transceiver that store their
`
`respective states in memory upon “Entering Sleep Mode” and retain these states in
`
`
`
`18
`
`Ex. 1003
`
`Page 18 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`memory while in sleep mode. Ex. 1001 at 6:67-7:9; 7:35-42. Once the parameters
`
`are stored, the CO and CPE transceivers enter a low power mode by reducing
`
`power to their respective circuitry. Id., 7:15-20; 7:44-47.
`
`50. With respect to the CO transceiver:
`
`After it has received acknowledgment from the CO transceiver, the
`CPE transceiver transmits an “Entering Sleep Mode” notification (step
`86) to the CO transceiver and ceases transmission, either immediately
`or after a given number of frames. The CO transceiver detects this
`notification; transmits its own “Entering Sleep Mode” notification
`(step 88); and enters sleep mode (step 90). In pursuance of this,
`the CO transceiver stores its state in its own state memory
`corresponding to the state memory 36 of CPE transceiver 10. The
`state of the CO or CPE transceivers preferably includes at least the
`frequency and time-domain equalizer coefficients (FDQ; TDQ) and
`the echo-canceller coefficients (ECC) of its receiver portion and the
`gain of its transmitter portion; the transmission and reception data
`rates;
`the
`transmission and reception coding parameters;
`the-
`transmission fine gains; and the Bit Allocation Tables.
`
`Ex. 1001, 6:61-7:9 (emphasis added). The CO transceiver can then “exit[] sleep
`
`mode by restoring its state and restoring power.” Id., 8:1-4 (emphasis added).
`
`51. With respect to the CPE transceiver:
`
`In response to the “Entering Sleep Mode” notification from the CO
`transceiver, the CPE transceiver enters the sleep mode (step 92). In
`particular, it stores its state (step 94) in state memory 38; as noted
`
`
`
`19
`
`Ex. 1003
`
`Page 19 of 79
`
`

`
`
`
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`above in connection with the CO transceiver, this includes preferably
`at least the frequency and time-domain equalizer coefficients (FDQ;
`TDQ) and the echo-canceller coefficients (ECC) of its receiver and
`the gain of its transmitter; the transmission and reception data rates;
`the transmission and reception coding parameters; the transmission
`fine gains; and the Bit Allocation Tables.
`
`Id., 7:33-42. The CPE transceiver can then “retrieve[] its stored state from the state
`
`memory 38” and “restore[] full power to its circuitry.” Id., 7:65-66.
`
`52. Thus, while the CO and the CPE both store their respective states
`
`while entering sleep mode, they also retain these states during sleep mode such that
`
`they can be restored upon waking up. Accordingly, consistent with the usage of the
`
`term “store/storing, in a lower power mode” in the ’404 patent, I believe that a
`
`POSITA would have understood the broadest reasonable interpretation of the
`
`“store/storing, in a/the lower power mode” to include maintaining in memory while
`
`in a reduced power consumption mode.
`
`B.
`
`“synchronization signal” (claims 6, 11, 16)
`
`53. The term “synchronization signal” appears in each of claims 6, 11,
`
`and 16.
`
`54. The ’404 patent does not provide an express definition for the term
`
`“synchronization signal.” Rather, the ’404 patent specification describes that
`
`during normal (non-sleep mode) operations, a “timing reference signal 62 [] is
`
`transmitted from the transmitter with which the receiver 16 communicates (e.g.,
`
`
`
`20
`
`Ex. 1003
`
`Page 20 of 79
`
`

`
`
`
`
`the CO transmitter).” The signal may be “a pure tone of fixed frequency and phase
`
`Declaration of Dr. Sayfe Kiaei Under 37 C.F.R. § 1.68 in Support of
`Petition for Inter Partes Review of U.S. Patent No. 8,611,404
`
`
`which is synchronized with the Master Clock in the transmitter,” though “[o]ther
`
`forms of timing signal may . . . be used.” Ex. 1001, 5:39-45. In one example, the
`
`’404 patent describes a “synchronizing pilot tone 62a” which is used “to maintain
`
`synchronization during the power down or idle state” between a CO transceiver
`
`and CPE transceiver. Id., 7:13-15.
`
`55. Fig. 1B, reproduced below illustrates an example “timing signal used
`
`in accordance with the invention.” Id., 3:52-53.
`
`
`
`Id., Fig. 1B.
`
`56. Consistent with the usage of the term “synchronization signal” in the
`
`’404 patent specification, I believe that a POSITA would have understood the
`
`broadest reasonable interpretation of the “synchronization signal” to include a
`
`signal used to maintain timing between transceivers.
`
`VII. DETAILED INVALIDITY ANALYSIS
`
`57.
`
`I have been asked to provide my opinion as to whether the Challenged
`
`Claims of the ’404