UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________
`
`CISCO SYSTEMS, INC.,
`Petitioner
`
`v.
`
`TQ DELTA LLC,
`Patent Owner
`_____________________
`
`Case IPR2016-01466
`Patent No. 8,611,404
`_____________________
`
`PETITIONER’S NOTICE OF APPEAL
`
`via E2E
`Patent Trial and Appeal Board
`
`via Hand Delivery
`Director of the United States Patent and Trademark Office
`c/o Office of the General Counsel, 10B20
`Madison Building East
`600 Dulany Street
`Alexandria, VA 22314
`
`via CM/ECF
`United States Court of Appeals for the Federal Circuit
`
`

`

`
`
`
`
`
`
`Case No. IPR2016-01466
`Petitioner’s Notice of Appeal
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`Pursuant to 35 U.S.C. §§ 141-44 and 319, and 37 C.F.R. § 90.2-90.3, notice
`
`is hereby given that Petitioner Cisco Systems, Inc. (“Petitioner”) appeals to the
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`United States Court of Appeals for the Federal Circuit from the Final Written
`
`Decision entered February 7, 2018 (Paper 34) in IPR2016-01466, and all prior and
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`interlocutory rulings related thereto or subsumed therein.
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`In accordance with 37 C.F.R. § 90.2(a)(3)(ii), Cisco Systems, Inc.’s issues
`
`on appeal include at least:
`
`(i) the Board erred in failing to find claims 6, 10, 11, 15, 16, and 20 of U.S.
`
`Patent No. 8,611,404 unpatentable;
`
`(ii) the Board erred in failing to find claims 6, 10, 11, 15, 16, and 20 obvious
`
`over the combination of Bowie, Yamano, and ANSI T1.413;
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`(iii) the Board erred in construing the term “synchronization signal” to
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`mean “a signal allowing synchronization between the clock of the transmitter of
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`the signal and the clock of the receiver of the signal”; and
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`(iv) any findings or determinations supporting or related to the
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`aforementioned issues as well as all other issues decided adversely to Cisco
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`Systems, Inc. in any orders, decisions, rulings, phone conference decisions, and/or
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`opinions.
`
`Pursuant to 37 C.F.R. § 90.3, this Notice of Appeal is timely filed within 63
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`days of the Final Written Decision dated February 7, 2018.
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`Case No. IPR2016-01466
`Petitioner’s Notice of Appeal
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`Simultaneously with this submission, Cisco Systems, Inc. is filing a true and
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`correct copy of this Notice of Appeal with the Director of the United States Patent
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`and Trademark Office and a true and correct copy of the same, along with the
`
`required docketing fee, with the Clerk of the United States Court of Appeals for the
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`Federal Circuit as set forth in the accompanying Certificate of Filing.
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`Dated: April 10, 2018
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`
`
`
`
`
`
`Respectfully submitted,
`
`/David L. McCombs/
`David L. McCombs
`Reg. No. 32,271
`
`
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`Case No. IPR2016-01466
`Petitioner’s Notice of Appeal
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`CERTIFICATE OF FILING
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`The undersigned hereby certifies that, in addition to being electronically
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`filed through PTAB E2E, a true and correct copy of the above-captioned
`
`PETITIONER’S NOTICE OF APPEAL is being filed by hand with the Director on
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`April 10, 2018, at the following address:
`
`Director of the United States Patent and Trademark Office
`c/o Office of the General Counsel, 10B20
`Madison Building East
`600 Dulany Street
`Alexandria, VA 22314
`
`The undersigned also hereby certifies that a true and correct copy of the
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`above-captioned PETITIONER’S NOTICE OF APPEAL and the filing fee is
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`being filed via CM/ECF with the Clerk’s Office of the United States Court of
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`Appeals for the Federal Circuit on April 10, 2018.
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`Dated: April 10, 2018
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`
`
`
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`
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`Respectfully submitted,
`
`
`
`/David L. McCombs/
`David L. McCombs
`Reg. No. 32,271
`Attorney for Petitioner
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`Case No. IPR2016-01466
`Petitioner’s Notice of Appeal
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`CERTIFICATE OF SERVICE
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`The undersigned hereby certifies that the foregoing PETITIONER’S
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`NOTICE OF APPEAL was served electronically via e-mail on April 10, 2018, in
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`its entirety on the following counsel for Patent Owner:
`
`Peter J. McAndrews
`Thomas J. Wimbiscus
`Scott P. McBride
`Christopher M. Scharff
`David Z. Petty
`Rajendra A. Chiplunkar
`MCANDREWS, HELD & MALLOY, LTD.
`pmcandrews@mcandrews-ip.com
`twimbiscus@mcandrews-ip.com
`smcbride@mcandrews-ip.com
`cscharff@mcandrews-ip.com
`dpetty@mcandrews-ip.com
`rchiplunkar@mcandrews-ip.com
`
`Dated: April 10, 2018
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`
`
`
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`
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`Respectfully submitted,
`
`
`
`/David L. McCombs/
`David L. McCombs
`Reg. No. 32,271
`Attorney for Petitioner
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`Trials@uspto.gov
`571-272-7822
`
`Paper No. 34
`Entered: February 7, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`CISCO SYSTEMS, INC.,
`Petitioner,
`
`v.
`
`TQ DELTA, LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01466
`Patent 8,611,404 B2
`____________
`
`Before SALLY C. MEDLEY, TREVOR M. JEFFERSON, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`CLEMENTS, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`

`

`IPR2016-01466
`Patent 8,611,404 B2
`
`INTRODUCTION
`I.
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`Cisco Systems, Inc. (“Petitioner”) challenges claims 6, 10, 11, 15, 16, and 20
`(“the challenged claims”) of U.S. Patent No. 8,611,404 B2 (Ex. 1001, “the
`’404 patent”), owned by TQ Delta, LLC (“Patent Owner”). We have
`jurisdiction under 35 U.S.C. § 6. This Final Written Decision is entered
`pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73. For the reasons
`discussed below, Petitioner has not shown by a preponderance of the
`evidence that the challenged claims are unpatentable. Patent Owner’s
`Motion to Exclude is dismissed.
`
`A. Procedural History
`Petitioner filed a Petition requesting an inter partes review of claims
`6, 10, 11, 15, 16, and 20 of the ’404 patent. Paper 1 (“Pet.”). Patent Owner
`filed a Preliminary Response. Paper 6. On February 9, 2017, we instituted
`inter partes review of claims 6, 10, 11, 15, 16, and 20 of the ’404 patent as
`unpatentable under 35 U.S.C. § 103(a)1 over Bowie,2 Yamano,3 and ANSI
`T1.413.4 Paper 7 (“Inst. Dec.”), 26.
`
`1 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the ’404
`patent has an effective filing date before the effective date of the applicable
`AIA amendments, we refer to the pre-AIA versions of 35 U.S.C. §§ 102 and
`103.
`2 U.S. Patent No. 5,956,323; issued Sept. 21, 1999 (Ex. 1005) (“Bowie”).
`3 U.S. Patent No. 6,075,814; issued June 13, 2000 (Ex. 1006) (“Yamano”).
`4 Network and Customer Installation Interfaces – Asymmetric Digital
`Subscriber Line (ADSL) Metallic Interface, AMERICAN NATIONAL
`STANDARDS INSTITUTION (ANSI) T1.413-1995 STANDARD (Ex.
`1007) (“ANSI T1.413”).
`
`2
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`IPR2016-01466
`Patent 8,611,404 B2
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`Thereafter, Patent Owner filed a Patent Owner Response (Paper 11,
`“PO Resp.”), to which Petitioner filed a Reply (Paper 14, “Reply”).
`Pursuant to an Order (Paper 21), Patent Owner filed a listing of alleged
`statements and evidence in connection with Petitioner’s Reply it deemed to
`be beyond the proper scope of a reply. Paper 22. Petitioner filed a response
`to Patent Owner’s listing. Paper 27.
`We held a hearing on November 8, 2017, and a transcript of the
`hearing is included in the record. Paper 33 (“Tr.”).
`
`B. Related Proceedings
`The parties indicate that the ’404 patent is the subject of several
`district court cases. Pet. 1; Paper 3, 2–3.
`
`C. The ’404 patent (Ex. 1001)
`The ’404 patent discloses a method and apparatus for establishing a
`power management sleep state in a multicarrier system. (cid:40)(cid:91)(cid:17)(cid:3)(cid:20)(cid:19)(cid:19)(cid:20)(cid:15)(cid:3)(cid:20)(cid:29)(cid:22)(cid:20)(cid:3013)(cid:22)(cid:22)(cid:17)(cid:3)(cid:3)
`The ’404 patent discloses an asynchronous digital subscriber loop (ADSL)
`system having a first transceiver located at the site of a customer’s premises
`(“CPE transceiver”) and a second transceiver located at the local central
`telephone office (“CO transceiver”). Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:22)(cid:29)(cid:25)(cid:21)(cid:3013)(cid:25)(cid:26)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85)(cid:86)(cid:3)
`include a transmitter section for transmitting data over a digital subscriber
`line and a receiver section for receiving data from the line. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:23)(cid:29)(cid:20)(cid:23)(cid:3013)(cid:20)(cid:26)(cid:17)(cid:3)(cid:3)
`The transceivers further include a clock, controller, frame counter, and a
`state memory. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:23)(cid:29)(cid:24)(cid:27)(cid:3013)(cid:24)(cid:29)(cid:20)(cid:24)(cid:17)(cid:3)(cid:3)(cid:55)(cid:92)(cid:83)(cid:76)(cid:70)(cid:68)(cid:79)(cid:79)(cid:92)(cid:15)(cid:3)(cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:76)(cid:86)(cid:3)(cid:70)(cid:82)(cid:80)(cid:80)(cid:88)(cid:81)(cid:76)(cid:70)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:76)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)
`form of a sequence of data frames, sixty-eight frames for ADSL, followed
`by a synchronization frame. Id. The sixty-nine frames comprise a
`“superframe.” Id.
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`IPR2016-01466
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`The power down operation of the CPE transceiver begins on receipt of
`a power-down indication. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:25)(cid:29)(cid:21)(cid:26)(cid:3013)(cid:22)(cid:19)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:38)(cid:51)(cid:40)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85)(cid:3)(cid:85)(cid:72)(cid:86)(cid:83)(cid:82)(cid:81)(cid:71)(cid:86)(cid:3)(cid:87)(cid:82)(cid:3)
`the power down indication by transmitting to the CO transceiver an “Intend
`to Enter Sleep Mode” notification. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:25)(cid:29)(cid:22)(cid:28)(cid:3013)(cid:23)(cid:21)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:38)(cid:50)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85)(cid:3)
`responds by transmitting an “Acknowledge Sleep Mode” notification to the
`CPE transceiver, and the CPE transceiver transmits an “Entering Sleep
`Mode” notification to the CO transceiver. Id. at 6:52(cid:3013)(cid:25)(cid:24)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:38)(cid:50)(cid:3)
`transceiver detects the notification and transmits its own “Entering Sleep
`Mode” notification. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:25)(cid:29)(cid:25)(cid:24)(cid:3013)(cid:25)(cid:26)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:38)(cid:50)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85)(cid:3)(cid:86)(cid:87)(cid:82)(cid:85)(cid:72)(cid:86)(cid:3)(cid:76)(cid:87)(cid:86)(cid:3)(cid:86)(cid:87)(cid:68)(cid:87)(cid:72)(cid:3)(cid:76)(cid:81)(cid:3)(cid:76)(cid:87)(cid:86)(cid:3)
`own state memory corresponding to the state memory of the CPE
`transceiver. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:25)(cid:29)(cid:25)(cid:26)(cid:3013)(cid:26)(cid:29)(cid:21)(cid:17)(cid:3)(cid:3)“The CO transceiver continues to advance the
`frame count and the superframe count during the period of power-down in
`order to ensure synchrony with the remote CPE transceiver when
`communications are resumed.” Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:26)(cid:29)(cid:28)(cid:3013)(cid:20)(cid:21)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:38)(cid:50)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85)(cid:3)(cid:73)(cid:88)(cid:85)(cid:87)(cid:75)(cid:72)(cid:85)(cid:3)
`continues to monitor the subscriber line for an “Exiting Sleep Mode”
`notification, and the CPE transceiver transmits this signal when it receives
`an “Awaken” indication. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:26)(cid:29)(cid:24)(cid:26)(cid:3013)(cid:25)(cid:23)(cid:17)(cid:3)(cid:3)(cid:44)(cid:81)(cid:3)(cid:85)(cid:72)(cid:86)(cid:83)(cid:82)(cid:81)(cid:86)(cid:72)(cid:3)(cid:87)(cid:82)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:179)(cid:36)(cid:90)(cid:68)(cid:78)(cid:72)(cid:81)(cid:180)(cid:3)
`signal, CPE transceiver retrieves its stored state from state memory and
`restores full power to its circuitry. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:26)(cid:29)(cid:25)(cid:23)(cid:3013)(cid:25)(cid:25)(cid:17)(cid:3)(cid:3)(cid:38)(cid:50)(cid:3)(cid:55)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87)(cid:87)(cid:72)(cid:85)(cid:3)(cid:71)(cid:72)(cid:87)(cid:72)(cid:70)(cid:87)(cid:86)(cid:3)
`“Exit Sleep Mode” notification and restores its state and power. Id(cid:17)(cid:3)(cid:68)(cid:87)(cid:3)(cid:27)(cid:29)(cid:20)(cid:3013)(cid:23).
`
`D. Illustrative Claim
`Petitioner challenges claims 6, 10, 11, 15, 16, and 20 of the ’404
`patent. Pet. 22–58. Claims 6, 11, and 16 are independent claims. Claim 6 is
`illustrative of the claims at issue and is reproduced below:
`6.
`An apparatus comprising a transceiver operable to:
`receive, in a full power mode, a plurality of superframes,
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`IPR2016-01466
`Patent 8,611,404 B2
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`wherein the superframe comprises a plurality of data frames
`followed by a synchronization frame;
`receive, in the full power mode, a synchronization signal;
`transmit a message to enter into a low power mode;
`store, in a low power mode, at least one parameter
`associated with the full power mode operation wherein the at
`least one parameter comprises at least one of a fine gain
`parameter and a bit allocation parameter;
`receive, in the low power mode, a synchronization signal;
`
`and
`
`exit from the low power and restore the full power mode
`by using the at least one parameter and without needing to
`reinitialize the transceiver.
`Ex. 1001, 10:29–43.
`
`II. ANALYSIS
`A. Claim Construction
`We interpret claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. See 37 C.F.R. § 42.100(b); see Cuozzo Speed Techs., LLC v.
`Lee, 136 S. Ct. 2131, 2142–46 (2016). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007).
`
`1. “store/storing, in a/the low power mode”
`In our Decision on Institution, we construed “store/storing in a/the
`low power mode” to mean “maintaining in memory while in a reduced
`power consumption mode.” Inst. Dec. 6–7. Neither party addressed this
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`Patent 8,611,404 B2
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`construction in subsequent briefing. Based on the record developed during
`this proceeding, we continue to apply this construction.
`
`2. “synchronization signal”
`Each independent claim recites a “synchronization signal.” In our
`Decision on Institution, we construed this term to mean “a signal allowing
`frame synchronization between the transmitter of the signal and the receiver
`of the signal.” Inst. Dec. 5–6.
`Patent Owner argues that our construction is not consistent with the
`ordinary meaning of the claim language, and proposes to construe this term
`to mean “a signal used to maintain a timing relationship between
`transceivers by correcting errors or differences between a timing reference
`of the transmitter of the signal and a timing reference of the receiver of the
`signal.” PO Resp. 17–18. Patent Owner agrees with Petitioner’s reliance on
`the timing reference signal disclosed in the ’404 patent (id. at 19–20 (“The
`parties agree that the timing reference signal that is transmitted by the CO is
`an embodiment of the claimed synchronization signal”)), but argues that the
`timing reference signal provides for timing synchronization between two
`transceivers—i.e., to synchronize their respective clocks—not for frame
`synchronization—i.e., to detect the boundaries of the transmitted superframe
`(id. at 18). According to Patent Owner, Petitioner’s reliance on lines 50 to
`52 of column 5 of the ’404 patent is misplaced because that passage
`describes synchronizing the timing of the transceivers’ respective frame
`counters—i.e., timing synchronization—not detecting superframe
`boundaries—i.e., frame synchronization. Id. at 19. Patent Owner also
`argues that the recited “synchronization signal” cannot encompass frame
`synchronization because the claims separately recite a “synchronization
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`frame,” which provides frame synchronization. Id. at 18. Finally, Patent
`Owner argues that its proposed construction is correct because a
`“synchronization signal” is used to maintain timing synchronization by
`correcting or compensating for errors or differences between the timing
`references of the transmitter of the signal and the receiver of the signal. Id.
`at 20–21.
`Petitioner, in its Reply, argues that “synchronization signal” should
`encompass both frame synchronization and timing synchronization. Pet.
`Reply 5–6. Petitioner argues that the construction proposed in Patent
`Owner’s Response is not the broadest reasonable interpretation because “it
`was proposed specifically in response to the analysis in Dr. Kiaei’s
`declaration” and because “it relies on a dictionary definition of a different
`term and fails to refer to anything in the specification.” Id. at 7.
`Having considered the arguments and evidence, we agree with Patent
`Owner that our construction in the Decision to Institute is overly broad to the
`extent it encompasses a synchronization frame. Column 5, lines 50 to 52 of
`the ’404 patent, on which we relied and which we reproduce below for
`context, describes “normal (non-sleep mode) operation”:
`During normal (non-sleep mode) operation, a phase-lock loop
`(PLL) 62 receives from the FFT 56 a timing reference signal 62a
`(see FIG. 1A) via a line 62b. The timing reference signal 62a is
`transmitted from the transmitter with which the receiver 16
`communicates (e.g., the CO transmitter). This signal is
`advantageously a pure tone of fixed frequency and phase which
`is synchronized with the Master Clock in the transmitter; its
`frequency defines the frame rate of the transceivers. Other forms
`of timing signal may, of course, be used, but use of a pure tone
`has the advantage of simplicity and reliability even when
`portions of the transceiver are powered down in accordance with
`the invention. The PLL 62 locks itself to this signal and drives
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`clock 30 in synchronism with the Master Clock in the driving
`transmitter. This also synchronizes frame counter 34 of the CPE
`transceiver to the corresponding frame counter of the CO
`transceiver. Control of the receiver section is provided by the
`controller 32.
`Ex. 1001, 5:37–53 (emphasis added to 5:50–52). We agree with Patent
`Owner that the italicized “this” refers to what is disclosed in the preceding
`sentence—i.e., driving clock 30 in synchronism with the Master Clock in the
`driving transmitter. PO Resp. 19. The synchronism of clock 30 with the
`Master Clock in the driving transmitter is what “synchronizes frame counter
`34 of the CPE transceiver to the corresponding frame counter of the CO
`transceiver.” Ex. 1001, 5:50–52.
`We also agree with Patent Owner that a “synchronization signal”
`should not be construed to encompass a synchronization frame because the
`claims separately recite a “synchronization frame.” Claim 6, for example,
`recites:
`
`receive, in a full power mode, a plurality of superframes,
`wherein the superframe comprises a plurality of data frames
`followed by a synchronization frame;
`receive, in the full power mode, a synchronization signal;
`Ex. 1001, 10:30–33 (emphases added). If we were to construe
`“synchronization signal” to encompass a synchronization frame, the step of
`“receive, in the full power mode, a synchronization signal” would be
`duplicative because a synchronization frame would have been received, in
`full power mode, when “receiv[ing], in full power mode, a plurality of
`superframes.” Id. “A claim construction that gives meaning to all the terms
`of the claim is preferred over one that does not do so.” Merck & Co. v. Teva
`Pharms. USA, Inc., 395 F.3d 1364, 1372 (Fed. Circ. 2005).
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`
`Notwithstanding our agreement with Patent Owner that
`“synchronization signal” should not encompass a synchronization frame, we
`are not persuaded that Patent Owner’s proposed construction is correct
`because it also is overly broad. Whereas our preliminary construction
`required “allowing frame synchronization between the transmitter of the
`signal and the receiver of the signal,” Patent Owner’s proposed construction
`replaces that with the more general “used to maintain a timing relationship
`between transceivers.” PO Resp. 17. Patent Owner does not attempt to find
`support in the ’404 patent for “timing relationship,” relying instead upon the
`testimony of its declarant. Id. at 17–18 (citing Ex. 2005 ¶ 81). Moreover,
`“timing relationship” is arguably broad enough to encompass the timing of
`superframe boundaries and, therefore, encompass the very frame
`synchronization that Patent Owner tries to distinguish. Patent Owner
`proposes to limit the way in which the timing relationship is maintained to
`“by correcting errors or differences between a timing reference of the
`transmitter of the signal and a timing reference of the receiver of the signal,”
`(id.), but Patent Owner again relies not upon the Specification for that
`language, but upon a dictionary definition. Because portions of Patent
`Owner’s proposed construction lack support in the Specification and would
`encompass the very synchronization frame that we are persuaded should be
`excluded, we determine that Patent Owner’s proposed construction also is
`overly broad.
`Because both parties agree that timing reference signal 62a
`corresponds to the recited “synchronization signal” and because the only
`purpose disclosed for timing reference signal 62a is being used by PLL 62 to
`“drive[] clock 30 in synchronism with the Master Clock in the driving
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`transmitter,” we determine that “synchronization signal” means “a signal
`allowing synchronization between the clock of the transmitter of the signal
`and the clock of the receiver of the signal.”
`
`3. “parameter associated with
`the full power mode operation”
`Patent Owner proposes construing this term to mean “parameter
`associated with the transmission and/or reception of data during normal
`operation.” PO Resp. 21. The ’404 patent describes storing a list of
`parameters comprising the “state” of transceiver. Ex. 1001, 6:67–7:9.
`Patent Owner argues that this list “includes only communication protocol-
`specific parameters that are used for the transmission and/or reception of
`data – it does not include loop characteristics.” PO Resp. 22.
`Petitioner counters that the term should have its ordinary and
`customary meaning. Pet. Reply 8. Petitioner also argues that the rest of the
`limitation—reciting “a fine gain parameter and a bit allocation parameter”—
`provide sufficient meaning. Id.
`Having considered the arguments and evidence, we are not persuaded
`that this term requires an express construction. Patent Owner’s proposed
`construction merely replaces “full power mode operation” with
`“transmission and/or reception of data during normal operation.” The
`parties, however, do not dispute the meaning of “full power mode
`operation.” As a result, an express construction of this term is not necessary
`in order to resolve the parties’ dispute.
`
`B. Level of Ordinary Skill in the Art
`Petitioner contends that a hypothetical person of ordinary skill in the
`art, with respect to and at the time of the’404 patent, “would have (i) a
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`Master’s degree in Electrical and/or Computer Engineering, or equivalent
`training, and (ii) approximately five years of experience working in digital
`telecommunications.” Pet. 13.
`Patent Owner contends that such a person would have had “a
`bachelor’s degree in electrical engineering (or a similar technical degree or
`equivalent work experience) and at least 3 years of experience working with
`such multicarrier communication systems.” PO Resp. 17.
`We determine that no express finding on a specific corresponding
`level of technical education and experience is necessary. Here, the level of
`ordinary skill in the art is reflected by the prior art of record. See Okajima v.
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re GPAC Inc., 57 F.3d
`1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579 F.2d 86, 91 (CCPA 1978).
`
`C. Obviousness over Bowie, Yamano, and ANSI T1.413
`Petitioner contends that claims 6, 10, 11, 15, 16, and 20 of the ’404
`patent are unpatentable under 35 U.S.C. § 103(a) as obvious over Bowie,
`Yamano, and ANSI T1.413. Pet. 13–61.
`
`1. Principles of Law
`A claim is unpatentable under § 103(a) if the differences between the
`claimed subject matter and the prior art are such that the subject matter, as a
`whole, would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains.
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
`obviousness is resolved on the basis of underlying factual determinations,
`including (1) the scope and content of the prior art; (2) any differences
`between the claimed subject matter and the prior art; (3) the level of skill in
`the art; and (4) when in evidence, objective indicia of non-obviousness
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`(i.e., secondary considerations). Graham v. John Deere Co., 383 U.S. 1, 17–
`18 (1966). We analyze this asserted ground based on obviousness with the
`principles identified above in mind.
`
`2. Bowie Overview
`Bowie discloses a power conservation system for transmission
`systems in which data is modulated over a communications loop from a
`central office location to a customer (cid:83)(cid:85)(cid:72)(cid:80)(cid:76)(cid:86)(cid:72)(cid:17)(cid:3)(cid:3)(cid:40)(cid:91)(cid:17)(cid:3)(cid:20)(cid:19)(cid:19)(cid:24)(cid:15)(cid:3)(cid:20)(cid:29)(cid:23)(cid:3013)(cid:27)(cid:17)(cid:3)(cid:3)(cid:37)(cid:82)(cid:90)(cid:76)(cid:72)(cid:3)
`discloses that to provision ADSL service, ADSL units are located at each
`end of a wire loop, a first ADSL unit at the customer premises (CPE) and a
`second ADSL unit at the telephone company central office (COT). Id. at
`3:(cid:24)(cid:20)(cid:3013)(cid:24)(cid:27)(cid:17)(cid:3)(cid:3)(cid:39)(cid:68)(cid:87)(cid:68)(cid:3)(cid:76)(cid:86)(cid:3)(cid:68)(cid:85)(cid:85)(cid:68)(cid:81)(cid:74)(cid:72)(cid:71)(cid:3)(cid:76)(cid:81)(cid:3)(cid:68)(cid:3)(cid:86)(cid:87)(cid:85)(cid:88)(cid:70)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:78)(cid:81)(cid:82)(cid:90)(cid:81)(cid:3)(cid:68)(cid:86)(cid:3)(cid:68)(cid:3)(cid:179)(cid:73)(cid:85)(cid:68)(cid:80)(cid:72)(cid:180)(cid:3)(cid:83)(cid:85)(cid:76)(cid:82)(cid:85)(cid:3)(cid:87)(cid:82)(cid:3)
`transmission. Id. (cid:68)(cid:87)(cid:3)(cid:22)(cid:29)(cid:25)(cid:25)(cid:3013)(cid:25)(cid:26)(cid:17)(cid:3)(cid:3)
`ADSL units enter a low power mode to reduce power requirements.
`Id. (cid:68)(cid:87)(cid:3)(cid:24)(cid:29)(cid:25)(cid:3013)(cid:27)(cid:17)(cid:3)(cid:3)(cid:38)(cid:51)(cid:40)(cid:3)(cid:88)(cid:81)(cid:76)(cid:87)(cid:3)(cid:76)(cid:81)(cid:76)(cid:87)(cid:76)(cid:68)(cid:87)(cid:72)(cid:86)(cid:3)(cid:79)(cid:82)(cid:90)(cid:3)(cid:83)(cid:82)(cid:90)(cid:72)(cid:85)(cid:3)(cid:80)(cid:82)(cid:71)(cid:72)(cid:3)(cid:69)(cid:92)(cid:3)(cid:86)(cid:72)(cid:81)(cid:71)(cid:76)(cid:81)(cid:74)(cid:3)(cid:68)(cid:3)(cid:179)(cid:86)(cid:75)(cid:88)(cid:87)-down”
`signal to the COT unit. Id. (cid:68)(cid:87)(cid:3)(cid:24)(cid:29)(cid:27)(cid:3013)(cid:20)(cid:19)(cid:17)(cid:3)(cid:3)(cid:37)(cid:82)(cid:87)(cid:75)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:38)(cid:51)(cid:40)(cid:3)(cid:88)(cid:81)(cid:76)(cid:87)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:38)(cid:50)(cid:55)(cid:3)(cid:88)(cid:81)(cid:76)(cid:87)(cid:3)(cid:80)(cid:68)(cid:92)(cid:3)
`store loop characteristics that enable rapid resumption of user data
`transmission when units return to full power mode. Id. at 5:17(cid:3013)(cid:21)(cid:24)(cid:17)(cid:3)(cid:3)(cid:40)(cid:68)(cid:70)(cid:75)(cid:3)
`unit then enters low power mode by shutting off the now unnecessary
`sections of the signal processing, transmitting, and receiving circuitry. Id. at
`(cid:24)(cid:29)(cid:21)(cid:25)(cid:3013)(cid:21)(cid:27)(cid:17)(cid:3)(cid:3)(cid:36)(cid:73)(cid:87)(cid:72)(cid:85)(cid:3)(cid:86)(cid:75)(cid:88)(cid:87)(cid:71)(cid:82)(cid:90)(cid:81)(cid:15)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:79)(cid:82)(cid:82)(cid:83)(cid:3)(cid:76)(cid:86)(cid:3)(cid:76)(cid:81)(cid:3)(cid:68)(cid:81)(cid:3)(cid:76)(cid:81)(cid:68)(cid:70)(cid:87)(cid:76)(cid:89)(cid:72)(cid:3)(cid:86)(cid:87)(cid:68)(cid:87)(cid:72)(cid:17)(cid:3)(cid:3)Id. at 5:28(cid:3013)(cid:21)(cid:28)(cid:17)(cid:3)(cid:3)
`The units return to full power mode after the CPE unit transmits to the
`COT unit a resume signal. Id. (cid:68)(cid:87)(cid:3)(cid:24)(cid:29)(cid:23)(cid:27)(cid:3013)(cid:24)(cid:28)(cid:17)(cid:3)(cid:3)(cid:55)(cid:75)(cid:72)(cid:3)(cid:86)(cid:87)(cid:82)(cid:85)(cid:72)(cid:71)(cid:3)(cid:79)(cid:82)(cid:82)(cid:83)(cid:3)(cid:70)(cid:75)(cid:68)(cid:85)(cid:68)(cid:70)(cid:87)(cid:72)(cid:85)(cid:76)(cid:86)(cid:87)(cid:76)(cid:70)(cid:86)(cid:3)
`are used to restore the loop parameters. Id. (cid:68)(cid:87)(cid:3)(cid:24)(cid:29)(cid:25)(cid:19)(cid:3013)(cid:25)(cid:25)(cid:17)(cid:3)(cid:3)
`
`3. Yamano Overview
`Yamano discloses a method for the reduction of the required amount
`of signal processing in a modulator and demodulator transferring packet-
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`(cid:69)(cid:68)(cid:86)(cid:72)(cid:71)(cid:3)(cid:71)(cid:68)(cid:87)(cid:68)(cid:17)(cid:3)(cid:3)(cid:40)(cid:91)(cid:17)(cid:3)(cid:20)(cid:19)(cid:19)(cid:25)(cid:15)(cid:3)(cid:20)(cid:29)(cid:28)(cid:3013)(cid:20)(cid:22)(cid:17)(cid:3)(cid:3)(cid:60)(cid:68)(cid:80)(cid:68)(cid:81)(cid:82)(cid:3)(cid:71)(cid:76)(cid:86)(cid:70)(cid:79)(cid:82)(cid:86)(cid:72)(cid:86)(cid:3)(cid:68)(cid:81)(cid:3)(cid:72)(cid:80)(cid:69)(cid:82)(cid:71)(cid:76)(cid:80)(cid:72)(cid:81)(cid:87)(cid:3)(cid:90)(cid:75)(cid:72)(cid:85)(cid:72)(cid:3)(cid:68)(cid:3)
`transmitter circuit transmits a predetermined non-idle state signal to indicate
`that packet data is about to be transmitted prior to the transmission of packet
`data. Id. (cid:68)(cid:87)(cid:3)(cid:20)(cid:22)(cid:29)(cid:24)(cid:25)(cid:3013)(cid:24)(cid:28)(cid:17)(cid:3)(cid:3)(cid:44)(cid:73)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:81)(cid:82)(cid:81)-idle state signal is not transmitted, the
`transmitter does not transmit any signals on the communication channel,
`and, therefore, the transmitter does not transmit any idle information. Id. at
`(cid:20)(cid:22)(cid:29)(cid:24)(cid:28)(cid:3013)(cid:25)(cid:22)(cid:17)(cid:3)(cid:3)(cid:56)(cid:83)(cid:82)(cid:81)(cid:3)(cid:71)(cid:72)(cid:87)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:82)(cid:73)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:83)(cid:85)(cid:72)(cid:71)(cid:72)(cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:72)(cid:71)(cid:3)(cid:81)(cid:82)(cid:81)-idle state signal, the
`receiver enters full processing mode and performs full demodulation of the
`incoming signal. Id. (cid:68)(cid:87)(cid:3)(cid:20)(cid:23)(cid:29)(cid:21)(cid:24)(cid:3013)(cid:21)(cid:28)(cid:17)(cid:3)(cid:3)(cid:36)(cid:73)(cid:87)(cid:72)(cid:85)(cid:3)(cid:87)(cid:75)e packet data has been received,
`the receiver detects the absence of the predetermined non-idle state signal
`and the receiver enters a reduced processing mode by disabling several
`components of the receiver. Id. (cid:68)(cid:87)(cid:3)(cid:20)(cid:23)(cid:29)(cid:21)(cid:28)(cid:3013)(cid:23)(cid:21)(cid:17)
`
`4. ANSI T1.413 Overview
`ANSI T1.413 discloses electrical characteristics of Asymmetric
`Digital Subscriber Line (ADSL) signals appearing at a network interface.
`Ex. 1007, Abstract. ADSL allows for the provision of Plain Old Telephone
`Service (POTS) and a variety of digital channels. Id. at 1. Digital channels
`consist of full duplex low-speed channels and simplex high-speed channels
`in the direction from the network to the customer premises, and low-speed
`channels in the opposite direction. Id.
`
`5. Analysis
`Petitioner contends that a combination of Bowie, Yamano, and ANSI
`T1.413 would have rendered obvious claims 6, 10, 11, 15, 16, and 20 of t