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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`CISCO SYSTEMS, INC.,
`Petitioner
`
`v.
`
`TQ DELTA LLC,
`Patent Owner
`
`_____________________
`
`
`
`
`SECOND DECLARATION OF DR. SAYFE KIAEI
`UNDER 37 C.F.R. § 1.68 IN SUPPORT OF PETITIONER’S REPLIES
`IN IPR2016-01466 AND IPR2016-01760
`
`
`1
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`
`
`I.
`
`II.
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`Table of Contents
`
`
`
`
`
`Introduction .................................................................................................... 3
`
`Claim Construction ......................................................................................... 3
`
`A.
`
`“maintaining synchronization with a second transceiver” /
`“synchronization signal” ...................................................................... 3
`
`1.
`
`2.
`
`Dr. Chrissan’s constructions are not the broadest
`reasonable. .................................................................................3
`
`The specification discloses both frame synchronization and
`timing synchronization. .............................................................5
`
`B.
`
`“parameter(s) associated with the full power mode operation” ........... 6
`
`III. Analysis .......................................................................................................... 7
`
`A.
`
`B.
`
`C.
`
`The combination of Bowie and Yamano renders obvious “a
`transmitter portion of the transceiver [that] does not transmit data
`during the low power mode” ................................................................ 7
`
`Yamano’s poll or other timing signal is a synchronization signal
`that maintains synchronization between the transceivers during
`low power mode. .................................................................................. 9
`
`Bowie and Yamano are both capable of receiving a
`synchronization signal in low power mode. ....................................... 11
`
`D. Yamano’s burst mode protocol is compatible with the ADSL
`standard .............................................................................................. 12
`
`IV. Conclusion .................................................................................................... 13
`
`
`
`
`
`
`
`
`2
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`INTRODUCTION
`
`
`
`
`
`
`
`I.
`
`I, Sayfe Kiaei, do hereby declare as follows:
`
`1.
`
`I previously submitted different Declarations as Exhibit 1003 in each
`
`of IPR2016-01466 and IPR2016-01760, setting forth my background and
`
`credentials and my curriculum vitae which provides further details.
`
`2.
`
`I submit this Declaration in reply to the Declaration of Douglas
`
`Chrissan, PhD, filed as Ex.2005 in IPR2016-01466 and Ex.2005 in IPR2016-
`
`01760, and the Board’s Institution Decisions in each case.
`
`II. CLAIM CONSTRUCTION
`
`A.
`
`“maintaining synchronization with a second transceiver” /
`“synchronization signal”
`
`1.
`
`Dr. Chrissan’s constructions are not the broadest
`reasonable.
`
`3.
`
`I understand Dr. Chrissan to have provided substantially similar
`
`constructions for these terms in IPR2016-01760 pertaining to U.S. Patent No.
`
`9,094,268 (“the ‘268 patent”) and IPR2016-01466 pertaining to U.S. Patent No.
`
`8,611,404 (“the ‘404 patent”). I understand that the ‘268 and ‘404 patents are part
`
`of the same patent family and share the substantially same specification.
`
`4.
`
`Dr. Chrissan concluded that the term “maintaining synchronization
`
`with a second transceiver” as defined by the specification of the ‘268 patent is
`
`“maintaining a timing relationship between two transceivers by correcting errors
`
`
`
`
`3
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`or differences in the timing of the timing reference of the transceiver and a timing
`
`
`
`
`
`
`
`reference of a second transceiver.” IPR2016-01760, Ex.2005, ¶83. Similarly, Dr.
`
`Chrissan concluded that the term “synchronization signal” as defined by the
`
`specification of the ‘404 patent is “a signal used to maintain a timing relationship
`
`between transceivers by correcting errors or differences between a timing
`
`reference of the transmitter of the signal and a timing reference of the receiver of
`
`the signal.” IPR2016-01466, Ex.2005, ¶81. A person of ordinary skill in the art
`
`(“POSITA”) would not understand either of these constructions to be the broadest
`
`reasonable in light of the specification.
`
`5.
`
`The claims at issue never limit synchronization to any specific type
`
`and much less do they require correcting errors or differences in the timing
`
`between transceivers. Although the patents at issue disclose using “a pure tone of
`
`fixed frequency and phase which is synchronized with the Master Clock in the
`
`transmitter,” they broadly recognize that “[o]ther forms of timing signal may, of
`
`course, be used” for synchronization. Ex.1001, 5:47-50. Since the specification
`
`encompasses other forms of timing signals for synchronization and not just a pure
`
`tone, a POSITA would have understood that the claims are not limited to
`
`correcting errors or differences in the timing references of the transmitter and
`
`receiver, as Dr. Chrissan states.
`
`
`
`
`4
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`Accordingly, it is my opinion that Dr. Chrissan’s proposed
`
`
`
`
`
`
`
`6.
`
`interpretation is not the broadest reasonable in light of the specification. As I have
`
`previously stated in my prior declarations, a POSITA would understand that the
`
`broadest reasonable interpretation for these terms includes “maintaining a timing
`
`relationship between transceivers.” IPR2016-01466, Ex. 1003, ¶56.
`
`2.
`
`The specification discloses both frame synchronization and
`timing synchronization.
`
`7.
`
`I agree with Dr. Chrissan that the patent specifications discloses both
`
`frame synchronization and timing synchronization. See IPR2016-01760, Ex.2005,
`
`¶81; IPR2016-01466, Ex.2005, ¶82. Frame synchronization is performed in full
`
`power mode when a transceiver “receives … a plurality of superframes” that
`
`comprise “a plurality of data frames followed by a synchronization frame.”
`
`IPR2016-01466, Ex.1001, 10:30-32. Frame synchronization also provides for
`
`timing synchronization. IPR2016-01760, Ex.2008, 62; IPR2016-01466, Ex.1007,
`
`62 (sections 6.9.1.2 & 6.9.3). Timing synchronization, however, can be performed
`
`in either full power mode or low power mode by reception of a “synchronization
`
`signal.” See IPR2016-01466, Ex.1001, 10:33, 39-40. Consequently, the
`
`construction of “synchronization signal” in the claims must be broad enough to
`
`include timing synchronization rather than just frame synchronization.
`
`
`
`
`5
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`“parameter(s) associated with the full power mode operation”
`
`
`
`
`
`I understand Dr. Chrissan to have concluded that this term in both of
`
`
`
`B.
`
`8.
`
`the ‘268 patent and ‘404 patent means “parameter associated with the transmission
`
`and/or reception of data during normal operation.” IPR2016-01760, Ex.2005, ¶87;
`
`IPR2016-01466, Ex.2005, ¶87. I disagree with these constructions.
`
`9.
`
`In my opinion, Dr. Chrissan’s proposed interpretation improperly
`
`excludes other parameters that a POSITA at the time would have understood that
`
`are associated with full power mode operation in the patents at issue. For example,
`
`the specifications provide for measuring line parameters, including signal to noise
`
`ratio (“SNR”), and deriving bits and gains from these measured parameters during
`
`full power mode. Ex.1001, 2:17-24. Dr. Chrissan agrees with me on this point
`
`since he notes that “(“Signal to noise ratio (‘SNR’) is a function of, inter alia, loop
`
`characteristics (e.g., line noise levels and line attenuation), and is used to determine
`
`transmission parameters that are used for transmission of data.” IPR2016-01760,
`
`Ex.2005, ¶30; IPR2016-01466, Ex.2005, ¶66. That SNR and attenuation are
`
`measured and used during full power mode is also evidenced by the ANSI T1.413
`
`standard. See, e.g., IPR2016-01760, Ex.2008, 82, 110; IPR2016-01466, Ex.1007,
`
`82, 110. Therefore, it is my opinion that a POSITA would have understood that in
`
`the context of the patents at issue, the parameters associated with full power mode
`
`not only include parameters used for transmission and reception of data (e.g., bits,
`
`
`
`
`6
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`gains, and equalizer values) but also include parameters from which the
`
`
`
`
`
`
`
`transmission and reception parameters are derived (e.g., attenuation, SNR).
`
`10.
`
`It is thus my opinion that Dr. Chrissan’s interpretation is not the
`
`broadest reasonable because it excludes parameters (e.g., SNR and attenuation)
`
`that are clearly associated with the full power mode operation of the patents at
`
`issue. Instead, a POSITA would find that this term does not need construction and
`
`the plain and ordinary meaning should be applied.
`
`III. ANALYSIS
`
`A. The combination of Bowie and Yamano renders obvious “a
`transmitter portion of the transceiver [that] does not transmit
`data during the low power mode”
`
`11.
`
`I understand that Dr. Chrissan concludes that the prior art does not
`
`teach a transmitter that does not transmit data in low power mode. IPR2016-
`
`01760, Ex.2005, ¶89-94. I disagree.
`
`12. First, as I discussed in my first declaration, Bowie’s transmitter
`
`teaches entering low power mode and not transmitting data upon receiving a
`
`signal. IPR2016-01760, Ex.1003, p.39-40; Ex.1005, 5:17-28. Dr. Chrissan does not
`
`dispute this teaching. Therefore, Bowie teaches entering low power mode and not
`
`transmitting data; and, in the combination this occurs while the receiver is
`
`receiving data.
`
`
`
`
`7
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`13. Second, I have also previously explained that Yamano enters low
`
`
`
`
`
`power mode since it utilizes a burst mode where “transmitter circuit only sends
`
`information when there is meaningful packet data available to be sent” and
`
`otherwise “the transmitter circuit does not transmit any signals on the
`
`communication channel.” IPR2016-01760, Ex.1003, p.43; Ex.1006, 13:56-65.
`
`When compared to normal operation (which transmits data regardless if it is
`
`meaning full or not), the burst mode represents significant power savings since no
`
`power is used to transmit data on the loop. Dr. Chrissan agrees with me on this
`
`point and acknowledges that the “burst mode protocol described in Yamano …
`
`conserve[s] power by not communicating idle information.” IPR2016-01760,
`
`Ex.2005, ¶116.
`
`14. Also, as I explained in my first declaration, Yamano discloses that the
`
`“echo canceler 309 can be disabled when the local transmitter circuit is not
`
`transmitting.” Ex.1003, p.43; Ex.1006, 13:56:65. A POSITA would have
`
`understood that the echo canceler in Yamano’s transceiver, which is interposed
`
`between both the transmitter and receiver, is part of both circuits. Ex.1006, FIGs.
`
`1-4. Accordingly, Yamano’s disabling of the echo canceller (which is part of both
`
`the receiver and transmitter circuit) further demonstrates what Yamano already
`
`teaches—that Yamano’s transmitter operates in a reduced power mode when not
`
`transmitting.
`
`
`
`
`8
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`B. Yamano’s poll or other timing signal is a synchronization signal
`that maintains synchronization between the transceivers during
`low power mode.
`
`
`
`
`
`15.
`
`I understand that Dr. Chrissan concludes that Yamano’s poll or timing
`
`signal is not a “synchronization signal” and “does not ‘maintain[] synchronization
`
`with a second transceiver during the low power mode.’” IPR2016-01760, Ex.2005,
`
`¶98; IPR2016-01466, Ex.2005, ¶112. I disagree.
`
`16. First, as discussed above, under the proper construction, the term
`
`“maintaining synchronization” includes “maintaining a timing relationship
`
`between transceivers” and the term “synchronization symbol” includes “a signal
`
`used to maintain timing between transceivers.” As I explained in my first
`
`declaration, Yamano expressly discloses using a “poll or other timing signal … to
`
`maintain synchronization of these time intervals between receiver circuit 400 and
`
`the remote transmitter circuit.” IPR2016-01760, Ex.1003, p.48-49; IPR2016-
`
`01466, Ex.1003, p.56; Ex.1006, 15:29-32. Therefore, under the correct
`
`construction, Yamano teaches this limitation.
`
`17. Second, even if Dr. Chrissan’s construction of “maintaining a timing
`
`relationship between two transceivers by correcting errors or differences in the
`
`timing of the timing reference of the transceiver and the timing reference of a
`
`second transceiver” is adopted, Yamano teaches it. Yamano’s timing signal is
`
`“used to maintain synchronization of [] time intervals” between receiver and
`
`
`
`
`9
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`transmitter circuits. Ex.1006, 15:29-32. And, as shown in the ANSI specification, a
`
`
`
`
`
`
`
`POSITA knew that a purpose of maintaining synchronization is to correct errors or
`
`differences that may periodically exist between transceivers. IPR2016-01466,
`
`Ex.1007, 62 (section 6.9.1.2); IPR2016-01760, Ex.2008, 62 (section 6.9.1.2). Thus,
`
`even if the claims are construed to incorporate Dr. Chrissan’s extra limitations,
`
`Yamano’s timing signal satisfies these in that it uses a timing signal to maintain
`
`synchronization by correcting timing errors to avoid re-initialization.
`
`18. Third, Yamano teaches a “synchronization signal” under the Board
`
`construction of “a signal allowing frame synchronization between the transmitter
`
`of the signal and the receiver of the signal.” IPR2016-01466, Institution Decision,
`
`6, 13-14. In fact, a POSITA knew that a purpose of the timing signal in Yamano is
`
`to “maintain synchronization of [] time intervals between receiver circuit 400 and
`
`the remote transmitter circuit.” Ex.1006, 15:29-32. Maintaining synchronization of
`
`the transmitter and receiver via this timing signal allows Yamano’s non-idle
`
`detector to wake periodically to detect “the presence of packet data” or, in other
`
`words, the beginning of a superframe boundary. Ex.1006, 14:20-23. Because
`
`Yamano’s timing signal is used in this way, it satisfies the “synchronization signal”
`
`under the Board’s construction.
`
`
`
`
`10
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`C. Bowie and Yamano are both capable of receiving a
`synchronization signal in low power mode.
`
`
`
`
`
`19.
`
`I note that Bowie teaches that part of its circuitry “must remain
`
`capable of signal detection during low power operation.” Ex.1005, 5:28-31. In
`
`view of the prior art teachings and the knowledge at that time, a POSITA would
`
`have understood that this part of the circuitry may also be used to detect a
`
`synchronization signal, while maintaining the transceiver in low power mode.
`
`20. Similarly, Yamano teaches that its receiver includes non-idle detector
`
`401 that is periodically enabled to detect a timing signal while the other
`
`components remain in low power mode. For example, Yamano states that
`
`“receiver circuit 400 can periodically enable the non-idle detector 401 during
`
`predetermined time intervals which can be used by the remote transmitter circuit to
`
`signal the transmission of a packet. A periodic poll or some other timing signal
`
`would be used to maintain synchronization of these time intervals between receiver
`
`circuit 400 and the remote transmitter circuit.” Ex.1006, 15:26-29. Thus, a
`
`POSITA would understand that Yamano’s non-idle detector 401 is active, at least
`
`periodically, in order to receive a timing signal to maintain synchronization while
`
`the receiver is in low power mode.
`
`21. Since Bowie teaches that part of its circuitry “must remain capable of
`
`signal detection during low power operation” in order to detect a resume signal
`
`
`
`
`11
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`(Ex.1005, 28-30), modifying this circuitry to also detect a timing signal, as taught
`
`
`
`
`
`
`
`in Yamano, would be well within the level of a POSITA since Yamano teaches
`
`similar circuitry (i.e., non-idle detector 401) that also functions in low power mode
`
`to also detect a resume signal.
`
`D. Yamano’s burst mode protocol is compatible with the ADSL
`standard
`
`22.
`
`It is my opinion that Yamano is compatible with the ADSL standard
`
`(i.e., ANSI T1.413) despite not specifically mentioning superframes. For example,
`
`Yamano teaches that its modem transmits and receives data via “an analog signal
`
`in accordance with a conventional modem protocol, such as xDSL.” Ex.1006,
`
`7:18-20. The ANSI specification, which discloses a conventional ADSL protocol,
`
`is just one of the variants of xDSL systems contemplated in Yamano. See
`
`IPR2016-01466, Ex.1003, p.35, 37.
`
`23. Additionally, even if Yamano’s burst-mode protocol does not result in
`
`a continuous stream of superframes, a POSITA would still find Yamano and the
`
`ANSI standard compatible. This is because the ANSI standard describes
`
`requirements for sending data in full power mode but also specifically allows for
`
`improvements (e.g., low power mode as in Bowie and Yamano)—“[t]his interface
`
`standard provides the minimal set of requirements for satisfactory transmission
`
`between the network and the customer installation. Equipment may be
`
`
`
`
`12
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
`
`Declaration of Dr. Sayfe Kiaei under 37 C.F.R. § 1.68 in Support of
`Petitioner Replies in IPR2016-01466 and IPR2016-01760
`implemented with additional functions and procedures.” Ex.1007, 2. Thus, a
`
`
`
`
`
`
`
`POSITA would understand Yamano’s burst mode to be compatible with the ANSI
`
`standard because low power mode operation is just an additional function that the
`
`standard permits.
`
`24. Further, as discussed above, Yamano’s burst mode uses the same
`
`method of transmitting data as other ADSL modems, i.e., “an analog signal in
`
`accordance with a conventional modem protocol, such as xDSL.” Ex.1006, 7:18-
`
`20. Thus, since Yamano’s burst mode can use the ADSL protocol to transmit data
`
`between modems using an analog signal, a POSITA would find Yamano and the
`
`ANSI specification combinable for this additional reason.
`
`IV. CONCLUSION
`
`25.
`
`I hereby declare under penalty of perjury under the laws of the United
`
`States of America that the foregoing is true and correct, and that all statements
`
`made of my own knowledge are true and that all statements made on information
`
`and belief are believed to be true. I understand that willful false statements are
`
`punishable by fine or imprisonment or both. See 18 U.S.C. § 1001.
`
`Respectfully Submitted,
`
`Aug 23, 2017 Sayfe Kiaei
`
`
`
`
`
`
`13
`
`Ex. 1012
`
`Cisco Systems v. TQ Delta, IPR2016-01466
`
`
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