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`EXPERT DECLARATION OF DOUGLAS A. CHRISSAN, Ph.D.
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`Case No. IPR2016-01160
`Patent No. 8,611,404
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01160
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`I.
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`INTRODUCTION & SUMMARY OF OPINIONS
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` My name is Douglas A. Chrissan. I have been engaged by TQ Delta,
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`LLC in connection with IPR number 2016-01160, which relates to U.S. Pat. No.
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`8,611,404 (“the ’404 patent”). In this declaration I provide my opinion that the
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`challenged claims of the ’404 patent would not have been obvious in view of the
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`references and grounds asserted by the Petitioner Arris Group, Inc. (“Arris” or
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`“Petitioner”).
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`II.
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`PROFESSIONAL QUALIFICATIONS
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`A. Background and Experience
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`2.
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`I am presently a technical consultant in the areas of communications
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`systems, multimedia systems, computer systems, and digital signal processing.
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`3.
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`I earned a B.S. and M.S. in Electrical Engineering from the University
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`of Southern California in 1988 and 1990, respectively, and a Ph.D. in Electrical
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`Engineering from Stanford University in 1998.
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`4.
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`5.
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`A copy of my current CV is attached as Ex. 2004.
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`I was a Masters Fellow and Member of the Technical Staff at Hughes
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`Aircraft Company in El Segundo, California, from 1988–1993. While at Hughes
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`Aircraft, I designed and developed communication systems for commercial and
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`military spacecraft, including for the MILSTAR satellite program.
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`6.
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`Between 1992 and 1993, while at Hughes Aircraft Company, I
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`designed and built a
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`state-of-the-art, 800 megabit-per-second
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`(Mbps)
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`telecommunications modem for the NASA Lewis Research Center.
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`7.
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`From 1997–2003, I worked at 8x8, Inc., starting as a DSP software
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`engineer in 1997, becoming a manager in 1998, a director in 1999, and Vice
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`President of Engineering in 2000 (managing a team of approximately 60 engineers
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`in the company’s microelectronics group). I played a key role in developing
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`several
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`semiconductor products used worldwide
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`in multimedia
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`and
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`communications devices, mainly for video conferencing systems and Internet
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`Protocol (“IP”) telephones. Some of these semiconductor products were in
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`production more than ten years.
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`8.
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`From 2003–2007, I was a Systems Architect and Engineering
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`Program Manager at Texas Instruments in the Digital Subscriber Line (“DSL”)
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`product business unit. At Texas Instruments, I was directly involved in the
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`architecture, design, development and production of multicarrier DSL modem
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`products. My work specifically included architecting a multicarrier DSL
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`semiconductor and software product and managing all aspects of its development
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`from inception to production.
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`Declaration of Douglas A. Chrissan, Ph.D.
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` My Ph.D. dissertation and related publications are in the fields of
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`statistical signal processing and communication systems, and more specifically in
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`the area of impulsive noise modeling for communication systems.
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`10.
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`In 1995 I was the instructor for the graduate Statistical Signal
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`Processing class (EE278) in the Electrical Engineering department at Stanford
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`University. Prior to teaching this class, I was a teaching assistant for ten different
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`classes in signal processing and radio frequency electronics at Stanford.
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`11.
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`I have developed, and managed the development of, several
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`successful semiconductor, software and systems products in the communications
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`and multimedia fields. These products are listed in the attached curriculum vitae.
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`B. Compensation
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`12.
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`I am being compensated for my time in this case at the rate of $250
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`per hour (plus expenses) for analysis, depositions, and, if necessary, trial
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`testimony. My compensation for this matter is not determined by or contingent on
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`the outcome of this case.
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`C. Materials Relied Upon
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`13.
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`In the course of preparing this expert declaration, I have considered
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`the ’404 Patent, its file history, the Petition and its exhibits (including the
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`Declaration of Mr. McNally), the Patent Owner’s Preliminary Response, the
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`Board’s Institution Decision, the transcript of the deposition of Lance McNally, as
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`well as any additional documents I cite or refer to in this declaration.
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`III. THE BOARD’S INSTITUTION DECISION
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`14.
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`I understand the Board granted review of the ’404 patent on the
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`ground that claims 1–20 are unpatentable over U.S. Patent No. 5,956,323
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`(“Bowie”) and U.S. Patent No. 6,247,725 (“Vanzieleghem”) in view of the
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`American National Standards Institute (ANSI) T1.413-1995 Standard, entitled
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`“Network and Customer Installation Interfaces—Asymmetric Digital Subscriber
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`Line (ADSL) Metallic Interface” (referenced herein as “ANSI T1.413” or the
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`“1995 ADSL Standard”).
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`IV. BACKGROUND
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`A. Overview of the Technology and the ’404 Patent
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` The ’404 patent claims improvements to multicarrier transceiver
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`devices used for data communication. The ’404 patent describes inventions that
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`allow a transceiver to enter a low power mode from a full power mode and to
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`rapidly exit the low power mode at some later time. The transceiver stores one or
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`more transmission and/or reception parameters associated with a full power mode
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`in the low power mode and uses the one or more parameters when exiting the low
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`power mode so that no re-initialization is required.
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`Declaration of Douglas A. Chrissan, Ph.D.
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`1.
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`Background of Multicarrier Technology
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` As explained in the ’404 patent, multicarrier transmission systems
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`provide high speed data links between communication points. See Ex. 1001 at
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`1:37–38. Digital subscriber line (“DSL”) systems are multicarrier transmission
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`systems that are used to provide high-speed data communication over the same
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`subscriber loop that provides telephone service to a subscriber. See id. at 1:37–47.1
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`The transceivers in a DSL system communicate with each other by dividing the
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`bandwidth of the communication channel connecting the subscriber and a central
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`office into separate subchannels, or carriers, each of limited bandwidth, operating
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`in parallel with each other. See id. at 1:48–55. The transceiver divides the data to
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`be communicated over the DSL link into groups of bits, allocates each group of
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`bits to a respective carrier, and modulates each group of bits onto its respective
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`carrier. See id. at 1:63–66. A transceiver that communicates data by modulating
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`data onto multiple carriers simultaneously is referred to as a multicarrier
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`transceiver.
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`1 The ’404 patent lists ADSL (asynchronous digital subscriber line) and HDSL
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`(High-Speed Digital Subscriber Line); this declaration references only ADSL, as
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`described in the 1995 ADSL Standard.
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` Before a multicarrier transceiver begins transmitting and receiving
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`data, the transceiver undergoes an initialization process. See id. at 3:7–9. There
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`are several distinct phases of initialization. Set forth below are the initialization
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`steps for a DSL transceiver.
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`2.
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`Timing Synchronization
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` As part of initialization, the transceivers exchange information to
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`synchronize their timing, including synchronizing the frequencies of their
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`respective clocks (i.e., “timing synchronization”). In the context of DSL systems
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`timing synchronization is accomplished as follows: one transceiver sends known
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`signals to the other transceiver. The transmitting transceiver typically derives the
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`known signal from its clock. Therefore the frequency of this known signal is
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`representative of the clock frequency of the transmitting transceiver. The other
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`transceiver receives this known signal and adjusts the frequency of its clock based
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`on the frequency of the received signal. The known signal thus indirectly allows
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`the two transceivers to synchronize, or “lock,” the frequencies of their respective
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`clocks. The timing synchronization procedure is also described in the ’404 patent.
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`See Ex. 1001 at 5:37–50 and 5:54–62. In the 1995 ADSL Standard, this procedure
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`is referred to as “loop timing” or “timing recovery.” See Ex. 1009, 1995 ADSL
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`Standard at § 12.2.2 (p. 90) & 12.5.6 (p. 97). In the context of the claims of the
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`’404 patent, the known signal is the claimed “synchronization signal.”
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`3.
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`Loop Characterization
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` Subsequently, the initialization process continues with the transceivers
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`determining certain characteristics of
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`the wire
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`loop
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`that connects
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`them.
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`Attenuation, also known as loop loss, is an example of a loop characteristic.
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`Attenuation is the reduction in power a signal experiences as it travels across a
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`wire loop and is a function of different physical characteristics of the wire loop,
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`such as its length, wire diameter and cable composition. The transceivers estimate
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`attenuation by measuring the received power of a known signal and comparing that
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`power to the known transmit power of the signal. The ratio of the signal power at
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`the transmitter to the signal power at the receiver is the attenuation. (For example,
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`a 100x reduction in power is an attenuation of 20 decibels, or 20 dB.) Attenuation
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`may be used to adjust transmit power, since less attenuation allows a smaller
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`transmit power to be used in order to meet a received power level requirement at a
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`receiver. Loop background noise is another example of a loop characteristic.
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`4.
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`Channel Characterization
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` The initialization process typically continues with the transceivers
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`performing transceiver training and channel analysis, which include determining
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`equalization settings, echo canceller settings, and measuring signal to noise ratio
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`on a per-subchannel basis. Signal to noise ratio (“SNR”) is a function of, inter
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`alia, loop characteristics (e.g., line noise levels and line attenuation), and is used to
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`determine transmission parameters that are used for transmission of data. If the
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`line noise level is elevated, SNR will be lower, and vice versa. SNR then in turn is
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`used to determine transmission parameters including transmission and reception
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`data ranges, fine gain parameters, and bit allocation parameters. See id. at 3:10–
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`20. The transceivers then go through the step of exchanging the transmission
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`parameters
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` As explained in the ’404 patent, the initialization process of a DSL
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`system can take tens of seconds. See id. at 3:23–25. Once the transceivers are
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`initialized, the transceivers can transmit and receive data. Data may be sent in
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`superframes that include frames of modulated data followed by a modulated
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`synchronization symbol. Id. at 5:5–10. For example, the superframe may include
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`68 data frames followed by a 69th frame that is a synchronization frame. Id. at
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`5:10–13. The synchronization frame may be used by a transceiver to determine the
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`boundary of
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`the
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`superframe and maintain
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`superframe alignment or
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`synchronization.
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`5.
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`The Inventions of the ’404 Patent
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` The ’404 Patent recognizes that prior art multicarrier transceivers
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`were maintained in the continuous “on” state because of the importance that they
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`remain ready to immediately transmit or receive data. See Ex. 1001 at 2:55–58. In
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`this “on” state, both the transmitter and receiver portion of a prior art transceiver
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`remained fully functional at all times, resulting in transceivers unnecessarily using
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`a significant amount of power and potentially having a reduced life span. See Ex.
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`1001 at 2:58–63. Low power modes (in which data communications are
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`temporarily suspended) were known in the prior art, but required a lengthy re-
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`initialization sequence upon coming out of the low power mode. See Ex. 1001 at
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`3:23–30. This was unacceptable to users who desired near-instantaneous return to
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`full data communications. Id.
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` The claimed inventions of the ’404 patent overcame this problem by
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`providing a transceiver that can enter a low power mode from a full power mode
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`(and thus reduce power consumption) and then subsequently exit the low power
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`mode and restore the full power mode without the need of going through the re-
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`initializing process. See Ex. 1001 at 10:2–12:21. The claimed transceivers of the
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`’404 patent provide this capability by (1) storing, in the low power mode, a full
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`power mode operation parameter (such as a fine gain and a bit allocation
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`parameter) and using that parameter to restore full power, and (2) transmitting or
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`receiving, in the low power mode, a synchronization signal. In this way, the
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`transceiver, upon waking up, does not have to engage in the re-initialization
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`process in order to commence exchanging data with another transceiver in the
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`system.
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`B. Overview of the Cited Art
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`24.
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`I understand that Petitioner relies on three references in its proposed
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`ground of invalidity of the ’404 patent claims – U.S. Pat. No. 5,956,323 (“Bowie”),
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`U.S. Pat. No. 6,246725 (“Vanzieleghem”), and the American National Standard
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`Institute’s ANSI T1.413-1995 Standard for Telecommunications—Network and
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`Customer Installation Interfaces – Asymmetric Digital Subscriber Line (ADSL)
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`Metallic Interface (the “1995 ADSL Standard,” as first mentioned earlier).
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`1.
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`Bowie
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` Bowie describes an invention that is directed to a power conservation
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`method for an asymmetric digital subscriber line (“ADSL”) system that transmits
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`wide-bandwidth modulated data over a two-wire loop using high frequency carrier
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`signals. Ex. 1005 at 1:4–8, 1:23–25. As shown in Figure 1 of Bowie, reproduced
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`below, the Bowie system uses ADSL units (e.g., modems) that are connected by a
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`wire loop 120. Each ADSL unit includes signal processing electronics 111, data
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`transmit circuitry 112 and data receive circuitry 113 to send, receive, and process
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`modulated data. See id. at 2:1–6, 3:2–5, 5:52–55. Each unit also includes a
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`resume signal detector 115, which can be a 16 kHz AC signal detector 115 that
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`employs conventional frequency detection techniques. See id. at 5:52–55.
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`Id., Fig. 1.
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` Bowie explains that, prior to data being sent between two ADSL units
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`over the loop, loop characteristics must be determined and exchanged. See id. at
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`4:64–5:4. He explains that loop characteristics include loop loss characteristics.
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`Id. Bowie uses the terms “loop characteristics,” “electronic characteristics of the
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`particular wire loop,” “loop transmission characteristics” and “loop characteristic
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`parameters” interchangeably, and describes “loop loss characteristics” as an
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`example of these. See Ex. 1005 at 4:67–5:3, 5:23–25, 5:62–66, 6:25–33. Bowie
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`refers to the exchange of loop characteristics as “handshaking.” Id. at 5:1–5.
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`27.
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` Bowie further teaches that when an ADSL unit receives a shut down
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`signal, it enters a low power mode in which the signal processing electronics, data
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`transmit circuitry, and data receive circuitry all shut down. See id. at 5:17–28. The
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`resume signal detector is the only circuitry that remains operational. See id.
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`Bowie explains that loop 220 is “in an inactive state” when the unit enters the low
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`power mode. Id. at 5:28–29. Bowie recognizes that the signal processing,
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`transmitting, and receiving circuitry consume substantial amounts of power when
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`transmitting and receiving “modulated data signals” and that consequently shutting
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`down the transmitting, receiving, and signal processing circuitry, i.e., most of the
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`transceiver’s circuitry, saves a significant amount of power—up to five watts per
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`loop. See id. at 2:1–6.
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`28.
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` Bowie further teaches that, upon entering the low power mode, the
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`ADSL units may “store[] in memory 117 characteristics of the loop 220 that were
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`determined by… handshaking.” Id. at 5:17–28. As previously explained at supra
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`IV.A.3, attenuation and loop background noise are exemplary loop characteristics.
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`Thus, Bowie teaches storing loop characteristics, such as attenuation, upon going
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`into low power mode. It is noteworthy that Bowie, however, does not disclose
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`storing bit allocation or fine gain parameters in the low power mode.
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` Upon receipt of a “resume signal” at the resume signal detector 115,
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`the Bowie unit “returns the signal processing 111, transmitting 112, and receiving
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`113 circuitry to full power mode.” Id. at 5:60–62. The stored “loop transmission
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`characteristics… are retrieved from memory 117 and used to enable data
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`transmission to resume quickly by reducing the time needed to determine loop
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`transmission characteristics.” Id. at 5:62–66 (emphasis added). Thus, Bowie
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`teaches using the stored loop characteristics as a starting point for a process of re-
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`determining the loop characteristics upon coming out of the low power mode.
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` Bowie teaches that one of the reasons that the loop characteristics
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`have to be re-determined upon coming out of the low power mode is that the loop’s
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`characteristics may have changed while the system was in the low power mode.
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`See Ex. 1005 at 5:66–6:1 (“After resumption of full power mode, additional
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`handshaking between ADSL units 232 and 242 may occur.”); id. at 6:37–41
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`(“Handshaking
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`information may be
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`required where,
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`for example,
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`loop
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`characteristics have changed due, for example, to temperature-dependent changes
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`in loop resistance.”). Re-determining the loop characteristics after coming out of
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`low power mode is required to ensure the transceivers “establish reliable data
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`communication between the units.” Id. at 6:36–37.
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` Accordingly, Bowie
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`teaches
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`that some
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`initialization (i.e., re-
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`determining the loop characteristics) must occur when the unit comes out of the
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`low power mode. Moreover, Bowie does not teach avoiding the initialization step
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`of determining transmission parameters such as bit allocation and fine gain
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`parameters.
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`32.
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`In my opinion, Bowie’s invention is limited to (1) a “resume signal
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`generator” and a “resume signal detector” added onto an existing ADSL Standard
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`transceiver, (2) a low-power mode that turns off the ADSL transceiver’s
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`communication circuitry except for the “resume signal detector” (and the “resume
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`signal generator,” if and when it is time to return the other transceiver to normal
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`operation) and (3) the concept of storing some information about the loop, such as
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`attenuation, while in low power mode. As Bowie explains, storing loop
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`information allows the Bowie unit to reduce the time needed to determine loop
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`characteristics, which in turn are used to determine transmission parameters. This
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`is a simplistic power saving scheme that does little to integrate with the existing
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`internal functionality of an ADSL modem, and Bowie does very little to describe
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`how any integration is to be performed by one of skill in the art. Therefore, it is
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`substantially different from the ’404 patent regarding the implementation of a low
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`power mode, as discussed further in this declaration.
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` Bowie also does not teach using a synchronization signal when in the
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`low power mode. This is consistent with Bowie’s teaching that all of the
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`transceiver circuitry except for the resume signal detector is shut off in low power
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`mode in order to save power.
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`2.
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`Vanzieleghem
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` Vanzieleghem discloses an ADSL transmitter for a multicarrier
`34.
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`system that can reduce power dissipation during operation depending on the type
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`of input data it is being asked to transmit. Ex. 1006 at 1:10–14; 4:46–50, 6:29–36.
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`The input data may be either effective data or idle data. See Ex. 1006 at 5:33–35.
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`When effective data is to be transmitted, the transmitter uses all of its carriers (e.g.,
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`256 carriers) to send the data to a receiver. See Ex. 1006 at 5:66–6:15. When the
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`transmitter has only idle data to transmit, it reduces power dissipation by
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`transmitting a reduced number of carriers.
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` See Ex. 1006 at 6:30–41.
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`Vanzieleghem further discloses maintaining frame synchronization with a receiver
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`by periodically sending synchronization symbols of the type described in the
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`ADSL Standard as part of a superframe. See Ex. 1006 at 6:59–61; 5:53–65.
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`Specifically, with respect to the synchronization symbol, Vanzieleghem explains
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`that at least one synchronization signal is sent for every 68 DMT symbols. See Ex.
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`1006 at 5:53–55 (“For every N=68 DMT symbols transmitted on the line, at least
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`one synchronization symbol
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`is sent.”).
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` Vanzieleghem explains
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`that
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`the
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`synchronization symbols “are generated as usual.” See Ex. 1006 at 6:60–61. Per
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`the 1995 ADSL Standard, the synchronization symbol is generated from a pseudo-
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`random number and is transmitted using all but the 64th carrier of the
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`communication channel. See Ex. 1009 at 46–47. The 64th carrier is used to
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`communicate the pilot tone. See Ex. 1009 at 47.
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` Vanzieleghem does not disclose storing, in a low power mode, any
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`transmission parameters such as fine gain or bit allocation parameters.
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`Vanzieleghem also does not disclose exiting a low power mode and restoring a full
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`power by using stored transmission parameters. Vanzieleghem also does not teach
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`that restoration of the full power mode can occur without re-initialization or
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`avoiding any steps of the initialization process upon coming out of a low power
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`mode. Vanzieleghem is directed to saving power by reducing solely the power
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`consumed by the transmitter of the transceiver. In contrast, Bowie saves power by
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`shutting down transmitting, receiving and processing circuity of the transceiver.
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`Therefore, Bowie’s low power mode saves more power than Vanzieleghem does
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`because Vanzieleghem only reduces the power dissipation of just its transmitter.
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`3.
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`The 1995 ADSL Standard
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` The 1995 ADSL Standard discloses electrical characteristics of ADSL
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`signals appearing at a network interface and the requirements for transmission
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`between a network and customer installation. Ex. 1009 at 1.
`
` A person of skill in the art (“POSITA”) would understand that
`37.
`
`initialization, as defined in the 1995 ADSL Standard, includes distinct, sequential
`
`steps of determining loop characteristics and determining bit and gain parameters
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`based on the loop characteristics. The 1995 ADSL Standard states “[o]ne part of
`
`the ADSL initialization and training sequence estimates the loop characteristics to
`
`determine whether the number of bytes per Discrete MultiTone (“DMT”) frame
`
`required for the requested configuration's aggregate data rate [i.e., the necessary bit
`
`allocations] can be transmitted across the given loop.” Ex. 1009 at 9. The
`
`Standard further explains that “each receiver communicates to its far-end
`
`transmitter the number of bits and relative power levels [i.e., bit allocation and fine
`
`gain parameters] to be used on each DMT sub-carrier, as well as any messages and
`
`final data rates information. For highest performance these settings shall be based
`
`on the results [i.e., based in part on loop characteristics] obtained through the
`
`transceiver training and channel analysis procedures.” Ex. 1009 at 87 (with
`
`bracketed comments inserted). Therefore, the Standard distinguishes between loop
`
`characteristics of the loop and transmission parameters like bit allocation and fine
`
`gain parameters.
`
`38.
`
` A POSITA would further understand that the 1995 ADSL Standard
`
`does not describe operating in a low power mode, going into a low power mode, or
`
`coming out of a low power mode. The 1995 ADSL Standard does not explain how
`
`to store bit allocation or fine gain parameters in a low power mode or how to use
`
`those parameters to avoid re-initialization when coming out of a low power mode.
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`Further, the 1995 ADSL Standard describes a mandatory control channel that is
`
`always required to be active. See Ex. 1009 at 13.
`
`V. LEGAL STANDARDS APPLIED
`
`
`39.
`
`I am not an expert in patent law, and I am not purporting to provide
`
`any opinions regarding the correct legal standards to apply in these proceedings. I
`
`have been asked, however, to provide my opinions in the context of the following
`
`legal standards that have been provided to me by TQ Delta’s attorneys.
`
` Obviousness in General: I have been informed that a patent can be
`40.
`
`invalidated through obviousness if the subject matter of a claim as a whole would
`
`have been obvious at the time of the invention to a person of ordinary skill in the
`
`art. I understand that obviousness allows for the combination of prior art
`
`references. I have been informed that there are three basic inquiries that must be
`
`considered for obviousness:
`
`a. What is the scope and content of the prior art?
`
`b. What are the differences, if any, between the prior art and each claim
`
`of the patent?
`
`c. What is the level of ordinary skill in the art at the time the invention
`
`of the patent was made?
`
`
`
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`41.
`
`I also understand that a claim composed of several elements is not
`
`proved obvious merely by demonstrating that each of its elements was
`
`independently known in the prior art. I understand that when prior art references
`
`require selective combination to render a patent obvious, there must be some
`
`reason to combine the references other than hindsight. I further understand that an
`
`assertion of obviousness cannot be sustained by mere conclusory statements, and
`
`that there must be some articulated reasoning with some rational underpinning to
`
`support a finding of obviousness. In particular, a person of skill in the art had to
`
`have had a motivation to combine the prior art in the way claimed in the claim and
`
`had a reasonable expectation of success in doing so. I understand that features
`
`from prior art references need not be physically combinable (i.e., a combination
`
`may be obvious if one of ordinary skill in the art would know how to make any
`
`necessary modifications to combine features from prior art references), but that this
`
`concept does not negate the requirement of a reasonable expectation of success.
`
`
`42.
`
`I understand that one must also consider the evidence from secondary
`
`considerations including commercial success, copying, long-felt but unresolved
`
`needs, failure of others to solve the problem, unexpected results, and whether the
`
`invention was made independently by others at the same time of the invention. I
`
`understand that these secondary considerations can overcome a finding of
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`obviousness.
`
`
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`43.
`
`I also understand that a combination of references does not render a
`
`claim obvious if a reference teaches away from its combination with another
`
`reference. I understand that a reference may teach away when (1) the teachings of
`
`a prior art reference undermine the reason being proffered as to why a person of
`
`ordinary skill would have combined elements of the reference with another prior
`
`art reference, (2) a proposed modification to a prior art reference’s device would
`
`render the device inoperable for its intended purpose, or (3) when a person of
`
`ordinary skill, upon reading the reference, would be led in a direction divergent
`
`from the path that was taken by the applicant.
`
`
`44.
`
`I further understand that in performing an obviousness analysis, it
`
`may be necessary to construe the one or more terms that are recited in the claims. I
`
`have been informed that in an Inter Partes Review, claims are given their broadest
`
`reasonable interpretation in light of the claims and specification. I have been
`
`informed that this means that the broadest reasonable construction of a term is not
`
`simply one which covers the most embodiments but one that is reasonable in light
`
`of the claims and specification.
`
`VI. PERSON OF ORDINARY SKILL IN THE ART
`
`
`45.
`
`I understand that a person of ordinary skill in the art is considered to
`
`have the normal skills and knowledge of a person in a certain technical field, as of
`
`the time of the invention at issue. I understand that factors that may be considered
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`in determining the level of ordinary skill in the art include: (1) the education level
`
`of the inventor; (2) the types of problems encountered in the art; (3) the prior art
`
`solutions to those problems; (4) the rapidity with which innovations are made; (5)
`
`the sophistication of the technology; and (6) the education level of active workers
`
`in the field.
`
`
`46.
`
`I understand that Petitioner’s expert, Mr. McNally, opined that a
`
`person of ordinary skill in the art would have had “education and/or experience in
`
`the field of digital communication or telecommunications products” and had “a
`
`basic Bachelor’s of Electrical Engineering, Computer Science, or equivalent
`
`degree, but with more than three years of relevant work experience” or “more
`
`advanced degrees—e.g., Masters or Ph.D.—but having fewer years of experience.”
`
`Ex. 1003 at ¶¶ 31–32.
`
`
`47.
`
`I have considered the factors listed above and Mr. McNally’s
`
`description of a person of ordinary skill in the art. In my opinion, with respect to
`
`the ’404 patent, a person of ordinary skill in the art would have an electrical
`
`engineering background and experience
`
`in
`
`the design of multicarrier
`
`communication systems, such as those employing orthogonal frequency division
`
`multiplexing (“OFDM”) or DMT modulation. More particularly, a person of skill
`
`in the art would be a person with a bachelor’s degree in electrical engineering (or a
`
`
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`similar technical degree or equivalent work experience) and at least three years of
`
`experience working with such multicarrier communication systems.
`
`
`48.
`
`I have 18 years of combined industrial and academic experience in the
`
`architecture, design, development, t
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