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`EXPERT DECLARATION OF DOUGLAS A. CHRISSAN, Ph.D.
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`Case No. IPR2016-01466
`Patent No. 8,611,404
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`TQ Delta Exhibit 2005
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`Cisco Systems, Inc. v. TQ Delta, LLC
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`IPR2016-01466
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
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`I.
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`INTRODUCTION & SUMMARY OF OPINIONS
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` My name is Douglas A. Chrissan. I have been engaged by TQ Delta, 1.
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`LLC in connection with IPR number 2016-01466 which relates to U.S. Pat. No.
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`8,611,404 (“the ’404 patent”). In this declaration I provide my opinion that the
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`challenged claims of the ’404 patent would not have been obvious in view of the
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`references and grounds asserted by the Petitioner Cisco. (“Cisco” or “Petitioner”).
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`II.
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`PROFESSIONAL QUALIFICATIONS
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`A. Background and Experience
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`2.
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`I am presently a technical consultant in the areas of communications
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`systems, multimedia systems, computer systems, and digital signal processing.
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`3.
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`I earned a B.S. and M.S. in Electrical Engineering from the University
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`of Southern California in 1988 and 1990, respectively, and a Ph.D. in Electrical
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`Engineering from Stanford University in 1998.
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`4.
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`5.
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`A copy of my current CV is attached as Ex. 2006.
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`I was a Masters Fellow and Member of the Technical Staff at Hughes
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`Aircraft Company in El Segundo, California, from 1988–1993. While at Hughes
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`Aircraft, I designed and developed communication systems for commercial and
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`military spacecraft, including for the MILSTAR satellite program.
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`Declaration of Douglas A. Chrissan, Ph.D.
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`6.
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`Between 1992 and 1993, while at Hughes Aircraft Company, I
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`designed and built a
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`state-of-the-art, 800 megabit-per-second
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`(Mbps)
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`telecommunications modem for the NASA Lewis Research Center.
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`7.
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`From 1997–2003, I worked at 8x8, Inc., starting as a DSP software
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`engineer in 1997, becoming a manager in 1998, a director in 1999, and Vice
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`President of Engineering in 2000 (managing a team of approximately 60 engineers
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`in the company’s microelectronics group). I played a key role in developing
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`several
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`semiconductor products used worldwide
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`in multimedia
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`and
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`communications devices, mainly for video conferencing systems and Internet
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`Protocol (“IP”) telephones. Some of these semiconductor products were in
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`production more than ten years.
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`8.
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`From 2003–2007, I was a Systems Architect and Engineering
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`Program Manager at Texas Instruments in the Digital Subscriber Line (“DSL”)
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`product business unit. At Texas Instruments, I was directly involved in the
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`architecture, design, development and production of multicarrier DSL modem
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`products. My work specifically included architecting a multicarrier DSL
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`semiconductor and software product and managing all aspects of its development
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`from inception to production.
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` My Ph.D. dissertation and related publications are in the fields of 9.
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`statistical signal processing and communication systems, and more specifically in
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`the area of impulsive noise modeling for communication systems.
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`10.
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`In 1995 I was the instructor for the graduate Statistical Signal
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`Processing class (EE278) in the Electrical Engineering department at Stanford
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`University. Prior to teaching this class, I was a teaching assistant for ten different
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`classes in signal processing and radio frequency electronics at Stanford.
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`11.
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`I have developed, and managed the development of, several
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`successful semiconductor, software and systems products in the communications
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`and multimedia fields. These products are listed in the attached curriculum vitae.
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`B. Compensation
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`12.
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`I am being compensated for my time in this case at the rate of $250
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`per hour (plus expenses) for analysis, depositions, and, if necessary, trial
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`testimony. My compensation for this matter is not determined by or contingent on
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`the outcome of this case.
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`C. Materials Relied Upon
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`13.
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`In the course of preparing this expert declaration, I have considered
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`the ’404 Patent, its file history, the Petition and its exhibits (including the
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`Declaration of Dr. Kiaei), the Patent Owner’s Preliminary Response, the Board’s
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`Institution Decision, the transcript of the deposition of Dr. Kiaei, as well as any
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`additional documents I cite or refer to in this declaration.
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`III. THE BOARD’S INSTITUTION DECISION
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`14.
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`I understand the Board instituted inter partes review of claims 6, 10,
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`11, 15, 16, and 20 of the ’404 patent as unpatentable over U.S. Patent No.
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`5,956,323 (“Bowie”) and U.S. Patent No. 6,075,814 (“Yamano”) in view of the
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`American National Standards Institute (ANSI) T1.413-1995 Standard, entitled
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`“Network and Customer Installation Interfaces – Asymmetric Digital Subscriber
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`Line (ADSL) Metallic Interface” (referenced herein as “ANSI T1.413,” the “1995
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`ADSL Standard” or the “1995 ADSL Specification”).
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`IV. BACKGROUND
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` The ’404 patent discloses improvements to a multicarrier transceiver. 15.
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`Specifically, the ’404 patent describes inventions that allow a transceiver to enter a
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`low power mode from a full power mode and to rapidly exit the low power mode
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`at some later time. The transceiver stores one or more transmission and/or
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`reception parameters associated with a full power mode in the low power mode,
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`and exits the low power mode using the one or more transmission and/or reception
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`parameters without re-initializing. To facilitate an understanding of the prior art
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`and the inventions of the ’404 patent, a brief overview of multicarrier technology is
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`set forth below.
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`A. Overview Of Multicarrier Technology
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` As explained in the ’404 patent, multicarrier transmission systems 16.
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`provide high speed data links between communication points. See Ex. 1001 at
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`1:37–38. A Digital subscriber line (“DSL”) system is one example of a
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`multicarrier transmission system that is used to provide high-speed data
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`communication over the same subscriber loop that provides telephone service to a
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`subscriber. See id. at 1:37–47.1, 2 Because the Petition specifically relies on the
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`1995 ADSL Standard in its obviousness analysis, this overview is provided with
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`reference to—and in the context of—DSL systems that operate in accordance with
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`the 1995 ADSL Standard. The transceivers in a DSL system communicate with
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`each other by dividing the bandwidth of the communication channel connecting the
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`subscriber and a central office into separate subchannels, or carriers, each of
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`limited bandwidth, operating in parallel with each other. See id. at 1:48–55. The
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`transceiver divides the data to be communicated over the DSL connection into
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`1 The ’404 patent identifies ADSL (asynchronous digital subscriber line) and
`HDSL (High-Speed Digital Subscriber Line) as exemplary multicarrier protocols;
`this declaration references only ADSL, as described in the 1995 ADSL Standard.
`2 Yamano describes an alternative “single carrier” DSL technology, which will be
`discussed in sections of this declaration specific to Yamano.
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`groups of bits, allocates each group of bits to a respective carrier, and modulates
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`each group of bits onto its respective carrier. See id. at 1:63–66. A transceiver that
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`communicates data by modulating data onto multiple carriers simultaneously is
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`referred to as a multicarrier transceiver.
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` Each carrier has a phase characteristic and an amplitude characteristic. 17.
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`The phase characteristic varies over a range of 0 to 360 degrees (i.e., 0 to 2π
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`radians); the amplitude characteristic varies over a range determined by the
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`transmit power level of the subcarrier. The phase and/or amplitude of a carrier is
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`modified based on the value of the group of bits allocated to the given carrier. The
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`number of bits that are allocated to a carrier is referred to as the “bit loading” for
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`that carrier. Modulation that changes the phase and/or amplitude of a subcarrier on
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`a per-symbol basis is referred to as quadrature amplitude modulation (“QAM”).
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`Modulating a multiplicity of subcarriers, as described above, is referred to as
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`multicarrier modulation. The inventions claimed in the ’404 patent improve the
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`operation of multicarrier transceivers.
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` The 18.
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`transmission signal comprising
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`the modulated carriers
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`is
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`transmitted for a fixed duration. This duration is referred to as the symbol period
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`or frame period, which for multicarrier DSL transceivers is typically a fraction of a
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`millisecond. During a subsequent symbol period the transmission signal is
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`generated by combining the same carriers, but modulated with the next set of data
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`bits, and so on.
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` A transceiver that receives this transmission signal “demodulates” the 19.
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`received signal to determine the amplitude and phase characteristic of each
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`constituent subcarrier for each symbol period, and decodes these respective
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`characteristics to reproduce original bit values.
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` Before a multicarrier transceiver begins transmitting and receiving 20.
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`data, the transceiver undergoes an initialization process. See id. at 3:7–9. There
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`are several distinct phases of initialization. Certain initialization steps for a
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`multicarrier DSL transceiver are described in Section IV.C.3.c below, “ADSL
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`Initialization.”
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`B.
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`The Inventions Of The ’404 Patent
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` The ’404 Patent recognizes that prior art multicarrier transceivers 21.
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`were maintained in the continuous “on” state because it was important that they
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`remain ready to immediately transmit or receive data. See Ex. 1001 at 2:55–58. In
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`this “on” state, both the transmitter and receiver portion of a prior art transceiver
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`remained fully functional at all times, resulting in the transceiver unnecessarily
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`using a significant amount of power and potentially having a reduced life span.
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`See Ex. 1001 at 2:58–63. Low power modes (in which data communications are
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`temporarily suspended) were known in the prior art, but required a lengthy re-
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`initialization sequence upon coming out of the low power mode. See Ex. 1001 at
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`3:23–30. This was unacceptable to users who desired near-instantaneous return to
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`full data communications. Id.
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` The claimed inventions of the ’404 patent overcame this problem by 22.
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`providing a transceiver that can enter a low power mode from a full power mode
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`(and thus reduce power consumption) and then subsequently exit the low power
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`mode and restore the full power mode without the need of going through the re-
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`initializing process. See Ex. 1001 at 10:2–12:21. The claimed transceivers of the
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`’404 patent provide this capability by (1) storing, in the low power mode, a full
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`power mode operation parameter (such as a fine gain and a bit allocation
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`parameter) and using that parameter to restore full power, and (2) transmitting or
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`receiving, in the low power mode, a synchronization signal. In this way, the
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`transceiver, upon waking up, does not have to engage in the re-initialization
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`process in order to commence exchanging data with another transceiver in the
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`system. Furthermore, because the transceiver continues to receive, while in the
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`low power mode, a synchronization signal transmitted by the remote transmitter,
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`the timing relationship established between the transceiver and the remote
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`transceiver during full power mode is maintained while the transceiver is in low
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`power mode.
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`C. Overview of the Cited Art
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`23.
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`I understand that Petitioner relies on three references in its proposed
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`ground of invalidity of the ’404 patent claims – U.S. Pat. No. 5,956,323 (“Bowie”),
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`U.S. Pat. No. 6,075,814 (“Yamano”), and the American National Standard
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`Institute’s ANSI T1.413-1995 Standard for Telecommunications—Network and
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`Customer Installation Interfaces – Asymmetric Digital Subscriber Line (ADSL)
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`Metallic Interface (the “1995 ADSL Standard,” as first mentioned earlier).
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`1.
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`Bowie
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` Bowie describes an invention that is directed to a power conservation 24.
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`method for an asymmetric digital subscriber line (“ADSL”) system that transmits
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`wide-bandwidth modulated data over a two-wire loop using high frequency carrier
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`signals. Ex. 1005 at 1:4–8, 1:23–25. As shown in Figure 1 of Bowie, reproduced
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`below, the Bowie system uses ADSL units (e.g., modems) that are connected by a
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`wire loop 120. Each ADSL unit includes signal processing electronics 111, data
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`transmit circuitry 112 and data receive circuitry 113 to send, receive, and process
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`modulated data. See id. at 2:1–6, 3:2–5, 5:52–55. Each unit also includes a
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`resume signal detector 115, which can be a 16 kHz AC signal detector 115 that
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`employs conventional frequency detection techniques. See id. at 5:52–55.
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`Figure 1, a reproduction of Fig. 1 from Bowie
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`Id., Fig. 1.
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` Bowie explains that, prior to data being sent between two ADSL units 25.
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`over the loop, loop characteristics must be determined and exchanged. See id. at
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`4:64–5:4. He explains that loop characteristics include loop loss characteristics.
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`Id. Bowie uses the terms “loop characteristics,” “electronic characteristics of the
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`particular wire loop,” “loop transmission characteristics” and “loop characteristic
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`parameters” interchangeably, and describes “loop loss characteristics” as an
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`example of these. See Ex. 1005 at 4:67–5:3, 5:23–25, 5:62–66, 6:25–33. Bowie
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`refers to the exchange of loop characteristics as “handshaking.” Id. at 5:1–5.
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` Bowie further teaches that when an ADSL unit receives a shut-down 26.
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`signal, it enters a low power mode in which the signal processing electronics, data
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`transmit circuitry, and data receive circuitry all shut down. See id. at 5:17–28. The
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`resume signal detector is the only circuitry that remains operational. See id.
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`Bowie explains that loop 220 is “in an inactive state” when the unit enters the low
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`power mode. Id. at 5:28–29. Bowie recognizes that the signal processing,
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`transmitting, and receiving circuitry consume substantial amounts of power when
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`transmitting and receiving “modulated data signals” and that consequently shutting
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`down the transmitting, receiving, and signal processing circuitry, i.e., most of the
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`transceiver’s circuitry, saves a significant amount of power—up to five watts per
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`loop. See id. at 2:1–6.
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` Bowie further teaches that, upon entering the low power mode, the 27.
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`ADSL units may “store[] in memory 117 characteristics of the loop 220 that were
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`determined by… handshaking.” Id. at 5:17–28. As previously explained supra,
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`attenuation and loop background noise are exemplary loop characteristics. Thus,
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`Bowie teaches storing loop characteristics, such as attenuation, upon going into
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`low power mode. It is noteworthy that Bowie, however, does not disclose storing
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`bit allocation or fine gain parameters in the low power mode.
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` Upon receipt of a “resume signal” at the resume signal detector 115, 28.
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`the Bowie unit “returns the signal processing 111, transmitting 112, and receiving
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`113 circuitry to full power mode.” Id. at 5:60–62. The stored “loop transmission
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`characteristics… are retrieved from memory 117 and used to enable data
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`transmission to resume quickly by reducing the time needed to determine loop
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`transmission characteristics.” Id. at 5:62–66 (emphasis added). Thus, Bowie
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`teaches using the stored loop characteristics as a starting point for a process of re-
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`determining the loop characteristics upon coming out of the low power mode.
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` Bowie teaches that one of the reasons that the loop characteristics 29.
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`have to be re-determined upon coming out of the low power mode is that the loop’s
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`characteristics may have changed while the system was in the low power mode.
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`See Ex. 1005 at 5:66–6:1 (“After resumption of full power mode, additional
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`handshaking between ADSL units 232 and 242 may occur.”); id. at 6:37–41
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`(“Handshaking
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`information may be
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`required where,
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`for example,
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`loop
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`characteristics have changed due, for example, to temperature-dependent changes
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`in loop resistance.”). Re-determining the loop characteristics after coming out of
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`low power mode is required to ensure the transceivers “establish reliable data
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`communication between the units.” Id. at 6:36–37.
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` Accordingly, Bowie 30.
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`teaches
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`that some
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`initialization (i.e., re-
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`determining the loop characteristics) must occur when the unit comes out of the
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`low power mode. Moreover, Bowie does not teach avoiding the initialization step
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`of determining transmission parameters such as bit allocation and fine gain
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`parameters.
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`31.
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`In my opinion, Bowie’s invention is limited to (1) a “resume signal
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`generator” and a “resume signal detector” added onto an existing ADSL Standard
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`transceiver, (2) a low-power mode that turns off the ADSL transceiver’s
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`communication circuitry except for the “resume signal detector” (and the “resume
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`signal generator,” if and when it is time to return the other transceiver to normal
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`operation) and (3) the concept of storing some information about the loop, such as
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`attenuation, while in low power mode. As Bowie explains, storing loop
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`information allows the Bowie unit to reduce the time needed to determine loop
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`characteristics, which in turn are used to determine transmission parameters. This
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`is a simplistic power saving scheme that does little to integrate with the existing
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`internal functionality of an ADSL modem, and Bowie does very little to describe
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`how any integration is to be performed by one of skill in the art. Therefore, it is
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`substantially different from the ’404 patent regarding the implementation of a low
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`power mode, as discussed further in this declaration.
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` Bowie also does not teach using a synchronization signal when in the 32.
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`low power mode. This is consistent with Bowie’s teaching that all of the
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`transceiver circuitry except for the resume signal detector is shut off in low power
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`mode in order to save power.
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`2.
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`Yamano
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` The disclosure in Yamano “relates to the reduction of the required 33.
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`amount of signal processing in a modulator/ demodulator (modem) which is
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`transferring packet-based data or other information which is intermittent in nature
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`on a communication channel.” See Ex. 1006 at 1:8–14.
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` Yamano acknowledges that DSL modems may use either single 34.
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`carrier modulation, denoted “QAM” by Yamano, or multicarrier modulation
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`(“MCM”), also known as Discrete Multi-Tone (“DMT”). However,
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`the
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`embodiments illustrated and described in Yamano, Figs. 2, 3 and 4, are single
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`carrier DSL receivers. Although Yamano references multicarrier DSL receivers, it
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`does so only in passing to recognize that multicarrier receivers are different from
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`the described single carrier receivers. See Ex. 1005 at 14:59–62 (“the receiver
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`circuit used in connection with an MCM signalling (sic) protocol (hereinafter an
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`MCM receiver circuit) is different from receiver circuit 400”). However, Yamano
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`falls far short of enabling a POSITA to modify a prior art DMT DSL modem to
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`implement Yamano’s invention. This was acknowledged by Dr. Kiaei during his
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`deposition. See Ex. 2004 at 173:18–19 (“In Yamano, it doesn't go into all the
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`details and the specifics”). To the extent Yamano suggests applicability of its
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`teachings to an ADSL system, as I explain later the teachings are incompatible
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`with multicarrier DSL and specifically with the 1995 ADSL Standard. Setting
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`aside that Yamano’s embodiments relate to single carrier receivers and that
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`Yamano’s embodiments are incompatible with the 1995 ADSL Standard (see infra
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`at VIII H), I provide below an exposition of the features of Yamano as they relate
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`to the challenge.
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`35.
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`In its discussion of “Related Art,” Yamano explains that conventional
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`DSL modems transport data by generating an analog transmission signal which is
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`representative of a synchronous, constant rate (i.e., continuous) bit stream. Ex.
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`1006 at 1:18–20. Yamano explains that the transmitter of a conventional DSL
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`modem converts packets into “a continuous bit stream which is synchronous with
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`respect to the modem bit clock.” Id. at 1:41–45. When no packets are available
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`for transmission, the transmitter of a conventional DSL modem inserts idle
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`information into the continuous bit stream. Id. at 1:45–49 (“To create such a
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`synchronous bit stream…, framer 102 generates idle information (i.e., nulls or a
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`marking tone) when no packets are available, and generates packet data when
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`packets are available.”) With respect to an ANSI T1.413 DMT modem known in
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`the art at the time, a POSITA would recognize that the “continuous bit stream
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`which is synchronous with respect to the modem bit clock” that Yamano
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`references, with respect to a DMT modem, would correspond to the signaling and
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`associated superframe structure described in the ANSI T1.413 communication
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`standard (hereinafter “ADSL Signaling”). See Ex. 1007 at p. 24.
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` Yamano contends that the conventional synchronous, constant rate bit 36.
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`stream, e.g., ADSL signaling, “is suitable for the transmission of real-time
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`information such as voice or video,” but is not suitable for packet-based
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`information, like internet traffic, which is typically bursty in nature with an
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`average data rate that is often much less than the available peak data transfer rate
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`of the communication channel. Ex. 1006 at 1:20–28.
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` Yamano identifies several purported disadvantages of prior art DSL 37.
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`modems. Specifically,
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`“[t]ransmitter circuit exhibits three distinct disadvantages.
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`First, because transmitter circuit transmits constantly (either
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`packet data or idle information), a modem can be functionally
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`connected to only one telephone line at any given time.
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`Moreover, only a small percentage of the total information
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`carrying capacity of the communication channel is used to
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`transmit data, while a large percentage of this capacity is used
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`to transmit idle information. Additionally, transmitter circuit is
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`unsuited to multi-drop operation on a single communication
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`channel.”
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`Id. at 2:7–16. With respect to the prior art receiver of DSL modems, Yamano
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`recognizes that “a significant percentage of [the receiver’s] processing is dedicated
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`to the processing of the idle information generated by transmitter circuit 100,” the
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`far end transmitter. Id. at 3:26–28. Therefore, Yamano essentially contends that
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`ADSL Signaling is inefficient and also not suited for multi-drop operation.
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` Yamano describes several embodiments that seek to overcome the 38.
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`purported disadvantages of prior art DSL modems, including both single-carrier
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`QAM modems and DMT modems that use ADSL Signaling. Each of these
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`embodiments modifies the operation of a conventional ADSL receiver in a manner
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`that would render
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`the modem
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`incompatible with
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`the ADSL Standard.3
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`Specifically, contrary to Dr. Kiaei’s contention that “[a] POSITA would have been
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`motivated to implement the ANSI T1.413 communication standard with the DSL
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`communications systems of Bowie and Yamano so that their respective modems
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`could communicate with other modems on a communication loop in a standard
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`way,” (Ex. 1003 at ¶ 85), Bowie or for that matter any ADSL modem modified
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`with the teachings of Yamano would be “incapable to communicate with other
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`modems on a communication loop in a standard way.”
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`3 As described previously, Yamano’s descriptions and figures are overwhelmingly
`for single carrier QAM modems rather than DMT modems. I do not agree with
`Yamano that a POSITA could modify a DMT modem to implement its invention
`without undue experimentation. See Ex. 1006 at 14:59–15:11. Therefore, I do not
`attempt to explain Yamano as applied to a DMT modem, but instead use only
`Yamano’s description as applied to a single carrier QAM modem.
`
`
`
`18
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`
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
`
`
`
`39.
`
`In the first embodiment described in Yamano the receiver of a single
`
`carrier DSL modem is improved with circuitry that detects that idle information is
`
`being received, and in response to detecting idle information, the DSL modem
`
`enters a mode wherein certain functional blocks of its receiver are disabled.
`
`Yamano describes this mode as a standby mode. See, e.g., Ex. 1006 at 8:58–9:49.
`
`A block diagram of this receiver is reproduced from Yamano below.
`
`
`
`Figure 2, a reproduction of Fig. 3 from Yamano
`
`
`
` Specifically, in response to detecting idle information, symbol 40.
`
`decision circuit 305, channel decoder 306, framer/idle detector 307, equalizer
`
`update circuit 308 and carrier update circuit 309 are disabled. See Ex. 1006 at
`
`9:34–36. Yamano explains that “the processing requirements of receiver circuit
`
`
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`19
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
`
`are greatly reduced when receiver circuit operates in the standby mode.” Ex 1006
`
`at 9:36–38.
`
`
`
` A POSITA would recognize that this standby mode embodiment, at 41.
`
`least when operating in full processing mode, could operate, with experimentation,
`
`in accordance with the 1995 ADSL Specification. However, Dr. Kiaei does not
`
`rely on this standby mode embodiment in his obviousness analysis.
`
`
`
` Another embodiment described in Yamano “provide[s] for direct 42.
`
`support of packet traffic, as opposed to continuous bit streams.” Ex. 1006 at
`
`13:49–51. Yamano refers to this embodiment as a “burst-mode protocol.” Id. at
`
`4:29–42. The burst mode protocol allows arbitrarily long periods with no received
`
`signal. See id. at 13:54–55, 63–65 (describing “the transmitter circuit does not
`
`transmit idle information” and “[t]he transmitter circuit only sends information
`
`when there is meaningful packet data available to be sent.”) However, ADSL
`
`Signaling requires a continuously received signal, with
`
`idle
`
`information
`
`transmitted when there is no packet data to be transmitted. Therefore, the burst
`
`mode protocol cannot operate in accordance with the 1995 ADSL Specification. I
`
`understand from Dr. Kiaei’s declaration and deposition testimony that he relies on
`
`Yamano’s description of this burst-mode embodiment in his obviousness analysis.
`
`See Ex. 1003 at 74; Ex. 2004, Kiaei Tr., at 124:4–125:9.
`
`
`
`20
`
`
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
`
`
`
`
` Figure 3 below, generated for this declaration, is a depiction of 43.
`
`Yamano’s burst-mode DSL Subscriber Modem connected to a far-end Central
`
`Office Modem via a subscriber line. The subscriber modem includes receiver
`
`circuit 400 and a local transmitter circuit, the latter of which may have a similar
`
`design to far end transmitter circuit 100. A block diagram for transmitter circuit
`
`100 appears as Fig. 1 in Yamano and a block diagram for receiver circuit 400
`
`appears as Fig. 4 in Yamano.
`
`
`
`
`
`Figure 3, Yamano’s DSL Subscriber Modem Connected to a Far-End Central
`Office Modem
`
`
`
` Fig. 4 of Yamano is reproduced below. Ex. 1006 at 13:66–67. “Fig. 44.
`
`4 is a block diagram of a receiver circuit [400] of a modem in accordance with a
`
`burst-mode protocol of the present invention.” Id. at 6:36-39. From Dr. Kiaei’s
`
`declaration and deposition testimony, I understand that he relies on Yamano’s
`
`description of burst-mode receiver circuit 400 in his obviousness analysis with
`
`respect to certain elements of claim 6. Specifically, Dr. Kiaei alleges that
`
`
`
`21
`
`Central Office Modem
`
`“Far End” Transmitter
`(Transmitter Circuit 100)
`
`“Far End” Receiver
`
`Yamano’s DSL
`Subscriber Modem
`
`Local Transmitter Circuit
`
`Subscriber Line
`(carries both upstream
`and downstream signals)
`
`Receiver Circuit 400
`
`
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
`
`Yamano’s receiver circuit 400 “receive[s],
`
`in
`
`the
`
`low power mode, a
`
`synchronization signal[,]” as recited by claim 6 of the ’404 patent. See Ex. 1003 at
`
`74; Ex. 2004, Kiaei Tr., at 124:4–125:9.
`
`
`
`
`
` Yamano explains that the receiver circuit 400 has two modes of 45.
`
`operation: a full processing mode associated with data packet reception and a
`
`reduced processing mode associated with idle periods between data packets. Ex.
`
`1006 at 14:25–33. In the full processing mode, all the blocks of receiver circuit
`
`400 are enabled and receiver circuit 400 is capable of processing packet data
`
`transmitted by far end transmitter. See, e.g., id. at 15:5–7. To facilitate the
`
`operation of the burst-mode protocol, the receiver circuit 400 is adapted with a
`
`non-idle detector 401. Non-idle detector 401 is configured to (i) detect the
`
`predetermined non-idle state signal transmitted by the far end transmitter, and (ii)
`
`
`
`22
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
`
`in response to detecting the non-idle state signal, enable the full processing mode
`
`of the receiver circuit 400. See id. at 14:10–29.
`
`
`46.
`
`“To enable the reduced processing mode of receiver circuit 400, non-
`
`idle detector 401 disables resampler 302, equalizer 303, carrier recovery circuit
`
`304, symbol decision circuit 305, channel decoder 306, framer/idle detector 307,
`
`echo canceler 309, timing update circuit 310, equalizer update circuit 311, carrier
`
`update circuit 312 and packet queue 318 of receiver circuit 400, thereby
`
`simplifying the modem function when there is no packet data being received” from
`
`the far end transmitter. Id. at 14:33–42. Thus in reduced processing mode,
`
`Yamano describes turning off or disabling all blocks of receiver circuit 400 except
`
`for non-idle detector 401, A/D 301 and sample buffer 308. I understand that Dr.
`
`Kiaei confirmed this during his deposition. See Ex. 2004 at 130:22–131:7. I
`
`understand that Dr. Kiaei also annotated Figure 4 from Yamano during his
`
`deposition to indicate the blocks of the receiver that are disabled in the reduced
`
`processing mode. See Ex. 2002 (diagram from Kiaei deposition, also reproduced
`
`in Paragraph 119 below). Dr. Kiaei also confirmed during his deposition that this
`
`reduced processing configuration of receiver circuit 400 is the claimed low power
`
`mode. See Ex 2004 at 126:2–15.
`
`
`
` To cause the non-idle detector to enable the full processing mode of 47.
`
`the receiver circuit 400, Yamano explains that “the transmitter circuit transmits a
`
`
`
`23
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`
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`Declaration of Douglas A. Chrissan, Ph.D.
`IPR2016-01466
`
`predetermined non-idle state signal to indicate [to the receiver] that packet data is
`
`about to be transmitted, and then transmits the packet data.” Ex. 1006 at 13:56–59.
`
`
`
` Yamano describes three different schemes for utilizing the non-idle 48.
`
`detector 401 to facilitate the burst mode protocol and enable the full processing
`
`mode of the receiver circuit 400. See Ex. 1006 at 14:18–19. In each of the
`
`schemes, Yamano explains that non-idle detector 401, upon detecting the non-idle
`
`state signal transmitted by the far end transmitter to signal the presence of packet
`
`data, enables the full processing mode of the receiver circuit 400 by enabling the
`
`previously disabled portions of receiver circuit 400. As previously stated, after
`
`transmitting the non-idle state signal, far end transmitter transmits the packet data.
`
`That packet data is then received and demodulated by receiver circuit 400 that is
`
`now operating in full processing mode. Yamano explains that “[a]fter the packet
`
`data has been received, non-idle detector [401] detects the a
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