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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
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`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`
`
`Case IPR2016-01379
`Patent 6,197,696 B1
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`PETITIONER’S UPDATED EXHIBIT LIST
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`IPR2016-01379
`Patent No. 6,197,696
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`In accordance with 37 C.F.R. § 42.63(e), Petitioner hereby submits a current
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`listing of Taiwan Semiconductor Manufacturing Company, Ltd.’s exhibits to
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`counsel for Patent Owner.
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`LIST OF EXHIBITS
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`Exhibit No.
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`Description
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`Previously
`Filed
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`Exhibit 1001 U.S. Patent No. 6,197,696 to Aoi et al.
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`Exhibit 1002 Expert Declaration of Dr. Bruce W. Smith,
`Ph.D.
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`Exhibit 1003 U.S. Patent No. 3,617,824 to Shinoda et al.
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`Exhibit 1004 U.S. Patent No. 3,838,442 to Humphreys.
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`Exhibit 1005 U.S. Patent No. 6,140,226 to Grill et al.
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`Exhibit 1006 U.S. Patent No. 5,635,423 to Huang et al.
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`Exhibit 1007 U.S. Patent No. 5,741,626 to Jain et al.
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`Exhibit 1008 C. Akrout et al., “A 480-MHz Microprocessor
`in a 0.12μm Leff CMOS Technology with
`Copper Interconnects,” IEEE J. of Solid-State
`Circuits, Vol. 33, no. 11 (November 1998).
`
`Exhibit 1009
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`J.N. Burghartz et al., “Monolithic Spiral
`Inductors Fabricated Using a VLSI Cu-
`Damascene Interconnect Technology and
`Low-Loss Substrates,” International Electron
`Devices Meeting (December 1996).
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`Exhibit 1010 U.S. Patent No. 6,100,184 to Zhao et al.
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`x
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`x
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`x
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`x
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`IPR2016-01379
`Patent No. 6,197,696
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`Exhibit No.
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`Description
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`Previously
`Filed
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`x
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`x
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`x
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`x
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`x
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`x
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`x
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`x
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`x
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`x
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`Served only.
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`Served only.
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`Exhibit 1011 U.S. Patent No. 6,103,616 to Yu et al.
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`Exhibit 1012 File History of U.S. Patent No. 6,197,696 to
`Aoi et al.
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`Exhibit 1013
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`Japanese Patent Application No. 10-079371
`to Aoi.
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`Exhibit 1014 Certified Translation of Japanese Patent
`Application No. 10-079371 to Aoi.
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`Exhibit 1015
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`Japanese Patent Application No. 11-075519
`to Aoi.
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`Exhibit 1016 Certified Translation of Japanese Patent
`Application No. 11-075519 to Aoi.
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`Exhibit 1017 U.S. Provisional Patent Application No.
`60/071,628.
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`Exhibit 1018 U.S. Patent No. 5,592,024 to Aoyama et al.
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`Exhibit 1019 U.S. Patent No. 5,920,790 to Wetzel et al.
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`Exhibit 1020 Transcript of Teleconference with the Board,
`dated November 16, 2016.
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`Exhibit 1021
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`http://ieeexplore.ieee.org/xpl/ mostRecentIssu
`e.jsp?punumber=4251
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`Exhibit 1022
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`“International Electron Devices Meeting.
`Technical Digest, Technical Digest of the
`International Electron Devices Meeting from
`December 8–11, 1996”
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`IPR2016-01379
`Patent No. 6,197,696
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`Exhibit No.
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`Description
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`Exhibit 1023 Burghartz et al., “Monolithic spiral inductors
`fabricated using a VLSI Cu-damascene
`interconnect technology and low-loss
`substrates”
`
`Exhibit 1024
`
`http://ieeexplore.ieee.org/xpl/tocresult.jsp?isn
`umber=15684
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`Exhibit 1025 G. Gerosa, “Introduction To The Digital
`Section, Publication Year: 1998,” IEEE
`Journal of Solid-State Circuits, Vol. 33, No.
`11, Nov. 1998
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`Exhibit 1026
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`J. Dreibelbis, “Introduction to the memory
`section, Publication Year: 1998,” IEEE
`Journal of Solid-State Circuits, Vol. 33, No.
`11, Nov. 1998
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`Exhibit 1027 L. E. Thon, “Introduction To The Signal
`Processing Section, Publication Year: 1998,”
`IEEE Journal of Solid-State Circuits, Vol. 33,
`No. 11, Nov. 1998
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`Exhibit 1028
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`http://ieeexplore.ieee.org/xpl/ tocresult.jsp?isn
`umber=15684&filter%3DAND%28p_IS_Nu
`mber%3A15684%29&pageNumber=2
`
`Exhibit 1029 C. Akrout et al., “A 480-MHz RISC
`microprocessor in a 0.12-μm Leff CMOS
`technology with copper interconnects,” IEEE
`Journal of Solid-State Circuits, Vol. 33, No.
`11, Nov. 1998
`
`Previously
`Filed
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`Served only.
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`Served only.
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`Served only.
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`Served only.
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`Served only.
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`Served only.
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`Served only.
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`Exhibit 1030 Declaration of J. Preston Long
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`Served only.
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`IPR2016-01379
`Patent No. 6,197,696
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`Exhibit No.
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`Description
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`Previously
`Filed
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`Exhibit 1031 Excerpts from James D. Plummer et al.,
`“Silicon VLSI Technology: Fundamentals,
`Practice, and Modeling” (2000).
`
`Exhibit 1032 Excerpts from C.Y. Chang & S. M. Sze,
`“ULSI Technology” (1996).
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`Exhibit 1033 Excerpts from S. Wolf & R.N. Tauber,
`“Silicon Processing for the VLSI Era: Volume
`1: Process Technology” (1986).
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`Exhibit 1034 U.S. Patent No. 5,091,047 to Cleeves et al.
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`Exhibit 1035 U.S. Patent No. 6,287,973 to Aoi et al.
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`Exhibit 1036 U.S. Patent No. 4,560,436 to Bukhman et al.
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`Exhibit 1037 U.S. Patent No. 6,091,081 to Matsubara et al.
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`Exhibit 1038 U.S. Patent No. 4,473,437 to Higashikawa et
`al.
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`Exhibit 1039 U.S. Patent No. 5,880,018 to Boeck et al.
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`Exhibit 1040 U.S. Patent No. 4,832,789 to Cochran et al.
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`Exhibit 1041 U.S. Patent No. 4,855,252 to Peterman et al.
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`Exhibit 1042 U.S. Patent No. 5,786,276 to Brooks et al.
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`Exhibit 1043 U.S. Patent No. 5,756,216 to Becker et al.
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`Exhibit 1044 U.S. Patent No. 5,821,168 to Jain.
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`Exhibit 1045
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`J.M. Moran & D. Maydan, “High Resolution,
`Steep Profile Resist Patterns,” J. Vac. Sci. &
`Tech., vol. 16, no. 6 (Nov./Dec. 1979).
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`IPR2016-01379
`Patent No. 6,197,696
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`Exhibit No.
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`Description
`
`Previously
`Filed
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`Exhibit 1046 M.M. O’Toole et al., “Linewidth Control in
`Projection Lithography Using a Multilayer
`Resist Process,” IEEE Transactions on
`Electron Devices, vol. ED-28, no. 11 (Nov.
`1981).
`
`Exhibit 1047 E. Bassous et al., “A Three-Layer Resist
`System for Deep U.V. and RIE
`Microlithography on Nonplanar Surfaces,” J.
`Electrochem. Soc.: Solid-State Sci. & Tech.
`(Feb. 1983).
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`Exhibit 1048 Transcript of the Deposition of Dr. A. Glew
`(June 30, 2017).
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`Exhibit 1049 U.S. Provisional Patent Application No.
`60/071,628 (with line numbering appended).
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`Exhibit 1050 Expert Declaration of Dr. Bruce W. Smith,
`Ph.D. in Support of Petitioner’s Reply
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`Petitioner hereby certifies that copies of all listed documents above have
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`Respectfully submitted,
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`been served on counsel for Godo Kaisha IP Bridge.
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`Dated: July 21, 2017
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`By: /Darren M. Jiron/
`Darren M. Jiron, Lead Counsel
`Reg. No. 45,777
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`Counsel for Petitioner
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`IPR2016-01379
`Patent No. 6,197,696
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`CERTIFICATE OF SERVICE
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`Pursuant to 37 C.F.R. § 42.6(e), this is to certify that I caused to be served
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`true and correct copies of the PETITIONER’S UPDATED EXHIBIT LIST and
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`TSMC Exhibits 1031-1050 by electronic mail, this 21st day of July, 2017, on
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`counsel of record for the Patent Owner as follows:
`
`Andrew N. Thomases
`andrew.thomases@ropesgray.com
`
`J. Steven Baughman
`sbaughman@paulweiss.com
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`Jordan M. Rossen
`jordan.rossen@ropesgray.com
`
`James L. Davis, Jr.
`james.l.davis@ropesgray.com
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`IPBridgeTSMCPTABService@ropesgray.com
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`Dated: July 21, 2017
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`By: /Lauren K. Young/
`Lauren K. Young
`Litigation Legal Assistant
`FINNEGAN, HENDERSON, FARABOW,
`GARRETT & DUNNER, L.L.P.
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