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`5,821,168
`[11] Patent Number:
`[19]
`Unlted States Patent
`
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`Jain
`[45] Date of Patent:
`Oct. 13, 1998
`
`U8005821168A
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`54
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`
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`PROCESS FOR FORMINGA
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`SEMICONDUCTOR DEVICE
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`[75]
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`Inventor: Ajay Jain, Austin, TeX.
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`
`'
`F'l
`N'
`T
`“F
`A h An
`1 ms
`ungsten— itrogen
`orming
`onymous,
`ut or
`
`
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`
`
`Using Plasma Etching”, Research Disclosure 298087, Feb.
`
`
`
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`
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`1989 and Abstract.
`
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`.
`.
`.
`Mikagi, et al. “Barrier Metal Free Copper Damascene Inter-
`
`
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`connection Technology Using Atmospheric Copper Reflow
`and Nitrogen Doping in SiOF Film”, IEEE, International
`
`
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`
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`
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`Electron Devicese, Meeting, pp. 395—468 (1996).
`Bai, et al., “Effectiveness and Reliability of Metal Diffusion
`
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`Barriers for Copper Interconnects”, Mat. Res. Soc. Symp.
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`Proc, vol. 403, pp. 501—506 (1996).
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`[73] Assignee: Motorola, Inc” Schaumburg, 111.
`..
`.
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`[21] Appl NO . 895 017
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`[22]
`Flled'
`Jul' 16’ 1997
`Int. Cl.6 ................................................... .. H01L 21/00
`[51]
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`[52] US. Cl.
`............................ .. 438/692; 216/18; 216/38;
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`[58] Field of Search 216/88; 438/627; 4382632 Primary Examiner—William Powell
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`................................... ..
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`A
`F. _G
`Art
`t
`R. M
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`438/628, 633, 692, 693, 697, 748; 216/18,
`omey’
`eorge
`gen” or m"
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`38, 39, 56, 88
`[57]
`ABSTRACT
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`eyer
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`[56]
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`References Cited
`
`5 332 691
`
`5:604:158
`
`5,741,626
`
`
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`
`
`U~S~ PATENT DOCUMENTS
`.................... .. 437/192
`7/1994 Kinoshita et al.
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`
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`2/1997 Cadien .............................. .. 438/692 X
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`
`
`4/1998 Jain et a1,
`.
`
`
`
`OTHER PUBLICATIONS
`
`
`
`Ting et al. “The Use of Titanium—Based Contact Barrier
`
`
`
`
`
`
`
`Layers in Silicon Technology”, Thin Solid Films, 96, Elec-
`
`
`
`
`
`
`
`
`tronics and Optics, pp. 327—345 (1982).
`
`
`
`
`
`
`Vogt et al. “Plasma Deposited Dielectric Barriers for Cu
`
`
`
`
`
`
`
`
`Metallization”, Electrochemical Society Proceedings, vol.
`
`
`
`
`
`96—12, pp. 613—622 (1996).
`
`
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`
`
`
`
`
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`
`
`Aprocess for forming a semiconductor device (68) in which
`an insulating layer (52) is nitrided and then covered by a thin
`
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`adhesion layer (58) before depositing a composite copper
`
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`layer (62) This PromsS does not require a separate difquiOH
`
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`
`
`
`
`
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`
`
`barrier as a portion of the insulating layer (52) has been
`converted to form a diffusion barrier film (56). Additionally,
`
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`
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`the adhesion layer (58) is formed such that it can react with
`
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`the interconnect material resulting in strong adhesion
`
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`between the composite copper layer (62) and the diffusion
`
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`barrier film (56) as well as allow a more continuous inter-
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`connect and via structure that is more resistant to electromi-
`
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`gration.
`
`21 Claims, 5 Drawing Sheets
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`NITRIDING THE EXPOSED SURFACES
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`OF THE INSULATING LAYER
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` 10
`FORMING A DUAL IN-LAID
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`OPENING TO AN UNDERLYING
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`COPPER INTERCONNECT
`11
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`Page 1 Of 10
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`DEPOSIT THIN SILICON ADHESION
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`LAYER
`I
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`14
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`DEPOSIT COPPER SEED LAYER
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`PLATE COPPER
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`POLISH COPPER TO FORM
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`INTERCONNECTS
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`7
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`16
`17
` 19
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`TSMC Exhibit 1044
`
`TSMC v. IP Bridge
`IPR2016-01379
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`Page 1 of 10
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`TSMC Exhibit 1044
`TSMC v. IP Bridge
`IPR2016-01379
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`US. Patent
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`Oct. 13, 1998
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`Sheet 1 0f 5
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`5,821,168
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`‘
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`10
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`FORMING A DUAL IN-LAID ’
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`OPENING TO AN UNDERLYING
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`COPPER INTERCONNECT
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`NITRIDING THE EXPOSED SURFACES
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`OF THE INSULATING LAYER
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` 11
` 14
` 16
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`DEPOSIT THIN SILICON ADHESION
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`LAYER
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`DEPOSIT COPPER SEED LAYER
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`PLATE COPPER
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`POLISH COPPER TO FORM
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`INTERCONNECTS
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`V
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`A
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`JZ7ZZW(E?E_IF
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`17
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`19
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`JE7DIIC2142?
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`5,821,168
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`saw
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`4
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`FIG. 3
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`FIG. 4
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`US. Patent
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`5,821,168
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`US. Patent
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`Page 5 0f 10
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`5,821,168
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`58
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`56
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`FIG.10
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`5,821,168
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`1
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`PROCESS FOR FORMING A
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`SEMICONDUCTOR DEVICE
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`FIELD OF THE INVENTION
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`This invention relates in general to processes for forming
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`semiconductor devices with interconnects, and more
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`particularly, processes for forming semiconductor devices
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`with inlaid interconnects.
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`BACKGROUND OF THE INVENTION
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`Currently, semiconductor devices are being scaled to very
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`small dimensions, such as less than 0.25 microns. As the
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`device sizes decrease, the contact openings are also becom-
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`ing narrower. Part of the problem with semiconductor
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`devices that operate at high speeds is that they essentially
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`require use of low resistance copper interconnects.
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`However, copper diffuses through most oxides resulting in
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`dielectric breakdown and increased line-to-line current leak-
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`ages. Therefore, use of copper requires a barrier layer to be
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`placed between the copper and the adjacent insulating layer.
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`The barrier layer needs to be formed along the walls and
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`bottom of the contact openings. When the size of the contact
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`openings becomes too small, the percentage of the cross-
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`sectional area occupied by the barrier layer becomes too
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`large. As the ratio of barrier layer to copper increases, the
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`effective resistance of the interconnect
`increases. This
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`greater resistance is adverse to forming a high speed semi-
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`conductor device.
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`One prior art attempt to solve the problem is to nitridize
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`a silicon oxyfluoride layer and deposit a copper layer over
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`the nitrided layer. This process has problems related to
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`adhesion. Copper does not sufficiently adhere to the nitrided
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`silicon oxyfiuoride. Poor adhesion between the nitrided
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`silicon oxyfluoride and copper is a serious manufacturing
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`concern because it results in peeling of copper during polish
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`steps. Furthermore, this process uses a high temperature
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`copper refiow (higher than 400 degrees Celsius) which
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`requires long thermal cycling. Consequently, multi-level
`copper cannot be fabricated using this process because of the
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`poor adhesion or high temperature refiow.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention is illustrated by way of example
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`and not limitation in the accompanying figures, in which like
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`references indicate similar elements, and in which:
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`FIG. 1 includes a process flow diagram for an embodi-
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`ment of the present invention;
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`FIG. 2 includes an illustration of a cross-sectional view of
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`a portion of a semiconductor device substrate after forming
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`a first interconnect level;
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`FIG. 3 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 2 after forming an insulating layer;
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`FIG. 4 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 3 after forming openings;
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`FIG. 5 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 4 after converting a portion of the
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`insulating layer into a nitrided oxide portion;
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`FIG. 6 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 5 after forming a silicon adhesion layer;
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`FIG. 7 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 6 after depositing a copper seed layer;
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`FIG. 8 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 7 after plating a copper layer over the
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`copper seed layer;
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`FIG. 9 includes an illustration of a cross-sectional view of
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`the substrate of FIG. 8 after polishing the silicon adhesion
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`and copper layers; and
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`FIG. 10 includes an illustration of a cross-sectional view
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`of the substrate of FIG. 9 after forming a substantially
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`completed device.
`Skilled artisans appreciate that elements in the figures are
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`illustrated for simplicity and clarity and have not necessarily
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`been drawn to scale. For example, the dimensions of some
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`of the elements in the figures are exaggerated relative to
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`other elements to help to improve understanding of
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`embodiment(s) of the present invention.
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`DETAILED DESCRIPTION
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`Aprocess has been developed in which an insulating layer
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`is nitrided and then covered by a thin adhesion layer before
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`depositing a composite copper layer. This invention has the
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`benefit of not requiring a separate diffusion barrier as a
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`portion of the insulating layer has been converted to form a
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`diffusion barrier film. Additionally,
`the adhesion layer is
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`formed such that it can react with the interconnect material
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`resulting in strong adhesion between the composite copper
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`layer and the diffusion barrier film as well as allow a more
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`continuous interconnect and via structure that is more resis-
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`tant
`to electromigration. The present
`invention is better
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`understood with the detailed description of the embodiments
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`that follow.
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`FIG. 1 includes a process flow diagram for an embodi-
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`ment of the present invention. A semiconductor device has
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`been processed to the point at which a first level of inter-
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`connects has been formed. Typically,
`this first
`level of
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`interconnects includes copper. One or more insulating films
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`is deposited to form an insulating layer that is then patterned
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`to form a dual inlaid opening that extends to the underlying
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`copper interconnect, as seen in step 10. After forming the
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`opening, the exposed surfaces of the insulating layer are then
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`exposed to a nitrogen plasma which converts a portion of the
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`insulating layer into a nitrided oxide film that is a diffusion
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`barrier layer for copper, as seen in step 11. After the nitriding
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`step, a thin silicon adhesion layer is deposited over all of the
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`exposed surfaces, as seen in step 14. A copper seed layer is
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`deposited by physical vapor deposition over the silicon
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`adhesion layer, as seen in step 16. The substrate is removed
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`from the tool, and a thick copper layer is plated over the
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`copper seed layer, as seen in step 17. After plating, the
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`substrate is then polished so that the copper only lies within
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`the openings to form the dual inlaid structures that include
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`via and interconnect portions, as seen in step 19.
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`This process will be described in more detail in reference
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`to the cross-sectional
`illustrations that
`follow. FIG. 2
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`includes an illustration of a cross-sectional view of a portion
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`of a semiconductor device substrate 12 after forming a first
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`level of interconnects 28. The semiconductor device sub-
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`strate 12 is any substrate used to form a semiconductor
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`device. The semiconductor device substrate 12 includes field
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`isolation regions 46 and doped regions 44 that are formed
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`from a portion of the substrate 12. A gate dielectric layer 42
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`and a gate electrode 40 overlie the substrate 12 and a portion
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`of the doped regions 44. An interlevel dielectric (ILD) layer
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`36 is formed over substrate 12 and planarized. The ILD layer
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`36 is patterned to include contact openings in which con-
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`ductive plugs 38 are formed. A first insulating layer 30 is
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`formed and patterned to include interconnect channels in
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`which interconnects 28 are formed.
`In this particular
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`embodiment,
`the interconnects 28 include copper, but in
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`other embodiments could include tungsten, aluminum, or
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`the like.
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`5,821,168
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`3
`A second insulating layer 52 is then formed over the
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`substrate 12 and interconnects 28 as illustrated in FIG. 3.
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`This insulating layer 52 includes four discrete insulating
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`films. The lower insulating film 48 is a passivation and
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`anti-reflective coating made of plasma enhanced nitride
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`having a thickness in a range of approximately 200—700
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`angstroms. An oxide film 26 is then deposited over the
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`plasma-enhanced nitride film. The oxide film typically has a
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`thickness in the range of 4,000—10,000 angstroms. An
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`optional etch-stop film 50 made of silicon oxynitride is then
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`formed over the oxide film 26 and has a thickness in the
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`range of 200—700 angstroms. This film 50 is also an anti-
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`reflective coating. A second oxide film 54 is formed over the
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`etch-stop film 50 to a thickness in a range of approximately
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`5,000—6,000 angstroms. The oxide films 26 and 54 can be
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`formed using tetraethylorthosilicate (TEOS), silicon
`oxyfiuoride, low k dielectrics, or the like. The TEOS may be
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`run in combination with oxygen gas in order to keep carbon
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`incorporation at an acceptable level. As used in this
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`specification, low k dielectrics low k dielectrics having a
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`dielectric constant
`less than that of silicon dioxide
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`(approximately 3.9). Some examples of low k dielectrics
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`include polyimides, fiuorocarbons (e.g., TeflonTM), paralene,
`or the like.
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`The insulating layer 52 is then patterned using conven-
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`tional techniques to form the dual inlaid openings as illus-
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`trated in FIG. 4. These dual inlaid openings include via
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`portions 70 and interconnect channel portions 72. The via
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`portions 70 contact the interconnects 28 and the interconnect
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`channels 72 are routed between the vias and other circuit
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`elements. After patterning the insulating layer 52 to form the
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`dual inlaid openings, the exposed surfaces of the oxide layer
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`are then converted to silicon oxynitride diffusion barrier
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`portions 56, as illustrated in FIG. 5, by performing a plasma
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`nitriding step.
`this step is performed
`In one particular embodiment,
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`using relatively high power plasma in a range of approxi-
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`mately 500—1,500 watts. Typically, the plasma includes a
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`nitrogen-containing compound, such as molecular nitrogen,
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`ammonia, or the like. Argon is used to stabilize the plasma.
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`This step is typically performed in a range of approximately
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`1—3 minutes. The step converts approximately 200—300
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`angstroms of the exposed oxide films into the silicon oxyni-
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`tride portions. The plasma processing is performed at a
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`pressure of approximately 10 millitorr to approximately 5
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`torr. Typically, the pressure is in a range of approximately
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`500—2,000 millitorr. Lower pressures may not properly
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`convert the sidewall portions of the insulating layer 52 into
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`substantially thick silicon oxynitride portions. Therefore,
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`higher pressures are typically preferred, but at too high of a
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`pressure, the plasma may become unstable. In an alternate
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`embodiment, a boron-containing species, such as diborane
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`or the like, may be used to form the diffusion barrier portions
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`that include silicon boroxide.
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`As illustrated in FIG. 6, a silicon adhesion layer 58 is then
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`formed over the nitrided oxide portions 56 and has a
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`thickness in a range of approximately 50—150 angstroms.
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`Typically,
`the adhesion layer 58 includes silicon, silicon
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`germanium, germanium, or
`the like.
`In alternate
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`embodiments, the adhesion layer 58 can include magnesium,
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`titanium, or the like. Generally, the adhesion layer 58 needs
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`to react with the subsequently formed copper layer to
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`provide a strong adhesion between the copper and the
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`nitrided oxide portions 56. Other benefits of the reaction will
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`be explained later in this detailed description.
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`The deposition parameters for the silicon adhesion layer
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`58 include using silane at a flow rate in a range of approxi-
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`Page 8 0f 10
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`4
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`mately 50—100 standard cubic centimeters per minute. This
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`is diluted with 10 parts nitrogen for each part of silane. The
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`pressure of the deposition is typically in a range of approxi-
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`mately 50 millitorr
`to approximately 5 torr. More
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`specifically, the deposition is typically performed at a pres-
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`sure in a range of approximately 1—2 torr. The power for the
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`plasma deposition is typically in a range of approximately
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`50—150 watts. The deposition temperature ranges from room
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`(approximately 20 degrees Celsius) to over 400 degrees
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`Celsius. The deposition rate of the amorphous silicon should
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`be relatively slow so that its thickness can be controlled. The
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`deposition time for the silicon layer 58 is in a range of
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`approximately 5—10 seconds.
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`As illustrated in FIG. 7, a copper seed layer 60 is
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`deposited by physical vapor deposition over the adhesion
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`layer 58 using a collimated sputtering chamber. A continu-
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`ous film is formed along all portions of the opening includ-
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`ing its walls. In many embodiments, the thickness of this
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`layer is in a range of approximately 50—150 angstroms along
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`the wall near the very bottom of the via portion of the
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`opening. In order to attain this, the copper seed layer 60 is
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`deposited to a thickness of approximately 3,000 angstroms
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`over the insulating layer 52. The substrate is then removed
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`from the tool at which time the vacuum is broken. Note that
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`between the time of the barrier film 56 formation through the
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`copper seed layer 60 formation, the substrate has been under
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`continuous vacuum.
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`The substrate is then taken to an electroplating system
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`where 6,000—15,000 angstroms of copper is plated over the
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`copper seed layer 60, as seen in FIG. 8. The copper seed
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`layer 60 can no longer be distinguished from the electro-
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`plated copper layer, thus forming a composite copper layer
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`62 overlying the adhesion layer 58. As illustrated in FIG. 9,
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`the portions of the adhesion layer 58 and the composite
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`copper layer 62 that overlie the uppermost surface of the
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`insulating layer 52 are then removed by chemical-
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`mechanical polishing. At this point, dual inlaid structures 74
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`have been formed that include both via portions and inter-
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`connect channel portions, which allows electrical connec-
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`tions to be made to various parts of the semiconductor
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`device.
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`As seen in FIG. 10, following the formation of the dual
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`inlaid structures 74, a passivation layer 66 is then formed
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`over the semiconductor device 68 including the dual inlaid
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`structures 74. At this point in time, a substantially completed
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`semiconductor device 68 has been formed. Optionally, other
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`interconnect levels similar to the one just described could be
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`formed overlying the dual inlaid structures 74, but are not
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`illustrated in the figures.
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`The dual inlaid structures can be modified to be a single
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`inlaid interconnect structure in which only interconnect
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`channels are formed. For example, the process previously
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`described could be modified to apply to the upper insulating
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`layer 30 of the first level interlevel dielectric to form the
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`interconnect channels for
`interconnects 28.
`In this
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`embodiment, the upper insulating layer 30 would be nitrided
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`to convert portions of this layer 30 into diffusion barrier
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`portions (not shown in the figures) similar to the diffusion
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`barrier portions 56. A silicon adhesion layer, similar to
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`adhesion layer 58, would then be formed over the diffusion
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`barrier portions, followed by a copper seed layer. Copper
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`would then be plated over the copper seed layer to form a
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`composite copper layer. The silicon adhesion layer overly-
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`ing the nitrided portions of the upper insulating layer 30 and
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`the composite copper layer are not illustrated in the figures.
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`The bottom of the interconnect channel 28 would now
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`contact the conductive plug 38 and lie over the ILD layer 36.
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`Page 8 of 10
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`5,821,168
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`5
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`After forming this single inlaid structure, a passivation layer
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`could be formed over the upper insulating layer 30 and the
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`interconnects 28. Alternatively, additional ILD layers and
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`interconnect levels could be formed before depositing the
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`passivation layer.
`In still other embodiments, the copper seed layer 60 and
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`electroplated copper layer may be replaced by a single
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`copper layer. This may be achieved by plasma vapor
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`deposition, chemical vapor deposition, or the like. Further,
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`other materials can replace copper for the interconnect
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`materials. Those other materials, for example, gold or the
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`like, can adversely interact with oxygen or have species that
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`diffuse through oxide layers.
`The present invention includes benefits over the prior art
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`methods. More specifically,
`the present invention has an
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`adhesion layer 58 that allows the composite copper layer 62
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`to adhere to the adhesion layer 58 that adheres to the nitrided
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`oxide portions 56. In this manner, the polishing conditions
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`do not have to be tightly controlled to reduce the likelihood
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`of peeling. Additionally,
`the process does not require a
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`titanium nitride or other metallic nitride barrier layer. In
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`electromigration tests, such a structure with the metallic
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`nitride barrier layer typically prevents copper from flowing
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`or migrating between the interconnect and via portion of the
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`dual inlaid structure. This can cause the copper within the
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`via portion to deplete, thereby creating a void and rendering
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`the interconnect structure as an electrical open. With an
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`embodiment of the present invention, the adhesion layer is
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`selected so that the adhesion layer can react with the copper
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`layer. In this manner, the copper layer will react with the
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`adhesion layer at the bottom of the opening, allowing the
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`copper to migrate between the interconnect and the via
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`portion of the dual inlaid structure. Therefore, some embodi-
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`ments of the present
`invention should make the wiring
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`system more robust and less likely to have a failure due to
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`electromigration reasons.
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`Another benefit over the prior art is that if a supplemen-
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`tary diffusion layer is used, it can be made thinner because
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`the diffusion barrier portions 56 are being formed from a
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`portion from the insulating layer 52. By nitriding the insu-
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`lating layer to form the diffusion barrier portions 56, a
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`supplementary diffusion barrier layer, such as a thin titanium
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`nitride layer and the like, may be formed along the walls. In
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`this manner, the titanium nitride layer would be no more
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`than 200 angstroms thick near the bottom of the contact
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`openings, compared to prior art methods which would have
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`a titanium nitride barrier layer of at least 300 angstroms
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`along the walls of the contact opening near the bottom of the
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`contact opening. As the contact openings continue to
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`decrease in size, the thickness of this barrier layer should
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`also decrease in order for the resistance through the via
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`portion to remain acceptable.
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`Another benefit of the embodiments of the present
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`invention, is that they can be used to form a copper layer
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`with larger copper grains. The larger copper grains are more
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`resistant to electromigration compared to smaller grains as
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`seen with a PVD copper system that has been refiowed.
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`Additionally, the plating of the copper layer can be con-
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`trolled better and be formed such that no voids are formed
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`within the dual inlaid structure. Also, the upper surface after
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`plating can be relatively planar compared to the PVD system
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`followed by a copper reflowing step.
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`Still another benefit of the embodiments of the present
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`invention is that
`they can be performed using existing
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`technology without having to develop a marginal process or
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`use exotic materials.
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`Page 9 0f 10
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`6
`the invention has been
`In the foregoing specification,
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`described with reference to specific embodiments. However,
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`one of ordinary skill in the art appreciates that various
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`modifications and changes can be made without departing
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`from the scope of the present invention as set forth in the
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`claims below. Accordingly, the specification and figures are
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`to be regarded in an illustrative rather than a restrictive
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`sense, and all such modifications are intended to be included
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`within the scope of present invention. In the claims, means-
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`plus-function clause(s), if any, cover the structures described
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`herein that perform the recited function(s). The mean-plus-
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`function clause(s) also cover structural equivalents and
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`equivalent structures that perform the recited function(s).
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`I claim:
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`1. A process for forming a semiconductor device com-
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`prising the steps of:
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`forming a patterned insulating layer over a substrate,
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`wherein the patterned insulating layer includes an
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`opening;
`converting a portion of the patterned insulating layer to a
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`barrier film;
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`depositing an adhesion layer over the barrier film; and
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`forming a conductive metal-containing layer over the
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`adhesion layer.
`2. The process of claim 1, wherein the step of forming the
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`patterned insulating layer is performed such that the pat-
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`terned insulating layer is formed using tetraethylorthosili-
`cate.
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`3. The process of claim 1, wherein the step of converting
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`comprises exposing the insulating layer
`to a material
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`selected from a group consisting of a nitrogen-containing
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`species and a boron-containing species.
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`4. The process of claim 3, wherein the step of converting
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`is performed using a plasma.
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`5. The process of claim 4, wherein the step of converting
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`uses the plasma at a power in a range of approximately 500
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`watts to approximately 1500 watts.
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`6. The process of claim 1, wherein the step of converting
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`is performed such that the barrier film has a thickness in a
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`range of approximately 200 angstroms to approximately 300
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`angstroms.
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`7. The process of claim 1, wherein the step of depositing
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`is performed such that the adhesion layer includes a material
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`selected from a group consisting of silicon, magnesium, and
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`titanium.
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`8. The process of claim 7, wherein the step of depositing
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`is performed such that the adhesion layer has a thickness in
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`a range of approximately 50 angstroms to approximately
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`150 angstroms.
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`9. The process of claim 1, wherein the step of forming the
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`conductive metal-containing layer is performed such that the
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`conductive metal-containing layer is at least approximately
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`half copper.
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`10. The process of claim 9, wherein the step of forming
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`the conductive metal-containing layer comprises the steps of
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`depositing a first copper layer and plating a second copper
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`layer over the first copper layer, wherein the second copper
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`layer is thicker than the first copper layer.
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`11. The process of claim 10, further comprising the step
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`of removing the first and second copper layers that overlie
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`an uppermost surface of the patterned insulating layer.
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`12. The process