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`[19]
`United States Patent
`Patent Number:
`4,855,252
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`
`
`
`
`Date of Patent:
`[45]
`Aug. 8, 1989
`
`
`
`Peterman et a1.
`
`[11]
`
`
`[54] PROCESS FOR MAKING SELF-ALIGNED
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`
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`CONTACTS
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`
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`FOREIGN PATENT DOCUMENTS
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`
`[75]
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`Inventors: Steven Peter-man; David
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`Stauasolovich, both of Manassas, Va.
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`[73] Assignee:
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`
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`International Business Machines
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`Corporation, Armonk, NY.
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`[21] App]. No.: 234,780
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`[22] Filed:
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`Aug. 22, 1988
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`[51]
`Int. CL4 ........................................... .. H01L 21/88
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`[52] US. Cl. .................................... 437/189; 437/194;
`437/228
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`[58] Field of Search ............... 437/189, 190, 194, 228,
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`437/189, 194; 148/DIG. 75
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`
`[56]
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`References Cited
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`
`U.S. PATENT DOCUMENTS
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`
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`4,315,984 2/1982 Okazaki et a1.
`..................... 437/187
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`4,392,298 7/1983 Barker et al._ .....
`...... 437/194
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`4,512,073 4/1985 Hsu ........................... 29/571
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`5/1985 Aoyama et al.
`...... 437/228
`4,520,041
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`4,523,976
`6/1985 Bukhman ... ...
`. ..... 156/643
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`4,544,445 10/1985 Jeuch et a1.
`...... 156/643
`
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`9/1986 Hulseweh
`.. 437/199
`4,614,021
`
`
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`
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`4,646,426 3/1987 Sasaki ........
`29/571
`4,661,204 4/1987 Mathur et a1.
`.. 437/189
`
`
`
`
`
`.. ...... 437/20
`4,700,465 10/1987 Sirkin ..... .. .....
`4,797,375
`1/ 1989 Brownell ............................. 437/189
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`0096752
`6/1983 Japan ................................... 437/ 194
`
`
`0192350 1 1/1983 Japan
`.. 437/194
`
`
`3/1984 Japan
`0055038
`.. 437/194
`
`
`
`
`0236248 11/1985 Japan
`.. 437/189
`0246649 12/1985 Japan
`.. 437/194
`
`
`5/1986 Japan
`0094345
`.. 437/194
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`
`0187346
`8/1986 Japan ................................. .. 437/ 194
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`
`
`
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`Primary Examiner—Brian E. Hearn
`
`
`
`Assistant Examiner—Tuan Nguyen
`Attorney, Agent, or Firm—Jesse L. Abzug
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`
`
`ABSTRACT
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`
`[57]
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`A process for making metal contacts and interconnec-
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`tion lines which are self-aligned to each other is dis-
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`closed. After semiconductor devices are formed and an
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`insulating/planarizing layer is deposited, a layer of
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`polyimide is deposited. A pattern of trenches into which
`the metal interconnection lines will be deposited is
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`formed in the polyimide layer. Next, a pattern of
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`contacts to the underlying semiconductor devices is
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`formed in a photoresist layer. This pattern of contacts is
`subsequently etched into the insulating/planarizing
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`layer. Since both the patterned photoresist layer and the
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`patterned polyimide layer are used as etch masks, the
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`contact windows through the insulating/planarizing
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`layer and the trenches in the polyimide layer will be
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`aligned with respect to each other. After metal deposi-
`tion, the metal contacts and interconnection lines will
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`be self-aligned.
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`9 Claims, 2 Drawing Sheets
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`Page 1 of 6
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`TSMC Exhibit 1041
`
`TSMC v. IP Bridge
`IPR2016-01379
`
`Page 1 of 6
`
`TSMC Exhibit 1041
`TSMC v. IP Bridge
`IPR2016-01379
`
`

`

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`Aug. 8, 1989
`US. Patent
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`FIG. I.
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`(PRIOR ART)
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`Sheet 1 of2
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`4,855,252
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`FIG. 2.
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`Page 2 of 6
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`US. Patent
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`Aug. 8, 1989
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`Sheet 2 of2
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`F[6. 6’.
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`4,855,252
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`l
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`llllllllu
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`- POLYIMIDE ONLY E- CA RESIST ONLY
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`CA RESIST 0N
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`POLYIMIDE
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`III- CONTACT AREA
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`Page 3 0f 6
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`Page 3 of 6
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`1
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`PROCESS FOR MAKING SELF-ALIGNED
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`CONTACI'S
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`4,855,252
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`5
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`10
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`2
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`f. depositing a layer of metal which formed the
`contact studs and interconnect wiring.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The foregoing and other advantages of the invention
`will be more fully understood with reference to the
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`description of the preferred embodiment and with refer-
`ence to the drawings herein:
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`FIG. 1 is an exploded top View of a semiconductor
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`wafer showing metal lines and contacts as formed in the
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`prior art.
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`FIG. 2 shows an exploded top view of a semiconduc-
`tor wafer showing metal
`lines and contacts formed
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`according to the invention disclosed herein.
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`FIGS. 3—5 show cross-sectional views of a semicon-
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`ductor wafer at various processing steps according to
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`the method of this invention.
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`FIG. 6 shows an exploded top view of a metal line
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`and contact.
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`FIGS. 7—9 show cross-sectional views of a semicon-
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`ductor wafer at various stages of processing.
`DESCRIPTION OF THE PREFERRED
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`EMBODIMENT
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`Referring to FIG. 3, a semiconductor substrate is
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`shown as reference numeral 14. In the preferred em-
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`bodiment, substrate 14 is a silicon wafer, but it will be
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`understood by those skilled in the art that substrate 14
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`could be made of gallium arsenide or other substrates
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`commonly used for making integrated circuits. Previ-
`ously fabricated in substrate 14 are a plurality of semi-
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`conductor devices such as FET transistors or bipolar
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`transistors (not shown). The structures and processes
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`used to make these semiconductor devices are not part
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`of the invention herein described.
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`Overlying substrate 14 is a planarizing/insulating
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`layer 16 of borophosphosilicate glass (BPSG). The pur-
`pose of the BPSG layer 16 is to insulate the substrate 14
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`from the metal interconnect lines to be deposited in later
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`processing steps, and also to provide a planar surface
`uponrwhich the metal is to be deposited. A planar sur-
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`face is important to ensure that the brittle metal lines
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`will not be easily cracked. "To achieve this planarity, a
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`minimum thickness of 6000 Angstroms is required over
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`the highest point on the substrate 14. In alternative
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`embodiments, the insulating/planarizing layer 16 can be
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`comprised of doped or undoped silicon oxide, silicon
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`nitride, phosphosilicate glass, etc. The deposition of
`layer 16 can be by conventional atmospheric pressure
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`chemical vapor deposition (APCVD) or low pressure
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`chemical vapor deposition (LPCVD).
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`Next, a layer of polyimide 18 is formed. Liquid po-
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`lyamic acid is spun on the substrate 14 and then baked at
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`120° C. for twenty minutes; 200° C. for twenty minutes;
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`and 350° C. for twenty minutes. The final thickness of
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`the polyimide should be the approximate thickness of
`the interconnection metallurgy to be deposited, be-
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`tween 0.5 and 1.5 microns. Alternatively, any insulator
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`which has different etch characteristics from layer 16,
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`such as spun on glass or other organic compounds, can
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`be used in place of the polyimide.
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`On top of the polyimide layer 18, a 2.0 micron thick
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`layer of positive diazonovolak or other positive resist is
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`deposited. Preferably,
`the thickness of the resist 20
`should be approximately twice the thickness of the
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`polyimide layer 18. The photoresist layer 20 is then
`exposed using standard optical or x-ray lithographic
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`tools through a mask (not shown) having the intercon-
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`BACKGROUND INFORMATION
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`1. Field of the Invention
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`This process relates generally to the fabrication of
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`integrated circuits. In particular, a process for making
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`metal contacts self-aligned to interconnecting metal-
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`lurgy is described.
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`2. Background of the Invention
`As manufacturers reduce the dimensions of inte-
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`grated circuits, it is readily apparent that one of the
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`greatest barriers to achieving sub-micron geometries is
`the area allotted to alignment or overlay tolerances
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`which are required to assure adequate connections be-
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`tween metal contacts to the semiconductor devices
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`themselves and the interconnecting metallurgy. An
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`20
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`alignment or overlay tolerance allows for small errors
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`in the alignment of photomasks used for patterning
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`various layers without compromising the adequacy of
`the connections between the layers.
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`To better appreciate the problems encountered, as
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`example of a prior art metal line and contact structure is
`shown in FIG. 1. As conventionally done in semicon-
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`ductor processing, the contacts 10 to the semiconductor
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`devices are first formed, and then in subsequent process-
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`ing steps, the interconnecting metallurgy 12 is depos-
`ited. With the current limitations of conventional opti-
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`cal lithography tools, which have a standard overlay
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`error of approximately 0.45 microns, in order to ensure
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`that one micron wide lines 12 completely overlay the
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`contacts 10, it is necessary that the contacts have a
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`width of approximately 2 microns. Obviously, if one
`could eliminate the extra one micron border on the
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`contact, as shown in FIG. 2, the ability to increase the
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`maximum wiring density of metal lines 12 would be
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`greatly improved.
`OBJECTS OF THE INVENTION
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`It is therefore a principal object of this invention to
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`provide a process for making contacts that are self-
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`aligned to metal lines.
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`It is a further object of this invention to provide a
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`process for making contacts and metal lines using well-
`known semiconductOr processes which do not increase
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`process complexity.
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`SUMMARY OF THE INVENTION
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`In accordance with these objects, and others which
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`are readily apparent, a process is provided for making
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`self-aligned metal lines and contact metallurgy through
`an insulating/planarizing layer to make contact with
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`semiconductor devices previously formed. The essen-
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`tial process steps include:
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`a. depositing a layer of polyimide over the insulating
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`layer;
`b. depositing a layer of photoresist over the polymide
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`layer;
`c. lithographically defining a wiring pattern in the
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`layer of photoresist and transferring that pattern into
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`the polyimide layer;
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`d. depositing a second layer of photoresist;
`e. lithographically defining a pattern of contacts in
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`the layer of resist and transferring that pattern into the
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`insulating layer; and
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`Page 4 of 6
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`4,855,252
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`4
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`Further processing, such as insulator deposition and
`fabrication of additional layers is then performed.
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`While the invention has been disclosed with refer-
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`ence to a preferred embodiment, it would be apparent to
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`those skilled in the art that various changes to the pro-
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`cess can be made without departing from the spirit and
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`scope of the invention. Accordingly, the invention shall
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`only be limited in accordance with the following claims.
`We claim:
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`1. In an integrated circuit having a plurality of semi-
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`conductor devices fabricated on a substrate, a process
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`for interconnecting the semiconductor devices compris-
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`ing the following steps in the following order:
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`A. depositing an insulating layer over said semicon-
`ductor devices;
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`B. depositing a layer of polyimide over said insulating
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`layer;
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`C. depositing a first layer of photoresist over said
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`polyimide layer;
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`D. lithographically defining an interconnect wiring
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`pattern in said first layer of photoresist;
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`E. dry etching said interconnect wiring pattern into
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`said polyimide layer;
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`F. depositing a second layer of photoresist over said
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`patterned polyimide layer;
`G. lithographically defining a pattern of contacts in
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`said second layer of photoresist, said pattern of
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`contacts overlying said patterned polyimide layer;
`H. transferring said pattern of contacts to said insulat-
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`ing layer; and
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`I. depositing a layer of interconnect wiring, said inter-
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`connect wiring layer filling said pattern of contacts
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`in said insulating layer and said interconnect wiring
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`pattern in said polyimide layer.
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`2. The process as claimed in claim 1 including the step
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`of removing said polyimide layer after depositing said
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`interconnect wiring layer.
`3. The process as claimed in claim 1 wherein said
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`insulating layer is borophosphosilicate glass.
`4. The process as claimed in claim 1 wherein said
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`interconnect wiring layer is selected from the group
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`consisting of aluminum, copper, silicon, titanium, tung-
`sten, silver, gold or alloys or composites thereof.
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`5. The process as claimed in claim 1 wherein said
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`interconnect wiring layer is deposited by evaporation
`or sputtering.
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`6. A process for interconnecting semiconductor de-
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`vices comprising the following steps in the following
`order:
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`A. providing a semiconductor substrate having a
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`plurality of semiconductor devices formed therein;
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`B. depositing an insulating layer over said semicon-
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`ductor devices on said substrate;
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`C. depositing a thin layer of polyamic acid over said
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`insulating layer;
`D. curing said polyamic acid to form a layer of poly-
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`imide;
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`E. depositing a first layer of photoresist over said
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`polyimide layer;
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`F. exposing said first layer of photoresist to optical or
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`X-ray radiation through a mask defining an wiring
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`pattern;
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`G. developing said first layer of photoresist;
`H. etching said interconnect wiring pattern into said
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`polyimide layer;
`I. removing said first layer of photoresist;
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`J. depositing a second layer of photoresist over said
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`patterned polyimide layer;
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`3
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`nection metallurgy pattern defined. The exposed photo-
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`resist is then developed in 0.17N KOI—I or equivalent for
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`other exposure techniques to open up the trenches 22 in
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`photoresist layer 20.
`Photoresist layer 20 is then used as an etch mask and 5
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`the pattern of trenches 22 is transferred to the polyimide
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`layer 18. This transfer is performed in a reactive ion
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`etch tool using oxygen as the etch gas. The etching
`parameters are as follows:
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`etch gas - 02
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`pressure - 10 mtorr
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`watts - 750
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`time - laser endpoint detection plus 20% overetch
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`Upon conclusion of the etching process, the trenches 15
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`22 extend throughout both the photoresist layer 20 and
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`the polyimide layer 18. The photoresist layer 20 is
`stripped using a wet chemical solvent, such as N-
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`methylpyrrolidone.
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`Referring now to FIG. 4, a second layer of positive 20
`diazonovolak photoresist 24 is spun on to a thickness of
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`approximately 1.6—2.0 microns, and then baked for fif-
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`teen minutes at 95° C. The photoresist layer 24 is then
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`exposed using conventional exposure tools through a
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`mask having a pattern of contacts to substrate 14. Fol-
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`lowing exposure, the photoresist 24 is then baked at 95°
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`for fifteen minutes. The developed photoresist layer 22
`is shown in FIG. 5.
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`Next, the contact pattern is etched into the polyimide
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`layer 18 and the BPSG layer 16 in a reactive ion etch
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`tool with the following parameters:
`etch gas - 8% 02 in CHF3
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`pressure - 50 mtorr
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`power - 1400 watts
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`time - endpoint plus 20% overetch
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`The resulting window 26 can be seen in FIG. 5. The
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`photoresist layer 24 is then stripped using a wet chemi-
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`cal solvent.
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`Referring to FIG. 6, since the contact window 26 was
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`etched into the BPSG layer using both the photoresist
`layer 24 and the polyimide layer 18 as etch masks, the
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`contact through the BPSG layer 16 will coincide pre-
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`cisely with the trench 22 which was previously defined
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`to be the area for the metal interconnect lines. The
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`45
`result is a self-aligned contact to metal line structure.
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`Referring now to FIG. 7, a layer of metallurgy 28 is
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`conformally deposited using evaporating or sputtering
`techniques. The interconnection metallurgy can be any
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`material conventionally used for such purposes includ-
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`ing, but not limited to, aluminum, polysilicon, copper,
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`silicon,
`titanium,
`tungsten, silver, gold, or alloys or
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`composites thereof. The thickness of the metal over the
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`polyimide layer 18 is preferably 2; times the radius of
`the contact window 26. In this preferred embodiment,
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`the thickness of the metal 28 is 1.5 microns. As can be 55
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`seen in FIG. 7, the metal 28 fills the contact window 26
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`creating a contact stud and also fills the window 22
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`where the interconnection metallurgy is desired. The
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`metal layer 28 is then blanket etched to the surface of
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`polyimide layer 18 in a reactive ion etcher using the
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`following parameters:
`etch gas - Clz-BC13
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`power - 500—850 watts
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`time - laser or spectrophotometric endpoint The result- 65
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`ing structure can be seen in FIG. 8. The polyimide
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`layer 18 is then removed in an oxygen etch leaving
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`the metal structures 30 and 32 as seen in FIG. 9.
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`1°
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`25
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`Page 5 of 6
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`Page 5 of 6
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`4, 8 5 5 , 25 2
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`6
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`pattern of contacts in sa1d 1nsulat1ng layer and sa1d
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`interconnect wiring pattern in said polyimide layer.
`7. The process as claimed in claim 6 including the step
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`of removing said polyimide layer after depositing said
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`interconnect wiring layer.
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`8. The process as claimed 1n clalm 6 wherem sa1d
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`insulating layer is borophOSphosilicate glass.
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`9. The process as claimed in claim 6 wherein said
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`interconnect wiring layer is selected from the group
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`10 consisting of aluminum, copper, silicon, titanium, tung-
`sten, silver, gold or alloys or composites thereof.
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`*
`* . *
`*
`*
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`5
`K. lithographicany defining a pattern of contacts in
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`Said second layer 0f photoresm’ said Pattern 0f
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`contacts aligned with and overlying said patterned
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`onm''d 1a
`r;
`,
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`p
`ye,
`(.3
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`L. transferring sa1d pattern of contacts to sa1d insulat-
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`ing layer;
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`M. removing said second layer of photoresist; and
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`N' conformany deposmng a layer 0f Interconnect
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`wiring, said interconnect wiring layer filling said
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`5
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`15
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`20
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`25
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`55
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`65
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`Page 6 of 6
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`Page 6 of 6
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