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`United States Patent
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`Boeck et al.
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`[19]
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`[54] METHOD FOR MANUFACTURING A LOW
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`DIELECTRIC CONSTANT INTER-LEVEL
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`INTEGRATED CIRCUIT STRUCTURE
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`[75]
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`Inventors: Bruce Allen Boeck; Jeff Thomas
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`Wetzel; Terry Grant Sparks, all of
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`Austin, Tex.
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`[73] Assignee: Motorola Inc., Austin, Tex.
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`[21] Appl. No.: 727,159
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`[22]
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`Filed:
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`Oct. 7, 1996
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`Int. CI.‘5 ................................................... H01L 21/441
`[51]
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`[52] U.S. Cl. .......................... 438/619; 438/700; 438/633;
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`438/623
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`[58] Field of Search ..................................... 438/619, 622,
`438/623, 627, 633, 700
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`[56]
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`............................ 437/180
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`References Cited
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`US005880018A
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`[11] Patent Number:
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`[45] Date of Patent:
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`
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`5,880,018
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`
`Mar. 9, 1999
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`
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`WO 87/04858
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`WO 96/19830
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`8/1987 WIPO ............................ HOIL 21/90
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`6/1996 WIPO .......................... HOIL 23/532
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`OTHER PUBLICATIONS
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`G. Minamihaba et al., “Double-Level Cu Inlaid Intercon-
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`nects With Simultaneously Filled Via—Plugs”, 2419A Int’l.
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`Conf. on Solid State Devices & Materials, Aug. 21—24,
`
`1995, pp. 97—99.
`
`
`
`
`Yoshio Homma et al., Low Permittivity Organic Dielectrics
`
`
`
`
`
`
`for Multilevel
`Interconnection in High Speed ULSIs,
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`Extended Abstracts of the 1995 Int’l. Conf. on Solid State
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`Devices & Materials, pp. 154—156.
`
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`
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`Yoshio Homma et al., “Low Permittivity Organic Dielectrics
`for Multilevel
`Interconnection in High Speed ULSls”,
`
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`
`
`2419A Int’l. Conf. on Solid State Devices and Materials,
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`Aug. 21—24, 1995, pp. 154—156.
`Partial European Search Report and Annex, EP 97 11 6851.
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`Primary Examiner—Caridad Everhart
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`Attorney, Agent, or Firm—Keith E. Witek; Kent J. Cooper
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`[57]
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`ABSTRACT
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`An interconnect structure having a dielectric layer with low
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`dielectric constant is formed within an integrated circuit. In
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`one embodiment of the invention, portions of a silicon
`dioxide layer (18) lying adjacent to a conductive intercon-
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`nect (21) are removed to expose portions of a silicon nitride
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`etch stop layer (16). A dielectric layer (22) having a low
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`dielectric constant is then formed overlying the conductive
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`interconnect (21) and the exposed portions of the silicon
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`nitride etch stop layer (16). Aportion of the dielectric layer
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`(22) is then removed to expose the top surface of the
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`conductive interconnect (21) to leave portions of the dielec-
`tric layer (22) between adjacent conductive interconnects
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`(21). The rewlting interconnect structure has reduced cross-
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`talk between conductive interconnects (21) while avoiding
`prior art disadvantages of reduced thermal dissipation and
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`increased mechanical stress.
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`50 Claims, 5 Drawing Sheets
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`Page 1 of 13
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`TSMC Exhibit 1039
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`TSMC v. IP Bridge
`IPR2016-01379
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`Page 1 of 13
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`TSMC Exhibit 1039
`TSMC v. IP Bridge
`IPR2016-01379
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`US. Patent
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`Mar. 9, 1999
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`Sheet 1 of5
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`5,880,018
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`US. Patent
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`Mar. 9, 1999
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`Sheet 2 of5
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`5,880,018
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`US. Patent
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`Mar. 9, 1999
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`Sheet 3 of5
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`30\‘
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`US. Patent
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`Mar. 9, 1999
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`Sheet 4 of5
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`5,880,018
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`50\
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`FIGJJ
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`FIG. 12
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`52
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`FON
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`I w E w6 U01“
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`FIG. 13
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`N E
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`60
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`56
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`F]0.14
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`US. Patent
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`74
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`72 — 7o
`7""
`57 s
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`~
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`60
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`72 — 70
`will”
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`5,880,018
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`1
`METHOD FOR MANUFACTURING A LOW
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`DIELECTRIC CONSTANT INTER-LEVEL
`
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`INTEGRATED CIRCUIT STRUCTURE
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`FIELD OF THE INVENTION
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`The present invention relates generally to semiconductor
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`manufacturing, and more particularly, in forming low dielec-
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`tric constant regions between metallic members to reduce
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`capacitive coupling and cross-talk.
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`BACKGROUND OF THE INVENTION
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`Modern integrated circuits contain thousands of semicon-
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`ducting devices on a single chip and as the device density of
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`a given chip increases more layers of metallization are
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`required to interconnect the devices. Moreover, within a
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`given metal layer, the horizontal distance separating metal-
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`lization lines must be reduced in order to minimize the chip
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`size as integrated circuit device density increases. At the
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`same time, metallization resistance and capacitance must be
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`minimized in order to meet the chip’s speed and perfor-
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`mance requirements. Traditionally, the inter-level dielectrics
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`used to isolate metallization lines within a same level and
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`metallization lines in two different levels have been per-
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`formed using materials with high dielectric constants. For
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`example, undoped and doped silicon dioxide layers such as
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`borophosphosilicate glass (BPSG), phosphosilicate glass
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`(PSG), and plasma and chemical vapor deposited tetraethy-
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`lorthosilicate based (TEOS) oxides have been used as
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`dielectric layers in these multi-metallization structures. The
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`semiconductor industry’s continuing demand for integrated
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`circuits with ever increasing device densities and operating
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`speeds requires new dielectric materials having low dielec-
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`tric constants in order
`to reduce cross-talk, capacitive
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`coupling, and resulting speed degradation.
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`However, many of the low dielectric constant materials
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`which are used to form inter-level and inter-metal dielectric
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`layers are difficult
`to work with because of their poor
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`mechanical strength. In addition, many of these materials
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`have processing temperature limitations, i.e., they cannot be
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`exposed to thermal processing over a certain temperature
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`once formed on an integrated circuit. In addition, many of
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`these materials also provide poor thermal conductivity.
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`Therefore, heat generated during high frequency operation
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`cannot be effectively dissipated from the integrated circuit
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`whereby circuit reliability becomes a problem. Accordingly,
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`a need exists for a method for forming an interconnect
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`structure with a dielectric layer having a low dielectric
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`constant whereby mechanical strength disadvantages are
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`reduced, and thermal dissipation is improved.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIGS. 1—6 illustrate, in cross-sectional diagrams, process
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`steps for making an interconnect structure in accordance
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`with one embodiment of the invention.
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`FIGS. 7—10 illustrate, in cross-sectional diagrams, process
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`steps for making an interconnect structure in accordance
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`with an alternative of embodiment of the invention.
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`FIGS. 11—15 illustrate, in cross-sectional diagrams, pro-
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`cess steps for making an interconnect structure in accor-
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`dance with yet another alternative embodiment of the inven-
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`tion.
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`FIG. 16 illustrates, in a cross-sectional diagram, an inter-
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`connect structure wherein air gaps are formed by a material
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`deposited via a non-conformal deposition process in accor-
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`dance with one embodiment of the invention.
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`2
`It will be appreciated that for simplicity and clarity of
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`illustration, elements illustrated in the FIGURES have not
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`necessarily been drawn to scale. For example, the dimen-
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`sions of some of the elements are exaggerated relative to
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`other elements for clarity. Further, where considered
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`appropriate, reference numerals have been repeated among
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`the FIGURES to indicate corresponding or analogous ele-
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`ments.
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`DESCRIPTION OF A PREFERRED
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`EMBODIMENT
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`Generally, the present invention involves a method for
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`forming an interconnect structure in an integrated circuit
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`(IC) wherein RC time delays or cross-talk between adjacent
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`metal lines is reduced. In one embodiment of the invention,
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`an interconnect structure is formed using a first dielectric
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`layer with a high dielectric constant and a second dielectric
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`layer with a low dielectric constant. In this embodiment of
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`the invention, the dielectric layer having a low dielectric
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`constant is formed predominantly between conductive inter-
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`connects and not substantially over the conductive intercon-
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`nects. The low-K dielectric material is formed in this manner
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`after a sacrificial higher-K dielectric layer between the
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`interconnects has been removed to provide areas between
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`conductive members which can be filled low-K dielectric
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`material whereby low-K dielectric material over the con-
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`ductive members is reduced or eliminated. This select place-
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`ment of low-K material
`to between conductive regions
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`instead of overlying or underlying conductive member
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`improves thermal dissipation and mechanical strength while
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`preserving the advantage of improved isolation associated
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`with the low-K material.
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`In another embodiment of the invention, an interconnect
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`structure having reduced cross-talk or RC time delays is
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`formed by etching a first dielectric layer to form a contact
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`opening. A second dielectric layer is then deposited wherein
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`the second dielectric layer has a low dielectric constant. The
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`second dielectric layer is deposited such that the contact
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`opening in the first dielectric layer is sealed to form an air
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`region (e.g., the second dielectric can be a low-K spin-on-
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`resin with a stiff polymer backbone). Aportion of the second
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`dielectric layer is then removed to expose the contact
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`opening previously sealed by the second dielectric layer. A
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`dual in-laid metal interconnect is then formed within the
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`contact opening whereby the low-K second dielectric is
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`positioned between conductive regions where isolation ben-
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`efits are achieved while thermal and mechanical properties
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`are improved.
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`In an alternative embodiment of the invention, void/air
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`regions are formed between adjacent conductive metal inter-
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`connect lines by spinning on a polymeric resin having a stiff
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`polymer backbone. This stiff backbone material forms air
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`regions between closely spaced metal conductive members
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`within the same conductive interconnect layer. Depending
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`upon the atomic gas content of the air gaps and atmospheric
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`pressure of formation, the air gaps will approach a dielectric
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`constant e=1 which is the optimal dielectric constant for
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`reduction of cross-talk and adverse capacitive coupling in
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`polysilicon and metal interconnects.
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`In yet another embodiment of the invention, a non-
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`conformal dielectric layer is formed overlying adjacent
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`conductive interconnect lines such that a void/air region is
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`formed between closely-spaced conductive interconnect
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`lines within the same conductive inter-connect
`level. A
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`second dielectric layer is then formed overlying the non-
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`conformal dielectric layer and planarized to form a com-
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`

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`5,880,018
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`3
`pleted inter-level dielectric. The second dielectric layer and
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`the non-conformal conductive layer are then patterned to
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`form a contact or via opening which is then filled with
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`conductive material to form a conductive interconnect. The
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`void region between the two adjacent conductive intercon-
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`nect lines reduces cross-talk/capacitance between the two
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`conductive interconnect
`lines so that circuit speed is
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`improved and logical cross-talk errors are avoided.
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`The embodiments of the present invention can be further
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`understood with reference to FIGS. 1—16.
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`FIGS. 1—6 illustrate, in cross-sectional form, process steps
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`for making an interconnect structure in accordance with a
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`first embodiment of the invention. Shown in FIG. 1 is a
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`portion 10 of an integrated circuit structure comprising a
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`first dielectric layer 12, an etch stop layer 16, and a second
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`dielectric layer 18. In FIG. 1, first dielectric layer 12, etch
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`stop layer 16, and second dielectric layer 18 are patterned
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`using conventional lithographic and etching techniques. In a
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`preferred embodiment, first dielectric layer 12, etch stop
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`layer 16, and second dielectric layer 18 are simultaneously
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`patterned and etched using a plasma etch chemistry com-
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`prising a fluorinated etch species. For example, the layers
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`12, 16, and 18 may be patterned in a plasma environment
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`which is generated using etch gases such as CHF3, CF4,
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`C2F6 and/or the like. It is important to note that this etch
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`process defines a contact opening 14 within first dielectric
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`layer 12 which allows a metallic conductive layer to be
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`subsequently deposited within the contact opening of FIG. 1
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`to form a conductive contact portion 14. This subsequently
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`deposited conductive layer
`is used to make electrical
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`contact/interconnection to an underlying conductive region
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`such as another metal layer or a doped semiconductive
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`region within polysilicon layer or the semiconductor sub-
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`strate. The doped region may be a bipolar electrode, a well
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`contact, a source/drain, a thin film transistor (TFT) node or
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`a like doped polysilicon or substrate portion. Polysilicon
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`may be replaced with amorphous silicon, epitaxially grown
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`silicon, or refractory silicided silicon-containing layers.
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`In one embodiment, first dielectric layer 12 and second
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`dielectric layer 18 are formed using the same material. For
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`example, first dielectric layer 12 and second dielectric layer
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`18 may be a layer of borophosphosilicate glass (BPSG),
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`layers of plasma tetraethylorthosilicate (TEOS), phospho-
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`silicate glass (PSG) layers, silicon dioxide, nitride layers,
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`In
`fluorinated oxide layers, or like dielectric materials.
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`another form,
`the dielectric layer 18 may be made of a
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`different material from layer 12. First dielectric layer 12,
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`second dielectric layer 18 are formed using conventional
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`plasma deposition processes, low pressure chemical vapor
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`position (LPCVD) processes, or
`the like.
`In one
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`embodiment, etch stop layer 16 is a layer of plasma
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`enhanced silicon nitride when the layers 12 and 18 are oxide.
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`Alternatively, etch stop layer 16, which can also function as
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`an anti-reflective coating (ARC) used in lithographic
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`processing, may be a layer of silicon rich silicon nitride,
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`aluminum nitride, or any dielectric layer which can be used
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`as an etch-back stopping layer or a chemical mechanical
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`polishing (CMP) stop layer. Also, silicon oxide nitride
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`(SiON) or silicon rich SiON may be used as an etch stop or
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`anti-reflective coating (ARC) layer herein.
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`In FIG. 2, another photoresist and etch process is used to
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`form interconnect trenches within layer 18. The openings
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`through layer 12 in FIG. 1 are contact openings to under-
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`lying material whereas the opening formed through layer 18
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`in FIG. 2 is an interconnect trench. To form the interconnect
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`trenches of an in-laid metal (damascene) process, the second
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`dielectric layer 18 is etched selective to etch stop layer 16
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`4
`using an etch chemistry environment. This etch process
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`defines an interconnect region 20 within second dielectric
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`layer 18. It is important to note that dual in-laid metal
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`processing can be performed in other similar ways than that
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`illustrated in FIGS. 1—2. FIGS. 1—2 are intended to be
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`representative of any method for forming dual in-laid struc-
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`tures having contact areas and interconnect trenches.
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`In FIG. 3, a conductive layer of material is then deposited
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`within contact portion 14 and interconnect portion 20. This
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`conductive layer of material is subsequently planarized by
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`CMP and/or etch processing to form conductive intercon-
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`nects 21. In one embodiment, conductive interconnects 21
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`are formed by first depositing a thin barrier layer within
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`contact portion 14 and interconnect portion 20 followed by
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`a thicker conductive layer which more completely fills
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`conductive portion 14 and interconnect portion 20. It should
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`be appreciated that interconnect 21 may be formed using
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`conventional chemical mechanical polishing (CMP)
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`techniques, resist etch back (REB) techniques, and/or timed
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`plasma etch processing. Any layer or composite layer com-
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`prising titanium nitride,
`titanium tungsten,
`titanium,
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`tantalum, tantalum nitride, tantalum silicon nitride, titanium
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`silicon nitride, tungsten nitride or other like material may be
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`used as barrier layers for the portions 14 and 20. In addition
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`it should be appreciated that copper, gold, silver, tungsten,
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`aluminum, any composite thereof, or the like may be used as
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`the thicker fill materials to form interconnect 21 over the
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`barrier layer(s). Moreover, conductive interconnect 21 may
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`be formed using conventional chemical vapor deposition
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`(CVD) techniques, electrode plating techniques, sputtering
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`techniques, and/or selective deposition techniques.
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`In FIG. 4,
`the remaining portions of second dielectric
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`layer 18 (referred to as sacrificial dielectric layer portions)
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`are selectively removed to expose portions of etch stop layer
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`16. It should be appreciated that the remaining portions of
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`dielectric layer 18 may be removed using conventional
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`plasma and/or wet etching techniques. In one embodiment
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`the remaining portions of dielectric layer 18 are removed
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`using buffered HF solution. Alternatively,
`the remaining
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`portions of dielectric layer 18 may be removed using the
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`same etch process used to define interconnects 21.
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`In FIG. 5, a third dielectric layer 22 having a low
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`dielectric constant e is then formed over conductive inter-
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`connects 21.
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`Adequate low-K dielectrics for use herein are such that
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`e§3.5. Even more reduction in cross-talk and capacitive
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`coupling will result when a low-K dielectric having e§3.0
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`is utilized. Preferably,
`from a capacitive-reduction
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`standpoint, materials with e§2.7 are optimal as inter-level
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`dielectrics. Third dielectric layer 22 maybe formed using
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`conventional spin-on techniques or chemical vapor deposi-
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`tion techniques. Spin-on polymers or spin on glasses (SOGs)
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`which are best used for the layer 22 are hydrogen silsesqui-
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`oxane (HSQ), benzocyclobutene (BCB), polyimide, and
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`polyarylether
`For example,
`in one embodiment,
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`dielectric layer 22 has a dielectric constant of approximately
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`e=3.0 and is a spin-on glass material such as HSQ.
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`Alternatively, dielectric layer 22 may be a thermal setting
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`resin such as BCB which has a dielectric constant of
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`approximately e=2.6. Alternatively, dielectric layer 22 may
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`be a polyaryl ether such as PAE or PAE2 having a dielectric
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`constant of approximately e=2.6. It is important to note that
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`any dielectric having e§3.5 can be utilized to improve
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`capacitance and cross-talk of TEOS or silicon dioxide which
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`has a dielectric constant within the range of 3.9 to 4.3. Layer
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`22 may be an organic spin-on dielectric or organic dielectric
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`layer formed by a CVD technique.
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`Page 8 of 13
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`

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`5,880,018
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`5
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`In FIG. 6, dielectric 22 is then planarized to expose a top
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`portion of conductive interconnects 21. Typically, the por-
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`tion of interconnect 21 which is exposed is a top portion of
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`the conductive interconnect portion 20 as illustrated in FIG.
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`6. In a preferred embodiment, dielectric layer 22 is pla-
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`narized using conventional plasma etching techniques and/
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`or chemical mechanical polishing. As shown in FIG. 6, this
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`planarization results in a formation of an interconnect struc-
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`ture having a low dielectric constant dielectric layer 22
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`(eé35) overlying another dielectric layer 12 and 16 having
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`a higher dielectric constant (e>3.5). In addition, layer 22
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`and/or top portions of the conductive interconnects of FIG.
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`6 may be covered by an optional anti-reflective coating
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`(ARC) layer. It should be appreciated that dielectric layer 22
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`which has a low dielectric constant improves circuit perfor-
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`mance because capacitance between adjacent interconnect
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`lines is reduced by lower-K films. Due to the fact that layer
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`22 does not cover the entire surface of the wafer (e.g. top
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`portions of 20 are not covered by layer 22 in FIG. 6),
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`mechanical stability is improved and thermal properties are
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`increased for the integrated circuit. If copper is used as a
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`conductive interconnect in FIG. 6, then a capping/barrier
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`layer may be needed on top of the structure of FIG. 6 to
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`isolate the copper from overlying materials.
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`FIG. 7—10 illustrate, in cross-sectional form, process steps
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`for making an interconnect structure in accordance with an
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`alternative embodiment of the invention. Shown in FIG. 7 is
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`a portion 30 of an integrated circuit structure comprising an
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`etch stop layer 32, a first dielectric layer 34, and a photo-
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`resist layer 36. Using conventional photolithographic pat-
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`terning and etch techniques, etch stop layer 32 and first
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`dielectric layer 34 are etched to form a contact portion 38
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`within first dielectric layer 34 and to expose an underlying
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`conductive region (not illustrated in FIG. 7) such as a metal
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`interconnect, polysilicon, or doped silicon region. Layer 32
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`is formed using conventional plasma or chemical vapor
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`deposition techniques and may be a layer of silicon nitride,
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`silicon rich-silicon nitride or aluminum nitride and functions
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`as an etch stop layer (ESL) and/or an anti-reflective coating
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`(ARC) layer. First dielectric layer 34 is also formed using
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`conventional chemical vapor deposition (CVD) techniques
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`such as plasma deposition, low pressure chemical vapor
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`deposition (LPCVD) and the like and may be a layer of
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`BPSG, PSG, TEOS, fluorinated oxide, or like dielectric
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`materials or composite layers.
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`In FIG. 8, photoresist mask 36 is removed and a dielectric
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`layer 40 having a low dielectric constant is formed over
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`dielectric layer 34 such that contact portion 38 is capped or
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`bridged by dielectric layer 40 and left unfilled (i.e., an air
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`gap 38 is formed in FIG. 8 from the contact portion 38 of
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`FIG. 7). An anti-reflective coating (ARC) layer 42 which
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`also serves as a hard mask is then deposited over dielectric
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`layer 40. In a preferred embodiment, dielectric layer 40 has
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`a dielectric constant e of 3.0 or less, but can be any material
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`less than Ez3.5 to confer electrical isolation benefits between
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`adjacent conductive members. In one embodiment, dielec-
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`tric layer 40 is polyphenquuinoxaline (PPQ) and has a
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`dielectric constant of e=3.0. Alternatively, dielectric layer 40
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`may be a layer of polyimide having a dielectric constant of
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`e=2.6. The polyimide may be formed from either a poly
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`(amic) acid solution or a fully imidized polyimide in FIG. 8.
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`In general, the spin-on material used in FIG. 8 to make the
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`layer 40 can be any material which has a substantially stiff
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`polymer backbone so that the air regions 38 are at least
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`partially formed in FIG. 8.
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`To avoid blistering of the air gap 38 of FIG. 8, an anneal
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`step of the layer 40 should be performed in a thermal ramp
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`10
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`60
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`65
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`Page 9 0f 13
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`6
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`manner. The ramp should start at less than 100° C. and
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`arrive, after a selected temperature ramp time period, at
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`roughly 100° C. to 300° C. for solvent-removal annealing of
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`the layer 40. A slower ramp thermal process will be more
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`likely to avoid any blistering of the air gap 38 than a fast
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`exposure to high temperatures. Also, a sub-atmospheric
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`spin-on process can be used to create air gaps 38 with
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`reduced pressure or fewer trapped molecules/atoms. This
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`sub-atmospheric process can reduce blistering effects by
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`eliminating a high density of atoms within the gap 38.
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`In FIG. 9, conventional photolithographic patterning and
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`etching techniques are then used to pattern and etch reflec-
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`tive layer 42 and dielectric layer 40 to define interconnect
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`portion 41 within dielectric layers and to re-expose contact
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`portion 38 which are the air gaps 38 in FIG. 8. It is important
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`to note that additional etching is not required to form a
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`contact opening to an underlying metal
`interconnect or
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`doped silicon region since the air gaps 38 were isolated in
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`FIG. 8. In one embodiment, dielectric layer 40 is patterned
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`using a plasma comprising oxygen, and photoresist mask 44
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`used to define the opening within dielectric layer 40 is
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`removed at the same time that dielectric layer 40 is etched.
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`Therefore,
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`the etch process used to
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`pattern dielectric layer 40 also simultaneously removes
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`some or all of the photoresist mask 44 used to define the
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`opening within dielectric layer 40.
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`In FIG. 10, a barrier layer 49 and a conductive film
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`material are then formed within contact opening 38 and
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`interconnect region 41. Aportion of the barrier layer 49 and
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`the conductive film material are then selectively removed to
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`form conductive interconnects 48 of FIG. 10.
`In one
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`embodiment, conductive interconnects 48 are formed using
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`conventional plasma etching techniques. Alternatively, con-
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`nective interconnects 48 may be formed using conventional
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`chemical mechanical polishing (CMP) techni