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`[19]
`United States Patent
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`4,560,436
`[11] Patent Number:
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`Bukhman et a1.
`[45] Date of Patent:
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`Dec. 24, 1985
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`[54] PROCESS FOR ETCHING TAPERED
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`POLYIMIDE VIAS
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`[75]
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`Inventors: Yefim Bukhman, Tempe; Steven C.
`Thornquist, Mesa, both of Ariz.
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`Motorola, Inc., Schaumburg, Ill.
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`[51]
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`[56]
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`[73] Assignee:
`[21] Appl. No.: 627,263
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`[22] Filed:
`Jul. 2, 1984
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`Int. c1.4 ...................... .. B44C 1/22;CO3C15/OO;
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`C03C 25/06; B29C 17/08
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`[52] us. Cl. .................................. ..156/643;156/646;
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`156/653; 156/655; 156/657; 156/659.1;
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`156/668; 204/192 E; 427/89; 357/71
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`[58] Field of Search ............. .. 156/643, 644, 646, 652,
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`156/653, 655, 657, 659.1, 661.1, 662, 668;
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`29/580; 204/164, 192 EC, 192 E; 427/38, 39,
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`88, 89—90, 91; 357/71; 430/313, 317
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`References Cited
`U.S. PATENT DOCUMENTS
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`
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`4,367,119
`1/1983 Logan et al. .................... 156/644 X
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`4,409,319 10/1983 Colacino et al.
`156/647 X
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`4,487,652 12/1984 Almgren .... .. .. .
`. .. .. ... 156/643
`.................... .. 156/653 X
`1/1985 Wolf et a1.
`4,495,220
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`FOREIGN PATENT DOCUMENTS
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`2/1978 Japan ................................. .. 156/652
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`0013372
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`Attorney, Agent, or Firm—~Michael D. Bingham
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`ABSTRACT
`[57]
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`A polyimide-oxide—polyimide integrated circuit struc-
`ture is utilized in the process for forming openings hav-
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`ing tapered sidewalls and predetermined controlled
`sizes. At least one opening size is replicated and trans-
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`ferred to an exposed surface in a underlying surface of
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`the structure by first forming a thick layer of oxide over
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`the first cured polyimide layer, anisotropically etching
`the thick layer of oxide to form an opening of predeter-
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`mined size therethrough to the surface of the first cured
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`polyimide layer. Next, the first layer of cured polyimide
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`is isotropically etched to form an opening therethrough
`of substantially said predetermined size and exposing a
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`portion of a thin layer of oxide underlying the first layer
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`of cured polyimide. The thin layer of oxide is then an-
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`isotropically etched using the thick layer of oxide as an
`etch mask to expose an opening of said predetermined
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`size on a surface of a second layer of cured polyimide.
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`The second layer of cured polyimide is then anisotropi-
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`cally etched again using the thick layer of oxide as the
`etch mask to transfer and replicate the opening in the
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`thick layer onto the surface of the underlying region.
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`Thereafter the thick layer of oxide is removed. Metaliz-
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`ation can then be deposited on the resulting structure to
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`make contact to the underlying surface.
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`Primary Examiner—William A. Powell
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`2 Claims, 6 Drawing Figures
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`D
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`146-
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`14
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`12
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`Page 1 of 5
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`TSMC Exhibit 1036
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`TSMC v. IP Bridge
`IPR2016-01379
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`Page 1 of 5
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`TSMC Exhibit 1036
`TSMC v. IP Bridge
`IPR2016-01379
`
`

`

`US Patent
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`Dec. 24, 1985
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`4,560,436
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`m"ME
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`IE
`14-
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`[III/Ill-IIE’
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`Page 2 0f 5
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`Page 2 of 5
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`

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`PROCESS FOR ETCHING TAPERED POLYIMIDE
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`VIAS
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`1
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`4,560,436
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`5
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`10
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`15
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`25
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`30
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`2
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`openings through a thick insulating layer of material
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`comprising a portion of an integrated circuit.
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`It is another object of the invention to provide a
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`process for etching an opening through a polyimide
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`layer wherein the opening has tapered sidewalls and is
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`controlled in size.
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`Still another object of the invention is to provide an
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`improved process for fabricating a semiconductor de-
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`vice including the etching of contact openings through
`a polyimide layer.
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`In accordance with the above and other objects there
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`is provided a process for etching dimensionally con-
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`trolled and tapered polyimide vias (openings) during
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`the fabrication of semiconductor devices utilizing dif-
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`ferential etching process steps.
`A feature of the embodiment of the invention is that
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`a first layer of cured polyimide is formed overlying a
`sub-surface of a semiconductor substrate which is to be
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`exposed. A first layer of oxide is then formed overlying
`the first layer of cured polyimide and a second layer of
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`cured polyimide is then formed overlying this first layer
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`of oxide. A second layer of oxide is then formed overly-
`ing the second layer of cured polyimide material. A
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`masking layer is applied over the second oxide layer
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`which is selectively patterned with openings there-
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`through using conventional photo etching processes
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`which openings are to be replicated at the top surface of
`the underlying sub-surface layer of the semiconductor
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`device thereby making contact openings thereto. Using
`the masking layer as an etch mask the second oxide
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`layer is etched anisotropically. The masking layer is
`removed as the second layer of cured polyimide is iso-
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`tropically etched through the opening in the second
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`oxide layer to provide 3 via therethrough. By isotropi—
`cally etching the second layer of cured polyimide ta-
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`pered sidewalls are formed as the opening is etched
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`therethrough. The etchant used for the isotropic etch-
`ing is selective and stops at the first oxide layer which
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`acts as an etch stop for all vias being simultaneously
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`etched in the semiconductor device. The first oxide
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`layer is then etched anisotropically using the second
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`oxide layer as an etch mask whereby the dimensions of
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`the opening in the second oxide layer is transferred to
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`the upper surface of the first layer of cured polyimide
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`material. The first layer of cured polyimide material is
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`next etched anisotropically using the first oxide layer as
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`an etch mask to provide the contact opening on the
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`exposed upper surface of the underlying sub-surface
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`layer of the semiconductor device. This contact open-
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`ing has essentially the same dimensions and replicates
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`the opening formed in the second oxide layer by the
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`photomasking layer. The second oxide layer is then
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`etched away to allow contact to the exposed portion of
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`the underlying sub-surface layer through the tapered
`via of the second polyimide layer. Metal or other types
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`of semiconductor material may then be deposited
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`through the openings or formed through the polyimide
`layers to contact the sub-surface layer of the semicon-
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`ductor device.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIGS. 1—6 are cross-sectional views of a portion of a
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`semiconductor device or integrated circuit fabricated
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`by the process steps of the present invention.
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`BACKGROUND OF THE INVENTION
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`The present invention relates to the fabrication of
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`integrated circuits and, more particularly, to the fabri-
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`cation of integrated circuits having multilayer struc-
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`tures interconnected by vias (openings) etched through
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`a polyimide layer separating such layers. Specifically,
`the invention relates to a process for transferring an
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`aperture formed in a photoresist masking layer to a
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`subsurface layer of an integrated circuit using a tapered
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`opening etched in a polyimide layer.
`The advent of very large scale integrated circuits
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`(VLSI) and very high speed integrated circuits
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`(VHSIC) technologies have placed stringent demands
`on very fine line geometry semiconductor devices as
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`well as multilayer metal schemes requiring attendant
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`20
`multilayer interconnect systems. In the fabrication of
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`semiconductor devices of high density and high com-
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`plexity, it is necessary to shrink the size and spacing of
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`device features. It is also necessary or desirable to use
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`thick layers of insulating material to isolate between the
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`semiconductor substrate and overlying metal layer or
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`between multiple interconnect metal layers. Polyimide
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`layers, in which a liquid material is applied to the sur-
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`face of the-semiconductor substrate and subsequently
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`heat treated to cure or form the polyimide material, are
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`well suited to the function of forming an insulating
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`layer. The use of thick polyimide insulating layers, and
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`especially on small geometry devices, presents a prob-
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`lem with metal continuity into contact openings. To
`provide desired electrical contact between interconnect
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`35
`layers, contact openings must be formed through the
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`polyimide material. Metal is then applied over the de-
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`vice and into these contact openings. Because the poly-
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`imide may be thick, it is difficult to achieve reliable
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`metal coverage over the peripheral walls of the contact
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`openings to the underlying material. Metal step cover-
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`age problems are enhanced by the need for the metal
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`patterns to consist of thin and very narrow metal strips
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`to allow fine geometry patterning. To insure reliability
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`utilizing step coverage into openings through the thick
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`polyimide layer, it is imperative that the edges of the
`opening be tapered. It is also important, however, that
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`the size of the opening be carefully controlled. The
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`latter requirement results partially from the fact that the
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`lower metal surface or device region being contacted
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`may be small and precisely placed. If the size of the
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`opening or via is not controlled and the opening
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`through the polyimide material is too large, then subse-
`quently applied metal may cause shorting between adja-
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`cent device regions. There are a number of processes
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`which provide for either the tapering of the walls of the
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`opening or for the control of the critical dimensions
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`thereof, however, there has not been a production cam-
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`patible etching process which simultaneously achieves
`both of these necessary features.
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`Thus, during the fabrication of fine line geometry
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`integrated circuits, a need exists for a process to etch
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`tapered openings through a thick insulating layer to
`transfer critical openings to a subsurface layer of the
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`integrated circuit.
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`BRIEF SUMMARY OF THE INVENTION
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`Accordingly, it is an object of the present invention
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`to provide an improved method of etching tapered
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`4O
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`Page 3 of 5
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`4, 5 60,43 6
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`4
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`formed tapered sidewalls 32 and 34. Very thin oxide
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`layer 18 acts as an etch stop so that everywhere in IC 10
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`where photoresist layer 24 has been selectively pat—
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`terned with an opening, a tapered via is etched through
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`cured polyimide layer 20 to the same depth i.e., to the
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`upper surface of oxide layer 18. Photoresist layer 24 is
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`etched away during this process step.
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`The next step in the process of the present invention
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`is to anisotropically etch through oxide layer 18 using
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`oxide layer 22 as an etch mask to replicate openings 28
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`therethrough to expose the upper surface of cured poly-
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`imide layer 16 (FIG. 3). To etch oxide layer 18, the
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`chemistry of the plasma etch step is conducted once
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`again in a fluorinated gas atmosphere.
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`As illustrated in FIG. 4, cured polyimide layer 16 is
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`then anisotropically etched in an oxygen atmosphere
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`using remaining oxide layer 22 as the etch mask there-
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`for. Again, the anisotropic etching can be done, for
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`example, by reactive ion etching. Thus, etching of
`cured polyimide layer 16 allows the exact transfer of
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`critical dimension D from the opening in the original
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`photoresist layer 24 through cured polyimide layer 16
`to expose the upper surface of sub-surface region 14 as
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`desired.
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`As shown in FIG. 5 the next step is to completely
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`etch away oxide layer 22 while simultaneously remov-
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`ing the exposed area of oxide layer 18 overlying cured
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`polymide layer 16. This is accomplished by utilizing
`fluorine gas base reactive ion etching, for example.
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`Hence, an enlarged opening 40 is formed in thin oxide
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`layer 18 prior to metalization of IC 10.
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`Finally, if, for example, region 14 is metal, i.e., a metal
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`conductive run which is to be interconnected to an
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`upper level metal contact, metalization 42 can then be
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`applied over the polyimide isolated IC structure to
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`provide the desired contact through opening 38.
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`By way of example only, IC 10 may be formed of the
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`above described layers having the following respective
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`thickness:
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`sub-surface region 14: approximately 0.7 microns
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`polyimide layer 16: approximately 1.0 microns
`oxide layer 18: approximately 0.05 microns
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`polyimide layer 20: approximately 1.0 microns
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`oxide layer 22: approximately 0.25 microns
`Further, the above described etch steps may be con-
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`ducted utilizing the following process chemistries and
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`the AME-8110 etcher:
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENT
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`FIG. 1 illustrates a cross-sectional view of a portion
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`of a semiconductor device or integrated circuit (IC) 10 5
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`formed of multiple layers 14—22 on substrate 12 using
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`conventional deposition techniques such as plasma de-
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`position. As shown, [C 10 may be a high density com-
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`plex IC wherein multilayer interconnects are required
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`between the upper surface of the IC and sub-surface 10
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`regions therein. For instance, IC 10 may consist of a
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`first metal layer 14 deposited on the upper surface of
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`substrate 12 which comprises a semiconductor material
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`of a first conductivity type. A first layer 16 of cured
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`polyimide material
`is formed overlying sub-surface 15
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`layer 14 having an upper planar surface upon which a
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`thin first layer 18 of oxide material is formed. Oxide
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`layer 18 which may be deposited Si02 material or any
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`other material commonly used in the manufacture of
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`integrated circuits,
`is formed over the upper planar 20
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`surface of polyimide layer 16. A second layer 20 of
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`cured polyimide material is formed over the upper pla-
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`nar surface of thin oxide layer 18. A second layer 22 of
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`oxide material is then formed over the upper planar
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`25
`surface of cured polyimide layer 20. The aforedescribed
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`structure forms the IC structure 10 consisting of a polyi-
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`mide-oxide—polyimide-oxide layered structure which
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`overlays sub—surface region 14 which, as aforemen-
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`tioned, may be an internal metal run of very fine line
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`dimensions or a portion of a semiconductor device of 30
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`small dimension.
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`In order to make metal contact to region 14 it is im-
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`portant that any openings formed through the layered
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`structure described above be dimensionally controlled
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`since in VLSI or VHSIC circuits the dimension D of 35
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`opening 26 will be of minimal size. Thus, maintaining
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`the predetermined size of this opening assures that this
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`opening is alligned with sub-surface region 14 and does
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`not overlap the edge thereof which otherwise may
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`present electrical shorting problems. The following 40
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`explanation describes a process for transferring the
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`opening from the upper planar surface of IC 10 to sub-
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`surface region 14in which the dimension of the opening
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`is replicated on the planar surface of region 14.
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`As illustrated in FIG. 1, in accordance with the pres-
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`ent invention, a layer 24 of resist material is formed
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`overlying oxide layer 22 with this resist layer being
`selectively patterned to have openings 26 of predeter-
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`mined dimensions, i.e., diameters D. Layer 24 may be of
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`photoresist or the like and openings 26 may be formed 50
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`therein using conventional photoetching processes to
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`expose the underlying upper surfaces of oxide layer 22.
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`Photoresist layer 24 is used as an etch mask layer for
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`masking oxide layer 22 while layer 22 is anisotropically
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`etched by reactive ion etching, for example, in a fluori-
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`nated carbon gas atmosphere. As illustrated in FIG. 2,
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`openings 26 are replicated in oxide layer 20. The critical
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`dimension D is maintained as openings 28 are etched
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`through oxide layer 22. Etching may take place in a dry
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`plasma atmosphere using, for example, a commercially
`available plasma etcher such as the AME-8110 etcher
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`manufactured by Applied Materials. Next, by changing
`chemistry in the etcher to a predominantly oxygen
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`atmosphere, cured polyimide layer 20 is isotropically
`etched forming an undercut beneath overlying oxide
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`layer 22 which acts as the etch mask therefor during this
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`process step.
`Isotropically etching cured polyimide
`layer 20 forms 3 via 30 therethrough which has uni-
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`45
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`I. Anisotropic etch of oxide layer 22
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`CHF3
`75 standard cubic centimeters per
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`minutes (sccm)
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`16 sccm
`mTorr
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`watts
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`C02
`65
`l 100
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`8 minutes
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`BMW
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`02
`75 sccm
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`CHF3
`15 sccm
`150
`mTorr
`280
`Vdc
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`14 minutes
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`111. Anisotropic etch of oxide layer 18
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`CHF3
`75 sccm
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`16 sccm
`C02
`mTorr
`65
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`watts
`l 100
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`2 minutes
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`IV. Anisotropic etch of mlyimide layer 16
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`40 sccm
`Oz
`mTorr
`10
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`Page 4 0f 5
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`Page 4 of 5
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`

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`4,560,436
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`5
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`-continued
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`700
`Vdc
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`12.5 minutes
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`V. Etch removal of oxide layers 22 and 18
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`CHF3
`75 sccm
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`16 sccm
`C02
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`watts
`1100
`6 minutes
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`6
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`thin layer of oxide; forming a second layer of oxide over
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`said second layer of polyimide; forming a masking layer
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`over said second layer of oxide; selectively patterning
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`said masking layer thereby forming at least one opening
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`therethrough to expose a portion of said second layer of
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`oxide wherein said at least one opening being of prede-
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`termined size; anisotropically etching said second layer
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`of oxide exposed through said masking layer to expose
`a portion of said second layer of cured polyimide under-
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`lying said at least one opening; isotropically etching said
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`second layer of cured polyimide using said second layer
`of oxide as an etch mask to form an opening exposing a
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`portion of said first layer of oxide wherein said opening
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`through said second layer of cured polyimide having
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`tapered sidewalls and said exposed portion of said first
`layer of oxide being an opening of substantially the same
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`dimensions as said at least one opening, said first layer of
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`oxide acting as an etch stop; anisotropically etching said
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`first layer of oxide using said second layer of oxide as an
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`etch mask to expose an opening to said first layer of
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`cured polyimide; anisotropically etching said first layer
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`of cured polyimide using said second layer of oxide as
`an etch mask to form an opening of said predetermined
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`size on the underlying surface.
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`2. The method of claim 1 further including the steps
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`of removing said masking layer simultaneously with
`etching said second layer of cured polyimide and re-
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`moving said second layer of oxide after said predeter-
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`mined opening is formed on the underlying surface.
`ill
`it
`*
`i
`it
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`Thus, in accordance with the invention, there is pro-
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`vided a process and structure for patterning of multiple
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`cured polyimide layers for the fabrication of semicon-
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`ductor devices having multiple contacting layers. The
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`process produces dimensionally controlled openings
`between upper and lower connected layers suitable for
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`use in fine line semiconductor process technologies and
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`further produces well controlled vias through a poly-
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`imide layer having tapered sidewalls. A feature of the
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`invention lies in the utilization of a thin oxide layer
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`sandwiched between two thick cured polyimide layers
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`which serves as the etch stop.
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`We claim:
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`1. A method for forming an opening through a poly-
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`imide layer to expose an underlying surface wherein the
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`dimension of the opening exposing the underlying sur-
`face is controlled and is characterized by tapered side-
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`walls, comprising the steps of forming a first layer of
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`cured polyimide on the underlying surface; forming a
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`thin layer of oxide over said first layer of cured poly-
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`imide; forming a second layer of polyimide over said
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`10
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`15
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`20
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`25
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`30
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`35
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`45
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`50
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`65
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`Page 5 of 5
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