IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 11, NOVEMBER 1998
`
`1609
`
`A 480-MHz RISC Microprocessor in a 0.12- m Leff
`CMOS Technology with Copper Interconnects
`
`Chekib Akrout, John Bialas, Miles Canada, Duane Cawthron, James Corr, Bijan Davari, Senior Member, IEEE,
`Robert Floyd, Stephen Geissler, Ronald Goldblatt, Robert Houle, Paul Kartschoke, Diane Kramer,
`Peter McCormick, Member, IEEE, Norman Rohrer, Gerard Salem,
`Ronald Schulz, Lisa Su, Member, IEEE, and Linda Whitney
`
`Abstract—This paper describes the performance improvements
`of a reduced instruction set computer (RISC) microprocessor that
`has migrated from a 2.5-V technology to a 1.8-V technology. The
`1.8-V technology implements copper interconnects and low VVV ttt
`field-effect transistors in speed-critical paths and has an LLLe of
`0.12 m. Global clock latency and skew are improved by using
`copper wires, and early mode timings are improved by reducing
`clock skew and adding buffers. These enhancements, along with
`an environment of 2.0 V, 85C, and with a fast process, produced
`a 480-MHz RISC microprocessor.
`
`Index Terms—CMOS, copper, low threshold, microprocessor,
`PowerPC, reduced instruction set computer (RISC).
`
`SPECint95 and SPECfloat95 ratings of 20 and 12, respectively,
`at 480 MHz with a 1-MB L2 cache running at 240 MHz and
`a 60
`bus frequency of 96 MHz. The 60
`bus is the high-
`speed 32- and 64-bit processor bus interface used throughout
`the PowerPC family of processors.
`
`I. INTRODUCTION
`
`III. TECHNOLOGY
`The 2.5-V CMOS technology, with a field-effect transistor
`(FET)
`of 0.18 m, has five interconnect levels made of
`aluminum, a tungsten local interconnect, and tungsten vies.
`The local interconnect contacts both diffusion and polysilicon
`by overlap. The contacted wiring pitch for the third level of
`metal is 1.26 m. The metal thicknesses are 0.54 m for M1,
`0.73 m for M2, M3, and M4, and 2.07 m for M5. The nom-
`inal internal clock frequency is 221 MHz; but the frequency
`increases to greater than 275 MHz when the
`line is tailored
`shorter, the voltage is increased, and the maximum operating
`temperature is reduced. The I/O’s were designed to interface
`from the internal voltage of 2.5 V to the 3.3-V external bus.
`The 6.4 million transistors fit into a 67 mm chip area.
`The 1.8-V CMOS technology has a nominal NFET
`of 0.12 m. This technology is a linear shrink from the 2.5-
`V technology with some changes to the ground rules for the
`local interconnect and the Si/local interconnect spacing. In this
`technology, the microprocessor has six levels of metal (Fig. 2).
`Metal-level thicknesses are 0.40 m for M1 and M2, 0.55 m
`for M3 and M4, and 1.20 m for M5 and M6. Beginning with
`M1, all levels of metal and vias are fabricated with copper.
`Again, a tungsten local interconnect with a tungsten via is used
`to increase the overall density. The copper wires, manufactured
`with a damascene process, are deposited via electroplating,
`which provides lower costs and better connections to the vias
`than the tungsten via and metal etch-back process used for
`aluminum. A single damascene process is used for M1 and a
`dual damascene process is used for the remaining metal levels.
`The dual damascene process produces the via connections
`and the metal level, in copper, at the same time. The third-
`metal level has a reduced contacted pitch of 0.81 m. This
`microprocessor’s SRAM cell, used in several custom circuits,
`is a migrated design with new ground-rule waivers measuring
`7.6 m . The smallest SRAM cell available in the 1.8-V
`technology, which measures 6.84 m , was not selected in
`order to maintain the M1 word line and not adversely affect the
`development schedule. The technology offers FET’s with two
`0018–9200/98$10.00 ª
`
`A32-BIT 480-MHz PowerPC1 reduced instruction set com-
`
`puter (RISC) microprocessor has been migrated into
`an advanced 0.2- m CMOS technology with copper for its
`interconnects and multithreshold transistors. The technology
`features help to increase the microprocessor’s internal clock
`frequency up to 480 MHz at 2.0 V and 85 C, and at the
`fast end of the process distribution. When operating at room
`temperature, the clock frequency increases to over 500 MHz.
`
`II. PROCESSOR ARCHITECTURE
`The microprocessor’s architecture can dispatch two in-
`structions per cycle by using two 32-KB L1 caches, one
`for data and one for instructions. An integrated L2 cache
`controller can work with L2 cache sizes of 256 KB, 512
`KB, or 1 MB, and the I/O’s interface with the external bus
`using an industry standard of 3.3 V. The 60
`bus has ratios
`of 1
`as well as 2
`to 8 with 0.5
`increments. The
`L2 cache interface contains ratios of L2 bus frequency to
`internal clock frequency of 1 : 1, 2 : 3, 1 : 2, 2 : 5, and 1 : 3. The
`microprocessor has been successfully implemented in a 2.5-V
`CMOS technology [1] and has migrated to a 1.8-V CMOS
`technology (Fig. 1). The 1.8-V microprocessor has estimated
`
`Manuscript received July 10, 1998; revised September 22, 1998.
`C. Akrout, D. Cawthron, D. Kramer, and L. Whitney are with IBM
`Microelectronics Division, Austin, TX 78758 USA.
`J. Bialas, M. Canada, J. Corr, R. Floyd, S. Geissler, R. Houle, P. Kartschoke,
`P. McCormick, N. Rohrer, and G. Salem are with IBM Microelectronics
`Division, Essex Junction, VT 05452 USA (e-mail: pkartsch@btv.ibm.com).
`B. Davari, R. Goldblatt, R. Schulz, and L. Su are with IBM Microelectron-
`ics, Hopewell Junction, NY 12533 USA.
`Publisher Item Identifier S 0018-9200(98)07042-5.
`1 PowerPC is a trademark of IBM Corporation.
`
`1998 IEEE
`
`TSMC Exhibit 1008
`
`Page 1 of 8
`
`

`
`1610
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 33, NO 11, NOVEMBER 1998
`
`NTEGER
`UNITS
`
`
`
`OOOOGCIIIC-IiIHC-ii..DI¥‘
`
`L2C®CflE
`TAGS
`
`A:
`t H! H!". ‘sum
`
`lflfilflurllflfl
`CACHL ,
`
`Fig. 1. A 480-MI-Iz RISC microprocessor with copper interconnect.
`
`distinct threshold voltages (IQ) for both NFET’s and PFET’s.
`At long channel lengths, the low threshold voltage NFET has a
`V, that is 100 mV lower than the nonlow V, device of 310 mV.
`The low V, devices are provided to increase performance. The
`microprocessor’s present chip size is 40 m2. Table I lists
`key microprocessor and technology parameters for both the
`2.5- and 1.8-V technologies.
`
`IV. COPPER INTERCONNECT
`
`Copper interconnects provide a 40% decrease in RC delay
`over the traditional aluminum wires due to the reduced resis-
`
`tivity of copper [2]. Reduced copper resistivity allows for a
`
`tradeofi of the resistance or capacitance by thinning the wire.
`The sheet resistance of the previous interconnect technology is
`maintained because a thinner wire improves manufacturability
`and yield and because the aspect ratio of the wire is not as
`extreme. Reliability of these thinner wires is not compromised
`because copper has less electromigration than aluminum. For
`the 1.8-V technology, the RC reduction of copper is mainly
`caused by the reduced capacitance; the sheet resistance for
`a given interconnect remains nearly constant. The total RC
`reduction is 23%. Because of lower capacitance on the wires,
`intralayer coupling capacitance between the third-metal-level
`wires is reduced by 27%. Fig. 3 shows the late-mode timing
`delay of all
`the timing paths when the microprocessor is
`
`Page 2 of 8
`
`

`
`AKROUT et al.: 480-MHz RISC MICROPROCESSOR
`
`1611
`
`TABLE I
`TECHNOLOGY FEATURES
`
`Fig. 2. Scanning electron microscope of six copper metal levels and local
`interconnect.
`
`wired with aluminum. Fig. 4 presents the same data with
`the metal levels fabricated in copper; the path delay near
`2.0 ns is reduced because the RC delay percentage on the
`critical paths is decreased. Path delays less than 1.0 ns did
`not change significantly because the paths contained little RC
`delay. The top 5% of the paths have RC delay ranging from
`5–25% of the total path delay, where the speed advantage
`
`Fig. 3. Histogram of path delays with Al interconnects.
`
`from copper is noticeable. The top 5% of the paths typically
`contain 18–23 gates/cycle. With a higher percentage of the
`critical path delay dominated by intrinsic gate delay,
`the
`frequency of the microprocessor more easily increases at the
`fast end of the process distribution, with either higher voltage
`or lower temperature. Some of the late-mode critical timing
`paths, which still contain a large amount of RC, are tripled
`in width to decrease the RC delay further. Decreased cycle
`time is accomplished without adding a pipe stage, so a high
`frequency can be reached while still preserving the number
`of instructions executed per cycle. A similar timing for early
`mode was performed to compare clock paths to shortest delay
`
`Page 3 of 8
`
`

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`1612
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`IHI JOURNAL OF SOLID-STATE CIRCUITS, VOL 33, N0 11, NOVEMBH{ 1998
`
`Copper
`
`
`
`100
`I‘-3508->l
`
`200
`150
`I~<sops<~|
`Delay(ps)
`
`2 100
`
`80
`
`8:
`
`3
`up
`
`5 60
`3K
`-3
`
`40
`
`2 g
`
`at
`
`20
`0
`
` 0
`
`0.5
`
`1.
`1.0
`Delay (ns)
`
`Fig. 4. Histogram of path delays with Cu interconnects.
`
`Fig.5.
`
`I-Iistog:n|moftheclocktreelatencywitIrAlandCuinterconnec1s.
`
`data paths. Ifa latching element has data inputs that transition
`too fast or a clock that transitions too slow, the latch can
`be comrpted. Because copper interconnects reduce RC delay
`and can produce early mode paths, buflers are added to slow
`down and eliminate these paths.
`
`clock buffers. The local clock splitter converts a global single-
`phase clock into compltary unbuflered C1 and C2 clocks.
`The local clock buflers use the split outputs to produce a
`buflered master latch clock Cl and a buifered slave latch
`clock C2.
`
`V. Low V, FET IMPLEMENTATION
`
`The microprocessor’s internal clock frequency is further im-
`proved with low V} FET’s. V/ith our timing and floor-planning
`methodology, low V,
`transistors are inserted manually into
`custom macros to improve delay through a custom circuit. The
`remaining logic on the chip is implemented with 4-bit nibbles
`of random logic gates (extended custom standard-cell library)
`and individual 1-bit standard-cell books. A duplicate low V,
`library has been developed for these standard cells. To allow
`nonlow V, and low V, books to be interchangeable, the layout
`of the low V, books is identical to that of the nonlow V, books
`in size and wiring. Afier timing the chip at 500 MHz, any part
`of a late-mode timing path that contains standard-cell books
`and does not meet the timing requirements is converted to a
`low M book and the chip is retimed. Because low V, books
`are used only for the critical paths, the number of transistors
`with the reduced threshold voltage is limited. For the whole
`chip, 12.3% of the 4-bit standard-cell books and 5.0% of the
`1-bit standard-cell books were converted to low V, books. The
`Id_..,.._ for the low V, FET’s is 10% higher than for the standard
`FET’s. The low V, FET leakage is 8—10x higher than standard
`FET’s. Therefore, to balance power versus speed, only 4.2%
`of the total transistors on the microprocessor are converted to
`low V}, which accounts for a performance increase of 6.5%.
`To minimize risk and maintain noise margins, this design does
`not implement low V, FET’s within dynamic circuits.
`
`VI. CLOCK DISTRIBUTION AND PHASE-IDCKED LOOP DESIGN
`
`Increasing the processor speed with a technology remap
`required a proportional improvemt in the clock design and
`distribution because clock skew subtracts from the proces-
`sor cycle time. A hierarchical clock-distribution methodology
`included variable wire widths to minimize delay, automated
`clock load balancing, and local clock bufl'er clustering. The
`clock distribution network contains four stages: a large global
`clock bufler, a clock tree, 500 local clock splitters, and local
`
`Page 4 of 8
`
`The clock tree is designed in a pseudogrid-spine network.
`Thick metal levels M6 and M5 are used for the primary global
`clock wiring. Four M5 spines run parallel for 3 mm, and
`M6 is used to connect the spines to form a grid network.
`Wiring levels M4 through M2 are used to connect clusters
`of clock splitters to the spines, and total wire lengths are
`restricted to 500 pm. If the 2.5-V-technology microprocessor
`implements six levels of metal, the improved RC delay from
`copper interconnect reduces clock latency from 170 to 85 ps
`and improves the clock tree skew from 55 to 35 ps, as shown
`in Fig. 5. This improvement in clock skew helps reduce the
`number of early mode fast paths. The copper interconnect
`allows the use of narrow metal lines, which reduces inductance
`efiects; an aluminum interconnect could produce similar RC
`skew by using wider lines, but the increased inductance would
`afiect skew significantly.
`Because additional clock skew directly impacts the process
`cycle time, the local clock splitter and local clock bufl'er must
`deliver accurate clock signals to the latches. Therefore, the
`number of local clock buffers was increased from eight to
`24, with each buffer driving a smaller restricted load range.
`The restricted bulfer load capacitance range reduces clock
`bufl'er skew from 100 to 20 ps. Sofiware tools allow automated
`repowering based on wire and latch capacitances. The low RC
`interconnect and smaller clock butfer load capacitance range
`improves the distribution of a falling C1 edge at the latch
`boundaries, as shown in Fig. 6, which compares the 2.5-V
`technology to the 1.8-V technology.
`Critical components must be adjusted when a phase-locked
`loop (PLL) is remapped from a 2.5-V to a 1.8-V technology.
`The PLL [3] was originally designed for a 2.5-V CMOS
`technology. The critical components examined during a tech-
`nology remap are the phase detector gain, voltage reference
`cter current, charge-pump current sources,
`feed-forward
`current sources, and voltage-controlled oscillator (VCO) gain.
`Statistical analysis is performed for various parameter changes
`such as channel length, threshold voltage, temperature, power
`supply, and process mistracking deviations. Open-loop and
`
`

`
`AKROUT at al_: 480-MI-lz RISC MICROPROCFSSOR
`
`1613
`
`Fig. 9
`
`74‘I
`E
`5
`53
`
`g
`I
`
`
`
`1.8V Technology
`
`NumberofLatches
`
`o 7
`
`so
`
`1oo
`(ns)
`
`Fig.6. Clockslrewofall1'allingC1_
`
`D60
`
`GND
`
`Fig. 7. Volmge reference circuit.
`
`closed-loop circuit simulations as well as closed-loop behav-
`ioral time-domain models are used to optimize the PLL for
`damping coeflicient and to improve stability of the VCO pole,
`phase error, and jitter.
`Analog circuit operation becomes diflicult when the power
`supply is scaled because MOS device threshold voltage and
`dc operating points are not scaling proportionally. The voltage
`reference circuit consists of a pair of ratioed diodes (D6 and
`D60), a pair of ratioed NMOS transistors (N1 and N2), and a
`pair of load PMOS transistors (P3 and P4), as shown in Fig. 7.
`As the technology is scaled, the diode forward bias remains
`
`constant, the MOS device dc bias condition (Vg_,.—V,) scales
`by 0.85)<, and the power supply scales by 0.72x. Thus, as
`the power supply is lowered. the voltage-reference-transistor
`operating points move from saturation into the linear region.
`When the transistors are in the linear region of their operation.
`the charge pump stops fimctioning as an infinite current source
`and operates with poor stability over process, temperature.
`and voltage. The voltage-reference-transistor operation in the
`saturation region is guaranteed by converting NMOS transis-
`tors (N1 and N2) from standard threshold devices to zero V,
`devices and PMOS transistors (P3 and P4) from standard V,
`to low 1/} devices. The improvement in the voltage reference
`circuit is measured through transistor N5 (Fig. 8).
`
`VII. TIMING AND PERFORMANCE
`
`The 1.8-V technology improves the frequency of the pro-
`cessor by 27%, while the logic, circuit, and floor-planning
`
`Page 5 of 8
`
`1 .50
`
`1.75
`
`2.00
`
`2.25
`Voltage (V)
`
`2.50
`
`2.75
`
`3.00
`
`Fig. 10.
`
`1",,....( versus voltage for critical path delays.
`
`enhancemts contribute a 17% improvent. In addition, the
`copper wires for this design result in a 12% improvemt
`in path delay, while low V, devices add another 6.5% to
`the maximum frequency. Total
`improvement is 77%. One
`of the critical path delays is shown in Fig. 9. The timing
`delay is segmted into custom gate delay, standard-cell gate
`delay, and interconnect delay for the 2.5-V technology, 1.8-V
`technology without copper interconnects or low 1'} FET’s, 1.8-
`V technology with copper interconnects and low V, devices,
`and 1.8-V technology with circuit enhancents.
`A timing analysis was performed at 480 MHZ, 2.0 V,
`85°C, and all process parameters were centered at 1-sigma
`fast—except for Leg‘, which was centered at 3-sigma fast—to
`represent a chip design line-tailored to the fast corner. The
`fast comer of the process dist:ribution also shows more RC
`eflects. Fig. 10 shows the late-mode timing for revisions 1.0
`and 2.0 of the 1.8-V microprocessor and the timing of the
`
`
`
`1.0
`
`1.2
`
`1.4
`
`1.6
`
`1.8
`
`2.0
`
`Power Supply Voltage (V)
`
`Fig. 8. Voltage reference current source N5.
`
`Custom
`
`Standard-Cell
`
`Interconnect
`
`‘
`
`i
`
`i
`
`2.5V Technology
`
`1.8V Technology
`wl Aluminum
`
`1 .8V Technology
`w/copper
`and Low Vt
`1.8V Tech nology
`wl Circuit
`Enhancements
`
`
`
`A 1.8V Microprocessor
`Revision 2.0
`
`0 1.8V Microprocessor
`Revision 1.0
`
`I I
`
`I I I
`
`

`
`1614
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`IHI JOURNAL OF SOLID-STATE CIRCUTIS, VOL 33, N0 11, NOVEMBH{ 1998
`
`3.3V
`8 stem
`C ock
`
`0V
`2.0V
`
`Internal
`Clock
`
`L2
`Clock
`
`0V
`3.3V
`
`V
`
`0V
`
`80MHz
`
`430"“:
`
`240MHz
`
`Fig. 11.
`
`Internal and L2 clock
`
`2.5-V microprocessor; the slope of the revision 2.0 data is 20
`MHz/100 mV.
`
`VIII. SYSTEM AND L2 CACHE INTERFACE
`
`A new option for the L2 bus interface with the L2 cache
`is featured on the 480-MHZ microprocessor. The present 3.3-
`V interface is maintained with an improved 1/0 that allows
`the internal voltage to be reduced to 1.8 V without creating
`additional stress on the thin gate oxide in the drivers; this I/O
`also provides good 50-Qm impedance matching to the external
`pins. Fig. 11 displays the internal clock to 60x bus ratio of
`6: 1 and the L2 clock to an internal clock ratio of 1 :2. When
`
`the L2 cache is fabricated in a 1.8-V technology, a second L2
`bus I/O can interface betwe the 1.8-V internal supply and
`the 1.8-V external L2 bus by changing the vies between M2
`and M3; this enables a faster L2 bus data transfer between the
`microprocessor and L2 cache. When using the 1.8-V receivers
`and drivers in a multichip module or multimodule card, the
`L2 cache and the microprocessor are expected to interface
`witha 1:1 or2:3 ratio ofL2 bus frequencyto internalclock
`frequency.
`The improved I/0 incorporates several advances in mixed-
`voltage I/O interface techniques. The off-chip driver
`is
`designed to provide low voltage transistor transistor logic
`(LVTTL)-compliant off-chip interface levels with a total swing
`of 0-3.3 V, using a dual power supply of the 1.8-V core and
`a 3.3-V second I/O supply. By incorporating voltage-dividing
`techniques to protect individual transistors from overvoltage
`stresses,
`the I/O circuit design provides the capability of
`supplying a 3.3-V output level using conventional transistors
`in the 1 .8-V technology. Key enhancements over prior designs
`include a “pulsed” voltage translation circuit that converts a
`0-1.8 V signal swing into a 1.8-3.3 V signal swing for output
`device predrive. This pulsed circuit eliminates the problems
`of prior voltage-translation designs that exhibit both poor
`throughput performance and large dc power consumption.
`Also, an additional circuit provides a precisely controlled
`reference voltage to drive the final output transistors, which
`eliminates a sensitivity to the voltage separation of the core
`and I/O supply identified in prior designs and
`power consumption. This reference voltage circuit renders
`the design virtually immune to performance—and impedance-
`matching variations caused by the collapse of the difference
`between the core and I/O supplies because the core voltage is
`increased to improve core logic performance. The driver
`
`Page 6 of 8
`
`impedance control over a
`is also source-terminated for
`wide process range, and the source-termination technique
`inherently provides a robust electrostatic discharge protection
`network. The on—chip receiver is also enhanced with a zero
`V, input clamp device, giving overvoltage stress protection to
`sensitive receiver circuits and guaranteeing that the receiver
`is LV'I'I'L-compliant.
`
`IX. CONCLUSIONS
`
`successfully
`The 480-MHz RISC microprocessor has
`demonstrated improvements when
`from a 2.5-V
`technology to a 1.8-V technology. Design improvements
`include additional bufl'ers for early mode, circuit-design
`changes, global clock latency, and skew reduction. Technology
`improvements include a copper interconnect with a 0.12-
`pm Leg and low V, FET’s. These changes culminate into
`a 480—lVII-Iz RISC microprocessor at 2.0 V, 85°C,
`that is
`manufactured in a fast process.
`
`REFERENCES
`
`[1] P. Reed, M. Alexander, J. Alvarez M. Brauer, C.—C. Chao, C. Croxtaon,
`L. Eisen, T. Le, T. Ngo, C. Nicoletta, H. Sanchez, S. Taylor, N.
`Vandcrschaaf,andG.Gerosa,“A250MHz51VRISCmicroprocessor
`with on-chip L2 cache controller," in ISSCC Dig. Tech. Papas, Feb.
`1997, pp. 412-413.
`[2] D. Edelstein, J. Heidenreich, R Goldblatt, W. Cote, C. Uzoh, N. Lustig,
`P.Ropcr,T.McDeVi!t,W.Motsi1TiA SimoI1.J.Dukovic,RWachnik.
`H.Rathore,R Schulz,andL. Su,"Fulloopperwir*inginasub-0.25 pm
`CMOS ULSI technology,” in EE Int. Electron Device Meeting Tech.
`Dig., Dec. 1997, pp. 773-776.
`[3] J.Alvarez,I-ISanchez,G.Gerosa,andRCountryman,“Awide—
`bandwidth low voltage PLL for PowerPC Microprocessors,” EH J.
`Solid-Slate Circuits. vol_ 30, pp. 383-390, Ail’. 1995.
`
`Chelrih Aln-out received the B.S. and MS. degrees in physics and the PILD.
`degree from the Univerfity Pierre and Marie Curie, Paris, France, in 1981,
`1982, and 1984, respectively.
`HejorinedIBM, Essonnes, France, in 1984 and worked inbipolar technology
`andtheninCMOS teclmologyforcadremacroswithinmicroprocessms. He
`also held several nnnrgement positions developing telecommunications prod-
`ucn In l994,hejoinedIBM,EssexJunetion, VT,wmlringonrnicroprocessor
`designasTedmicalLeadandlaterasManager.HeanrenflyisManagerof
`advanced PowerPC rniuoprocessor development at IBM, Austin, TX.
`
`JohnBi:lasreoeivedtheA.S.deyeeinelec1ricalengineeringfiomLincoln
`Technical Institute, Allentown, PA in 1981 and the B.S_E.E. degee from
`Capitol College, Laurel, MD, in 1989.
`HeisanAdvisoryEngineu'specializinginvery—large—scale-integration
`circuit design in the applicatiomqrecific integrated circuit core development
`
`advanced technology development, all with IBM. He has received five U.S.
`patans.
`
`
`
`Miles Canada received the B.S. degree in electrical
`
`engmeenn''gfiomtheUnrversny'' oflllrnfi
`and the BA. degree in physics from Augustana
`College, Sioux Falls, SD, in 1978.
`He joined IBLL Fishkilh NY, in 1979, working
`on emitter-coupled logic and SRAM products until
`1992. Sincetherrhehasworkcdonnricroproces
`sot circuit design at IBM Microelectronics, Essex
`Junction, VT.
`
`

`
`AKROUT et al.: 480-MHz RISC MICROPROCESSOR
`
`1615
`
`Duane Cawthron, photograph and biography not available at the time of
`publication.
`
`James Corr received the B.E.E. degree from the University of Minnesota,
`Minneapolis St. Paul, and the M.S. degree in electrical engineering from
`California State University.
`He is an Advisory Engineer in the Advanced PowerPC Development De-
`partment, IBM, Essex Junction, VT, where he is involved in hardware design
`verification and test and diagnostics strategy development. Since joining IBM
`in 1979, he has been involved in both design and manufacturing of various
`microprocessors and logic devices, as well as design and development of
`application-specific integrated circuit design systems and system design tools.
`Much of this work has been in the area of automated test and diagnostics
`systems. His work on this new reduced instruction set computer processor
`has been primarily in the area of hardware verification and functional pattern
`diagnostics methodologies.
`
`Bijan Davari (S’77–M’79–SM’92) received the
`M.S. and Ph.D. degrees in electrical engineering
`from the Rensselaer Polytechnic Institute, Troy,
`NY, in 1984.
`He joined IBM’s research division at the T. J.
`Watson Research Center, Yorktown Heights, NY.
`Since that time, he has worked on various aspects of
`scaled CMOS and BiCMOS technologies, including
`device scaling and process integration. He defined
`and developed a selectively scaled 0.25-m CMOS
`technology at 2.5 V, demonstrating significant
`performance and power-reduction improvement over CMOS technologies
`at 3.3 V. This work has set the direction and the supply voltage for the post-
`3.3-V CMOS generations. He presently is the Director of the Advanced Logic
`and SRAM Technology Development Department in IBM’s Semiconductor
`Research and Development Center, Hopewell Junction, NY. His department’s
`activities include the development of CMOS technologies down to sub-0.1
`m for logic and SRAM products, silicon on insulator, embedded DRAM, and
`nonvolatile RAM. He is the author or coauthor of more than 70 publications
`in various aspects of semiconductor devices and technology.
`Dr. Davari is an IBM Fellow.
`
`Robert Floyd received the B.S.E.E./C.S. degree
`from the University of Connecticut, Storrs, in 1978.
`For most of his 20 years with IBM, he has worked
`in chip integration for microprocessors.
`
`Robert Houle received the B.A. degree in mathe-
`matics and the B.S. degree in electrical engineering
`from the University of Vermont, Burlington, and
`the M.S. degree in electrical engineering from the
`University of Connecticut at Storrs.
`He joined IBM in 1980. Since 1981, he has been
`involved in the design of microprocessors.
`
`Paul Kartschoke received the B.S.E.E. degree from
`Rutgers—The State University, New Brunswick,
`NJ, in 1990 and the M.S.E.E. from the University
`of Virginia, Charlottesville, in 1992.
`He joined IBM in 1992 and currently is a Staff
`Engineer performing circuit design on a micro-
`processor project. He has worked on several mi-
`croprocessor projects specializing in programmable
`logic arrays, microprocessor circuit development,
`and various circuit tools. He is the author of several
`papers and has received eight patents.
`
`Diane Kramer received the B.S. degree in electrical engineering from the
`University of Vermont, Burlington, VT.
`She joined IBM in 1988 and since has been involved in both process
`development and microprocessor design.
`
`Peter McCormick (S’64–M’67)
`received the
`B.S.E.E.
`degree
`from Worcester Polytechnic
`Institute, Worcester, MA, in 1965 and the M.S.E.E.
`degree from Michigan State University, East
`Lansing, MI, in 1967.
`He joined IBM, East Fishkill, NY, in 1967 and
`transferred to Manassas, VA, in 1970 and to Essex
`Junction, VT, in 1978. His work experience has
`been in bipolar and field-effect
`transistor circuit
`and chip design spanning SSI, LSI, and VLSI
`digital
`integrated circuits. Development projects
`have included master slice, master image, and custom chip designs. He
`currently is a Senior Engineer in the PowerPC Microprocessor Development
`Group of the IBM Microelectronics Division.
`
`Stephen Geissler received the B.S.E.E. degree from the Rochester Institute
`of Technology, Rochester, NY, in 1981 and the M.Eng. degree from Cornell
`University, Ithaca, NY, in 1982.
`He joined IBM in 1982 and is currently an Advisory Engineer responsible
`for phase-locked loop and high-speed clock circuit design. He has also been
`involved in a device design and process integration for CMOS DRAM and
`logic technologies. He is the author or coauthor of 12 publications and has
`received seven U.S. patents.
`
`Ronald Goldblatt, photograph and biography not available at the time of
`publication.
`
`Norman Rohrer received the B.S. degree in physics
`and mathematics from Manchester College, North
`Manchester, IN, in 1987 and the M.S. and Ph.D.
`degrees in electrical engineering from The Ohio
`State University, Columbus,
`in 1990 and 1992,
`respectively.
`He has been with IBM, Essex Junction, VT, since
`1992, where he works in the PowerPC microproces-
`sor area. His interests include microprocessor de-
`velopment, VLSI, and technology interactions with
`CMOS circuit design.
`
`Page 7 of 8
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 33, NO 11, NOVEMBER 1998
`
`Gerard Salem received the B.S.E.E. degree from
`the Polytechnic Institute of New York, Brooklyn, in
`1983.
`He is a Logic Design Engineer currently working
`on design, bringup and debug, and hardware/model
`critical path analysis of PowerPC processors at IBM
`Microelectronics, Essex Junction, VT. He joined
`IBM in 1983 and worked on ES/9000 processor
`design, recovery design, and bringup. In 1993, he
`joined PowerParallel and worked on RS/6000 SP
`communication adapter design, bringup, and test.
`He has filed several patent applications.
`
`Ronald Schulz, photograph and biography not available at
`publication.
`
`the time of
`
`Lisa Su (S’92–M’95) received the B.S., M.S., and Ph.D. degrees in electrical
`engineering from the Massachusetts Institute of Technology, Cambridge.
`She joined Texas Instruments in 1994 as a Member of Technical Staff
`working in the SOI Process Integration group. Since 1995, she has been with
`the IBM Semiconductor Research and Development Center. She currently is
`Manager of CMOS front-end process integration.
`
`Linda Whitney, photograph and biography not available at the time of
`publication.
`
`Page 8 of 8