`
`IP Bridge Exhibit 2015
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`TSMC v. IP Bridge
`IPR2016-01379
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`Page 0001
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`IP Bridge Exhibit 2015
`TSMC v. IP Bridge
`IPR2016-01379
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`aP9731n."6102RPI
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`2000e
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`g
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`IPR2016-01379 Page 0002
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`HANDBOOK OF
`
`SECOND EDITION
`
`VLSI MICROLITHOGRAPHY
`
`Principles, Technology, and Applications
`
`IPR2016-01379 Page 0003
`
`

`

`HANDBOOK OF
`
`VLSI MICROLITHOGRAPHY
`
`Principles, Technology, and Applications
`
`Norwich, New York, U.S.A.
`
`SECOND EDITION
`
`Edited by
`
`John N. Heibert
`
`Motorola, Inc.
`
`Phoenix, Arizona
`
`NOYES PUBLICATIONS
`
`Park Ridge, New Jersey, U.S.A.
`
`WILLIAM ANDREW PUBLISHING, LLC
`
`IPR2016-01379 Page 0004
`
`

`

`Library of Congress Catalog Card Number: 00-028173
`ISBN: 0—8155-1444-1
`Printed in the United States
`
`Published in the United States of America by
`Noyes Publications / William Andrew Publishing, LLC
`13 Eaton Avenue
`
`Norwich, NY 13815
`1 -800-932—7045
`www.knove1.com
`
`10987654321
`
`Copyright © 2001 by Noyes Publications
`No part of this book may be reproduced or
`utilized in any form or by any means, elec—
`tronic or mechanical,
`including photocopying,
`recording or by any information storage and
`retrieval system, without permission in writing
`from the Publisher.
`
`CIP
`
`Library of Congress Cataloging-in-Publication Data
`
`Handbook of VLSI Microlithography / [edited] by
`John Helbert.——2nd edition
`p.
`cm.
`IHCIUdeS bibliographical references and index.
`ISBN 0-8155-1444—1
`
`1. Integrated circuits-—Very large Scale integration. 2. Microlithography.
`l. Helbert, John N.
`
`TK7874 .H3494
`621.3815’31—-dc21
`
`2001
`
`OO_028173
`
`IPR2016-01379 Page 0005
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`

`

`5.0 APPLICATIONS AND SPECIAL PROCESSES
`
`5.1
`
`Future Device Demands
`
`Resist Technology
`
`259
`
`lithography usage has continued to be delayed for years.
`
`Integrated circuit lithographic design rules have historically de—
`creased over time, and will continue to do sow—at least to the O.l~0.07
`micron level over the next 2—5 years. The driving forces for these increased
`circuit packing density demands are cost per function decreases, faster
`switching speeds, and lower chip power consumption. These new design
`rules will necessitate higher resist and lithographic tool resolution perfor-
`mance. Since the etching technology exists and tool contrast is only
`improved by the purchase of expensive new equipment, the goal for some
`process engineers simplifies to one of improving resist process perfor—
`mance. The processes in this section address this issue. Quoting L.F.
`Thompson of AT&T Bell Labs, “It’ s all in the processing.” Resist process—
`ing is really the only variable left to most lithographic engineers with which
`they can influence device production, because the photolithographic tool
`aerial image limit is basically fixed by the manufacturer for a given
`generation of tool.
`Conventional single—level positive photoresist technology has re—
`cently progressed rapidly, especially in the DUV class, but may be incapable
`of providing the necessary resist imaging required for the next generation
`of chips, i.e., less than 0.1 micron CD. Here, resist imaging thickness is the
`key issue to meet RIE etch masking requirements. Therefore, new resist
`processing technology (for example, surface imaging, like Desire process—
`ing) may be needed. Furthermore, processes which extend the performance
`levels of existing projection exposure tools or provide depth of focus relief
`are very attractive due to the increasing cost of new higher performance
`exposure equipment and the return on net asset demands placed upon chip
`sales of new devices to pay for these tools.
`While a great deal of resist process research has been occurring to
`extend phototool lifetime, advances in reduction lens design and reflective
`optical wavelength reductions have also been occurring. As a result, optical
`lithography continues to relegate direct—write e—beam lithography to a quick
`turn around Application Specific IC (ASIC) role, and extensive x-ray
`
`IPR2016-01379 Page 0006
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`

`260
`
`Handbook of VLSI Microlithography
`
`water solublc)barrier layer coating for the lithographic trilayerprocesses, as
`
`Multilayer processing techniques, where layers of radiation sensitive
`(top), non—photosensitive organic, and/or inorganic materials sandwiched
`together to become the total patterning layer, have become common in
`semiconductor and computer manufacturing R&D labs. (See Fig. 1 14.)[3]
`Due to their complexity and problems that have appeared at bilayer interfaces,
`these techniques have not been widely accepted in high volume production.
`Photolithography image edge and dimension quality is limited by
`two basic effects, bulk and substrate reflectivity.[13][154] The bulk effect
`arises when lithography patterns are required at two different topographical
`layer levels of the vertically—fabricated monolithic circuit. Reflectivity
`effects occur when patterned areas of the circuit have different reflectivity
`coefficients, as well as topographical levels.
`Lithographic exposure tool resolution performance can be influ-
`enced by resist processing. Stover et al.[155] have shown K from the
`resolution equation, R = K wl/2NA, is directly influenced by multilayer
`processing: wl is the monochromatic light wavelength and NA is the
`numerical aperture of the projection optics lens system; K is typically 0.8
`in manufacturing with single layer resist processes but can be as low as 0.5
`with multilayer processes.[156] Linewidth control is also directly affected
`by resist processing, and greater resist image critical dimension control can
`be achieved through multilayer processingm] combined with anisotropic
`reactive—ion etching technology.
`Lin[157j has done extensive research in bilayer systems, multilayer
`processes utilizing a UV sensitive material on top with a DUV absorbing
`or non—absorbing system underneath. This type of multilayer system has
`seen limited circuit fabrication application, because it is plagued by
`deleterious interfacial layers formed between layers at coat.[13][158] These
`problems have been solved by various treatments both before and after
`image formation, but bilayer technology has taken a backseat primarily to
`dyed thick single—layer photoresist processes.[159] Some bilayer processes
`are reported to be free of interfacial mixing problemstOJ and the organic
`ARC process described is a usable bilayer system.
`Trilayer systems[ 161] utilize an intermediate layer between the photosen-
`sitive top layer and the virtually developer—insoluble oxygen RIE patterned
`bottom layer. It is usually deposited by low temperature (< 250°C) thin film
`
`5.2
`
`Introduction to Multilayer Applications
`
`deposition techniques, but can also be applied as a liquid spin—on—glass
`solution.[162]‘[164] The middle layer can also be a spun organic polymer (also
`
`IPR2016-01379 Page 0007
`
`

`

`0l0nhaTt.mSeR .8:ch3
`£3.5::22qumoMass2355:REEDU:5235
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`
`IPR2016-01379 Page 0008
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`

`262
`
`Handbook of VLSI Microlithography
`
`opposed to RIE trilayer processes where the middle hard mask material
`must be RIE etched and cannot be developed by base developers or water.
`
`While the former technique is usually void of interfacial mixing layer
`
`problems, the latter technique can exhibit this problem intermittently.
`
`All of the multilevel processes described are successful to some
`degree in relieving resolution and linewidth control limitations of current
`single-layer optical exposure equipment. Future device fabrication require—
`
`ments and the application of high numerical aperture exposure equipment,
`
`however, will most likely create the need for multilayer processes at one or
`two critical device levels.
`
`5.3
`
`Introduction to MLM Lithography
`
`The requirements of VLSI/ULSI multilevel metallization (MLM)
`systems have led to numerous challenges in the phOtolitho graphic and etch
`areas. These challenges arise from two inter-related sources: the continuing
`
`trend to smaller geometries and the new materials that must be used to build
`
`a successful MLM. Smaller geometries often create a need for new materi—
`
`als, and the ability to process those materials can limit usable geometries.
`Photolithography and etch technologies with the capability of producing
`
`submicron MLM structures are an integral part of the successful fabrication
`
`of the high density, high performance, and highly reliable interconnect
`
`technologies of the nineties and beyond.
`
`For devices with multilayer metal (MLM) interconnects, these indi—
`
`vidual layers are insulating dielectrics or metallic interconnect layers. The
`
`ability to produce high quality MLM layers depends upon both the litho—
`
`graphic tool imaging capability, quantified by the Modulation Transfer
`
`Function (MTF) (see Ch. 5) of the tool optics which in part depends upon
`
`quality of the stepper projection lens (i.e., NA and MTF), the resist contrast
`
`the tool objective lens numerical aperture (NA), and the resist process
`quality or CMTF.[3][165] The electrical yield for MLM device layers depends
`upon these quantities for device element packing density and the ability of
`
`the lithographic tool to align layer to layer; the combination of CD control
`
`and alignment control represents the total overlay capability of the system
`
`which must be better than that required by the design rules for the circuit.
`
`5.4 Applications
`
`It is well known that lithographic image sizes, better known as critical
`dimensions orjust CDs, and CD variation are governed to first order by the
`
`IPR2016-01379 Page 0009
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`Resist Technology
`
`263
`
`et a1. [76] have demonstrated similar results, and an approximately 60% gain in
`
`or CMTF, and the degree of the resist process optimization.[3][105][]65] As
`CDs get smaller and the lens and resist parameters approach their practical
`limits, secondary characteristics such as lens astigmatism and proximity,
`substrate reflectivity, topographical or bulk effects, and local resist thick—
`ness variation begin to be significant and have to be controlled along with
`the primary effects for successful device fabrication, especially at less than
`0.5 pm polysilicon gate, or any other layer for that matter, dimensions for
`advanced CMOS or BICMOS device fabrication.
`Dyed and Thinned Single Layer Resist (SLR) Processes. The two
`most obvious things to do to improve resist imaging performance on the
`most difficult substrates (i.e., those requiring greatest resolution and with
`reflective topography as for device isolation, gate, and MLM metal and via
`levels), is to reduce the resist thickness and add dyes to it, respectively.
`Unfortunately, resist thinning is most feasible with multilevel lithography
`processes,[166] where a thin top resist layer is allowable. Resist thinning in
`itself accomplishes nothing towards reflective image notching relief, the
`main observed problem for reflective topographical gate or MLM situa—
`tions. Furthermore, resist thinning presents a severe problem to step
`coverage and metal etching because of poor selectivity, and is in fact usually
`prohibitive. All of these negatives aside, resist thinning has been shown by
`IBM researchers[167] to improve linewidth control by 15 % and focus control
`by 35%, when and if it is feasible to do it. Therefore, the full advantages of
`resist thinning may be really only achievable through bi— and trilayer
`lithographic processes, further reinforcing the restrictive applicability of
`resist thinning.
`The more practical solutiOn to reflective notching problems, those
`observed on reflective surfaces due to either feature topographical or metal
`grain boundary relief structures, is provided by resist dyeing. Most device
`fabrication areas will select this option over multilayer Portable Conform—
`able Mask (PCM)[166] processes due to greater simplicity and lower costs.
`The resulting dyed and usually thicker (~2 microns) material is still a single
`level resist process, but withoutlthe added complexity of multilayer pro-
`cesses; note also, by going to thicker dyed resists relief from topography
`induced CD variation, the well—known “bulk effect” is also achieved. Dyeing
`resists requires a price be paid in lower resist contrast[168] and greater
`exposure time,[169] but dyeing does provide greater process latitudel97] and
`reflective notching can be effectively eliminatedwé] or at least minimized-
`Sandia workerslno] have provided a dyed system for H and G line
`steppers which has a very small exposure penalty, just 15 mJ/cmz. Bolson
`
`IPR2016-01379 Page 0010
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`264
`
`Handbook of VLSI Microlithography
`
`exposure latitude was achieved or a reduction inkI from the Raleigh resolution
`equation from 1.1 to 0.6 was effectively obtained. On the negative side,
`adding dye to the resist formulation may lead to a larger standing wave
`foot,[171] lower depth of focus (Table 5), and reduced imageedge wall angles
`consistent with the observedbulkcontrastreductions reportedby Pampalone.[168]
`Most dramatically, Brown and Arnoldnn] have observed a 3-fold increase
`in CD exposure latitude, a result which explains the wide acceptance of this
`technique for metal layer lithography by older mature production fab lines , lines
`where metal CDs are larger and advanced planarization techniques beyond
`POT processing are not common (see planarization section).
`SLR Image Reversal (IREV). Positive photoresist image reversal
`(i.e., negative toned imagery from a positive toned resist) is a processing
`technology which addresses the deficiencies of single-layer dyed resists.
`Moreover, IREV can be accomplished on dyed material to achieve the best
`of both worlds, namely, relief from topographical or bulk effects and
`reflective notching minimization. Over the years, many papers have been
`published on this subj ect.[172]_[180] The salient contents of those papers will
`be reviewed and compared. The main focus of this section is on single level
`thermal induced reversal processes for AZ 5214.
`Image reversal is an alternative to conventional positive photoresist
`technology. Briefly, a single layer of positive photoresist is exposed using
`a projection aligner, reversed by either doing a post exposure thermal
`treatment on a hotplate or by adding a base to the resist, flood exposing and
`developing. The result is a negative toned image with a controllable edge
`wall angle, something dyed resists with conventional processing cannot
`deliver. The IREV processes are capable of printing images previously
`unattainable with the given exposure tool, thus, extending the resolu—
`tion and focus latitude performance of the alignment tool, and the life of it
`
`were also reported.[179] AZ researchers further reported a bulk contrast
`
`as a capital asset.
`Marriott, Garza, and Spak have written the definitive paper on
`thermal image reversal.[179] Using both theoretical PROSIM simulation
`and empirical methods, the AZ 5214 IREV process has been optimized, and
`good agreement between theoretical images and real images obtained. The
`process was optimized for photospeed, resolution, focus and CD latitude,
`and vertical edge wall by adjusting the developer concentration to 0.21 N
`MF—312 (90 secs), setting the PEB temperature to l 10°C, and by using a
`flood exposure after PEB. This data has been independently verified at
`Motorola (see Fig. 1 15). An improvement of 1.25 micron in focus latitude,
`l 50% improvement in CD control and a 8° improvement in image edge wall
`
`IPR2016-01379 Page 0011
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`

`

`Resist Technology
`
`265
`
`1.2 MICRON/UV-3/B49B
`#74..__—.—-— __,_
`
`1.8 MICRON/UV—3/H9P
`.__._.__..
`
`performance improvement of roughly 200% for IREV AZ 5214 over that
`for the positive performance mode. Consistent edge wall imagery improve-
`ment can be seen when comparing Figs. 115 and 116, where Fig.
`l 16
`portrays images with edge wall angles more typically observed from
`normal positive tone performance.
`
`Note, the edge walls are poorer than those for both IREV processes.
`
`
`
`4.5 MICRON
`
`4.5 MICRON
`
`Figure 115. AZ—5214 thermal tone reversal process edge wall profiles illustrating vertical
`edge walls.
`
`AZ 5214
`
`OFPR-800
`Negative Mask
`
`OFPR—800
`Positive Mask
`
`Figure 116. Edge wall profiles for conventionally developed positive photoresist images.
`
`IPR2016-01379 Page 0012
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`

`266
`
`Handbook of VLSI Microlithography
`
`All in all, it is felt that the image reversal process advantages may
`overshadow the disadvantages for certain critical device fabrication levels,
`where standard resist processing technology simply cannot satisfy the
`future lithographic imaging requirements. Furthermore, work by Gij sen et
`al. (see Ref. 90 of Ref. 129) has demonstrated image reversal behavior for
`dyed positive photoresist without degrading edge wall slope advantages,
`thus providing a process with relief from integrated standing wave and
`pattern scattering effects in addition to the relief from the bulk effect
`provided by the undyed reversal process.
`Resist Processes For Reflective and Topographical MOS Gate
`Situations.[181] In this section, an example, silicided, 0.5 um polysilicon
`gate layer is focused upon and all data presented is for that critical device
`layer. Resist simulations of CDs and substrate reflectivities were obtained
`employing the version 2.2 PROLITH simulation package.
`The problem or dilemma faced early in the 0.5 pm work dealt with
`polysilicon CDs which were larger in a packed line device configuration
`than when they were isolated. This was just the opposite to that which was
`typically observed for metal or for single crystal silicon substrates and even
`flat polysilicon substrates.[182][183] Furthermore, the results of Ref. 184
`have demonstrated that the effect gets larger the smaller the pitch, and those
`authors actually recommended that this effect be corrected for at design by
`differential biasing.
`On flat surfaces, with all other factors being negligible, the isolated
`CDs can be anywhere from 0.03—0.06 pm larger than that for the tightly
`packed features, a bias which is not negligible at 0.5 pm CDs, i.e., it’s
`greater than 10% without any normal processing variation; this bias can
`actually get as large as 0.08 pm depending upon how large the normal
`photo/etch bias is. Figure 1 17 contains PROLITH 2 simulation data
`consistent with these empirical results, therefore, another mechanism must
`be controlling the CD behavior on the polysilicon gate device test structures
`other than the normal iso/dense resist CD bias effect.
`
`regiOHS,[185] to allow for the possibility for the resist polysilicon CD to be
`
`PROLITH swing curve simulations, plots of resist CD vs. resist
`thickness, for silicon and polysilicon substrates were also very similar as
`found in Fig. 1 18. But, when swing curves for polysilicon resist images on
`raised field oxides are compared to those for images on topographically
`lower active device regions, the curves are shifted along the resist thickness
`axis for both isolated and dense gate features.[185] This result now provided
`a mechanism, i.e., the resist thickness differences between field and active
`
`IPR2016-01379 Page 0013
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`

`

`Resist Technology
`
`267
`
`‘IWSOUUED
`
`‘DIWWKED
`
`larger or smaller depending on polysilicon underlying structures. Notice,
`however, that although the data of Ref. 185 shows the effect of swing curve
`shifting for the first time it still cannot account for the Observed gate CDs
`being larger for packed features, so a closer look is required.
`
`lines. The simulations are verified empiracally in the SEM picture on the top.
`
`15 16 17 18’19 20 21 22 23 24 25 26 27 28 29 30
`O
`0
`0
`0
`0
`O
`0
`0
`0
`0
`0
`O
`0
`0
`0
`0
`
`Figure 117. PROLITH generated polysilicon resist CD vs. exposure for isolated and packed
`
`IPR2016-01379 Page 0014
`
`

`

`Handbook of VLSI Microlithography
`
`
`
`Subslrala
`
`'—Ei‘— Bans S'I
`
`---o— 3M poly on Si
`
`smaller than the isolated gates as pure “proximity effect” would dictate.
`
`This leads to lens astigmatism. For the Canon 0.52 NA lens employed,
`the astigmatism was :10 nm, so, this contributor was negligible. This was
`a valuable piece of information since the packed CDs were oriented 90
`degrees off 0 or horizontal to the isolated transistor gates. Figure 1 19 further
`illustrates the CD distributions for isolated horizontal gates are also well
`separated from the vertical isolated gates as well as smaller. As a sanity
`Check, swing curves were generated for silicon and polysilicon test wafers
`with absolutely no underlying patterns or topography. The polysilicon CDS
`for these images were as predicted by normal proximity, and reversed in
`order from those observed for live product wafers (compare the data of Fig.
`120 to that of Fig. 118 and 119). So, when the substrate is flat and
`unpatterned, there are no swing curve phase shifts and the packed gates are
`
`FIESIST THICKNESS {urn}
`
`Figure 118. Resist sensitivity vs. resist thickness for gate CDs on polysilicon and silicon
`wafers. Linewidth vs. thickness would look the same if plotted.
`
`IPR2016-01379 Page 0015
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`

`

`Resist Technology
`
`269
`
`
`
`
`
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`IPR2016-01379 Page 0016
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`

`

`Handbook of VLSI Microlithography
`
`Data from "pol‘ymv"I
`
`(um)
`
`Dim.
`Critical
`
`previous patterns.
`
`Bare Silicon swing curves for D75FP05
`(All
`three cd structure types)
`
`El
`
`0
`3
`
`venical Cd
`
`horizontal Cd
`sp1il—bridge Cd
`
`11000
`
`Thickness A
`
`Figure 120. CD vs. thickness of resist for the three gate types on bare silicon wafers with no
`
`IPR2016-01379 Page 0017
`
`

`

`How can the data of Fig. 119 be rationalized? The answer lies in the
`
`data of Fig. 121. Here, the swing curves have been generated for the three
`different gates on live BIMOS product wafers as in Fig. 1 l9; notice that the
`packed gates on field oxide, as for Ref. 185, have a dramatically different
`swing curve phase than the other curves. At resist thickness of 10,800 A, the
`split bridge packed gates are in fact larger than both the horizontal and
`vertical gates on gate oxide over active area. Hence, a mechanism or a reason
`for the observed gate CD order results is obtained, which, as for the results
`of Ref. 185, is attributed to local resist thickness variation in the respective
`gate areas. Further note, that even though there is little if any lens astigma—
`tism, the horizontal gates are also larger than the vertical gates, again
`because their swing curves are shifted even though they are at the same
`
`Resist Technology
`
`271
`
`effect. This is similar to the effect discussed above for polysilicon gates.
`
`topographical level.
`The final effect described is reflectivity, R. As for swing curves,
`polysilicon reflectivity varies sinusoidally with resist thickness due to
`standing wave interference effects. CD variation with thickness is in phase
`withR, but CD variation is usually j ust roughly in phase, or the CD variation
`on polysilicon is usually a minimum when reflectivity is at a minimum.[186]
`In conclusion, the large effects reported here must be canceled out by
`differential CD biasing at device design CAD or with OPC applied correc—
`tions. The proximity induced iso/dense CD effect contribution, which can
`be completely canceled Out or dominated by larger swing curve effects, can
`be minimized by employing improved resists.
`Device Isolation Topography Effect upon Resist Gate CD Con-
`trol.[187] First generation LDMOS devices, laterally diffused RF devices,
`are characterized by large gate pattern dimensions (i.e., 1 micron and
`greater) and mature but topography creating single hipox isolation process-
`ing. Figure 122 illustrates the severe topography created by the “bird’ 5
`bea ” of this older device isolation process. This topography creates an
`unwanted constraint upon the resist coating process, which in turn affects
`CD control in a negative way, both gate to gate and within gate for the RF
`device. In fact, the gate dimension across the RF device active area can vary
`as much as 160 nm as verified by Fig. 123, the “wavy gate effect” first
`reported in this section. If the resist thickness is measured across the active
`area, it varies in direct correlation to the CD variation consistent with the
`well known effect on CDs of varying resist thickness, the resist swing curve
`
`IPR2016-01379 Page 0018
`
`

`

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`IPR2016-01379 Page 0019
`
`

`

`Resist Technology
`
`SINGLE HIPOX ENCHROACHMENT:
`
`device isolation process.
`
`LDMOS SINGLE HIPOX PROCESS -
`1.80 pm BIRD’S BEAK
`
`Figure 122. SEM cross scction of the “Bird’ 5 beak” topography inherent to the single hipox
`
`IPR2016-01379 Page 0020
`
`

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`Resist Technology
`
`275
`
`DOUBLE HIPOX ENCROACI—IMENT:
`
`Third generation LDMOS devices, however, must have submicron
`gate dimensions (i.e., < 0.6 microns) and require much less gate image
`dimensional variation to perform within minimum acceptable device thresh—
`old tolerances. The topography minimizing or “bird’ 3 beak” reducing effect
`of the modified double hipox isolation is shown in Fig. 124. There, the first
`hipox is followed by oxide removal and another hipox to leave the wafer
`surface much flatter. The effect of this extra device isolation processing is
`improved wafer flatness as manifested by improved resist uniformity across
`the active area and the resultant gate CD control. The data of Table 22,
`clearly demonstrates a factor of four times the improvement due to the less
`topographical modified double LOCOS isolation process. The gate CD
`range along the gate for the improved isolation scheme reduces to 22 nm
`versus the 160 nm observed for the single LOCOS isolation process, and the
`gate to gate variation is only 39 nm for the new process. These CD
`improvements are dramatic and more than justify the extra process cycle
`time incurred.
`
`device isolation process.
`
`BIPOLAR DOUBLE HIPOX PROCESS
`
`Figure 124. SEM cross section of the reduced topography inherent to the double hipox
`
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`276
`
`Handbook of VLSI Microlithography
`
`Table 22. CD Families of Variation for Both Isolation Processes and
`The ARC Process With The New Isolation Processnm
`
`Variance Component Estimates
`
`
`2-MLOCOS
`
`l—LOCOS
`
`Component
`
`wafer
`site [wafer]
`
`wafer
`site [wafer]
`
`Standard Deviation
`
`3.1 x 10‘3 um
`6.3 x 10'3 pm
`
`7.67 x 10-3 pm
`20.8 x 10'3 1.1m
`
`1.01 X 10'3 pm
`wafer
`6.55 x 10'3 pm
`site [wafer]
`
`
`reflective notching is found in Fig. 125; the severe reflective notches are
`
`flatness created by the modified double LOCOS process.
`In conclusion, we have quantitatively compared the effect of resist
`process and isolation processing upon RFLDMOS gate image CD variation,
`and found that the modified double hipox isolation process reduces the gate
`variation by close to a factor of four times. This tighter gate CD variation
`performance has allowed this device to be manufactured in volume produc—
`tion at high yields and performance levels.
`Multilayer Resist Processing—An Optimized Organic ARC Pro-
`
`Notice also that the use of ARC, which usually improves CD control
`
`where CDs are varying due to local thickness variation, has little effect upon
`the multivari CD results as would be predicted. The total CD variation is the
`same with or without ARC, again as a result of the improved wafer surface
`
`cess for I-Line Lithographic Fabrication of 0.5 pm Devices.When dyed
`resists, which have been widely used to prevent notching reflections in older
`product line fabs at greater than 1.0 pm metal linewidths, fail to provide the
`necessary reflective notching relief, multilayer processes may be employed.
`Dyed resist useage is limited by reduced contrast, resolution loss due
`to greater film thicknesses, and poorer general effectivity.[171] An example
`of the failure of dyed resist processing to prevent metal grain boundary
`
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`IPR2016-01379 Page 0024
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`278
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`Handbook of VLSI Microlithography
`
`production lines. Currently, almost all DUV applications involve either
`anisotropically dry—developed organic ARCS or inorganic ARCS, such as
`
`TiN, Si—rich nitride or an oxy—nitride film. Very few DUV resists are even
`
`tested without an appropriate ARC, all being required due to the greater
`
`reflectivity of device layers at DUV wavelengths and below.
`ARC Processing Example. Organic ARC bake conditions need to be
`
`carefully optimized and controlled for aqueous—base developed organic
`ARCs.[171][192] The bake latitude for the ARC process is found to be
`extremely critical to the lithographic results.[191][192] This section outlines
`a strategy for ARC process optimization, which led to improved litho—
`graphic results, as verified by metal electrical snake structure probe data.
`Most significantly, through ARC process optimization, including the de—
`
`velop process, it is found that the ARC application resolution range can be
`
`extended to much smaller geometries than the 0.9—1.0 urn limits
`previously reported;[171][188][191][192] these references attributed that limita-
`tion to development undercut of the ARC layer, created by the isotropic
`
`nature of it. Furthermore, the greater bake process latitude reported in Ref.
`191 has been confirmed.
`
`ARC Process Optimization Strategy. The optimization strategy en-
`
`Inorganic layers, sputtered thin films, such as a—Si, V, TiW,[171][188]
`TaSi and TiN,[189] and TiON,[190] have been tested and employed as ARC
`layers. Economic factors at larger feature sizes, however, favor the use of
`organic ARCS based upon equipment costs.[171] The example, and actually
`an older material, organic ARC referred to primarily in this chapter, is ARC—
`XLT, manufactured by Brewer Science.[191] Bilayer ARCS from this manu—
`facturer have been, and continue to be, widely used, even in volume MOS
`
`lifting. This response variable plays a key role in ARC process optimization.
`
`tails the use of the following two response variables which help by
`
`simplifying the type of experiments to be performed: (a) ARC thickness
`
`remaining after development: Experiments that use this variable as a
`
`response are very simple to perform, in that they do not require the use of
`
`photoresist or an exposure tool. The rate of ARC development is probably
`the most important factor in determining lithographic performance for a
`fixed ARC/photoresist system. This response variable is used to explore and
`
`Obtain a broad process window, while the final conditions were determined
`by further experimentation within this window using the response men-
`tioned in b, (b) Minimum CD remaining without lift off: ARC undercutting
`has been a limiting factor in determining the upper limit of resolution with
`regards to lithographic performance. A small circular pillar—like pattern is
`best for this testing because this structure is very susceptible to undercut
`
`IPR2016-01379 Page 0025
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`Resist Technology
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`279
`
`An example of a pillar functional test working specification for 0.5 pm
`MLM processing would be 0.6 :0.1 pm. Furthermore, this simple func—
`tional test provides an SPC ARC control test for routine daily qualifications.
`The following sequence of experiments were all integral parts of the
`
`optimization strategy:
`
`i. Identification of bake and develop methods: The
`following variable combinations will be discussed here:
`
`a. Convection bake/immersion develop
`
`[7. Contact bake on a hot plate/single spray puddle
`
`develop
`
`ii. Determination of bake uniformity: An acceptable level
`of ARC thickness uniformity following bake has to
`
`be achieved and verified by ellipsometry.
`
`to be the only significant variables. Henée, a two factor
`
`Screening design experiment to determine significant
`variables: This experiment was a 274 fractional
`factorial[99] using ARC thickness after development as a
`response. Wafers were coated with ARC only. Resist
`softbake /PEB were taken into account in the process
`simulation. The development time used was 5—10% of
`the actual develop time for resist coated wafers; Variables
`used in this design were:
`
`a. Dehydration b