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`Dual Damascene Processing for Semiconductor Chip Interconnects
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`FIELD OF THE INVENTION
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`The present invention relates to lithographic methods for forming a dual relief
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`pattern in a substrate, and the application of such methods to fabricating multilevel
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`interconnect structures in semiconductor chips.
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`BACKGROUND OF THE INVENTION
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`Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large
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`Scale Integrated (ULSI) semiconductor chips are typically effected by multilevel
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`interconnect structures containing patterns of metal wiring layers called traces.
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`Wiring structures within a given trace or level of wiring are separated by an
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`intralevel dielectric, while the individual wiring levels are separated from each
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`other by layers of an interlevel dielectric. Conductive vias are formed in the
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`interlevel dielectric to provide interlevel contacts between the wiring traces.
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`By means of their effects on signal propagation delays, the materials and layout of
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`these inter(cid:173) connectinterconnect structures can substantially impact chip speed, and
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`thus chip performance. Signal propagation delays are due to RC time constants
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`wherein R is the resistance of the on-chip wiring, and C is the effective capacitance
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`between the signal lines and the surrounding conductors in the multilevel
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`interconnection stack. RC time constants are reduced by lowering the specific
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`resistance of the wiring material, and by using interlevel and intralevel dielectrics
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`with lower dielectric constants.
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` A
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` preferred metal/dielectric combination for low RC interconnect structures might
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`be Cu metal with a carbon-based dielectric such as diamond-like-carbon (DLC) or
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`an organic polymer. Due to difficulties in subtractively patterning copper,
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`IP Bridge Exhibit 2011
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`IPR2016-01379
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`however, interconnect structures containing copper are typically fabricated by a
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`Damascene process. In a Damascene process, metal patterns inset in a layer of
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`dielectric are formed by the steps of
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`etching holes (for vias) or trenches (for wiring) into the interlevel or intralevel
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`dielectric,
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`optionally lining the holes or trenches with one or more adhesion or diffusion
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`barrier layers,
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`overfilling said holes and trenches with a conductive wiring material, by a process
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`such as physical vapor deposition (for example, sputtering or evaporation),
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`chemical vapor deposition, or plating, and
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`removing the metal overfill by planarizing the metal to be even with the upper
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`surface of the dielectric.
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`This process is repeated until the desired number of wiring and via levels have
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`been fabricated.
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`Fabrication of
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`interconnect structures by Damascene processing can be
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`substantially simplified by using a process variation known as Dual Damascene, in
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`which a wiring level and its underlying via level are filled in with metal in the
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`same deposition step. However, fabrication by this route requires transferring two
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`patterns to one or more layers of dielectric in a single block of lithography and/or
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`etching steps. This has previously been accomplished by using a layer of masking
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`material that is patterned twice, the first time with a via pattern and the second time
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`with a wiring pattern. This procedure typically comprises the steps of:
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`forming one or more layers of dielectric having a total thickness equal to the sum
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`of the via level and wiring level thicknesses,
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`IPR2016-01379 Page 0002
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`applying a layer of a hard mask material such as SiO2 or Si3N4 having different
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`etch characteristics than the underlying dielectric,
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`patterning the hard mask material with the via level pattern, typically by etching
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`through a photoresist stencil,
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`transferring said via level pattern into a first upper thickness of said one or more
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`layers of dielectric by a process such as etching,
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`repatterning the same layer of hard mask material with the wiring level pattern,
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`transferring the wiring level pattern into a second upper thickness of said one or
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`more layers of dielectric in such a manner as to simultaneously transfer the
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`previously etched via pattern to a bottom thickness of said one or more layers of
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`dielectric, said second upper and bottom thicknesses closely approximating the
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`wiring and via level thicknesses, respectively.
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`
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`While this "twice patterned single mask layer" process has the virtue of simplicity,
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`difficulties in reworking the second lithography step may occur if the interconnect
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`dielectric and the photoresist stencil used to pattern the hard mask have similar
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`etch characteristics. Such would be the case with an organic photoresist and a
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`carbon-based interconnect dielectric such as DLC. A typical cause for rework
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`wouldmight be a misalignment between the via-patterned hard mask/upper
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`dielectric layers and the wiring-patterned resist layer. However, lithographic
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`rework at this stage is a problem because the sidewalls of the via-patterned
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`dielectric are not protected from the resist stripping steps necessary for removing a
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`misaligned wiring-patterned resist layer.
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`
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`SUMMARY OF THE INVENTION
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`The present invention relates to improved methods for defining and transferring
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`two patterns (or a single dual relief pattern) to one or more layers of dielectric in a
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`IPR2016-01379 Page 0003
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`single block of lithography and/or etching steps. The invention comprises two
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`preferred modifications of a prior art "twice patterned single mask layer." Dual
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`Damascene process and two preferred embodiments of a fabrication process for a
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`dual pattern hard mask which may be used to form dual relief cavities for Dual
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`Damascene applications.
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`
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`The first and second preferred modifications of a prior art "twice patterned single
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`mask layer" process introduce an easy-to-integrate sidewall liner which protects
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`organic interlevel and intralevel dielectrics from potential damage induced by
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`photoresist stripping steps which may be needed, for example, during rework
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`processing to correct for lithographic misalignment. In the first modification, the
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`liner may be permanent, in which case portions of the liner can remain in the final
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`structure. In the second modification, the liner may be disposable, in which case
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`the liner would be removed from the finished structure. Use of these inventive
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`modifications allows problem-free rework with minimal impact on processing.
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`
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`The two preferred embodiments of a dual pattern hard mask fabrication process
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`provide a mask wherein the lithographic alignment for both via and wiring levels is
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`completed before any pattern transfer into the underlying interlevel/intralevel
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`dielectric. The dual pattern hard mask might preferably comprise a bottom layer of
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`silicon nitride with a first pattern and a top layer of SiO2 with a second pattern.
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`The two embodiments differ by the order in which said first and second patterns
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`are transferred into the hard mask layers.
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`
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`It is thus an object of the present invention to improve the existing "twice patterned
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`single mask layer" Dual Damascene process by adding a protective sidewall liner
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`which may or may not remain in the final structure.
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`IPR2016-01379 Page 0004
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`It is a further object of the present invention to teach the use of a Dual Damascene
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`process in which a dual pattern hard mask containing both via and wiring level
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`patterns is fabricated on a substrate comprising at least one layer of an
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`interlevel/intralevel dielectric, prior
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`to any pattern
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`transfer
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`into
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`the
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`interlevel/intralevel dielectric.
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`
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`It is a further object of the present invention to provide a general method for
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`forming a dual pattern hard mask, said dual pattern hard mask comprising a first
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`set of one or more layers with a first pattern, and a
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`
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`second set of one or more layers with a second pattern.
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`
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`It is a further object of the present invention to teach a method for transferring said
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`first and second patterns of said dual pattern hard mask to an underlying substrate
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`to form a dual relief patterned structure.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`
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`These and other features, objects, and advantages of the present invention will
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`become apparent upon a consideration of the following detailed description of the
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`invention when read in conjunction with the drawings, in which:
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`
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`FIGS. 1A-1L show in cross section view the prior art "twice patterned single mask
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`layer" Dual Damascene process flow for forming a wiring layer and its associated
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`underlying via layer;
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`IPR2016-01379 Page 0005
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`FIGS. 2A-2D show in cross section view an exaggeration of the rework problem
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`that may be encountered with the process flow of FIG. 1;
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`
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`FIGS. 3A-3G show in cross section view a first preferred modification of the FIG.
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`1 process;
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`
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`FIGS. 4A-4F show in cross section view a second preferred modification of the
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`FIG. 1 process;
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`
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`FIGS. 5A-5H illustrate in cross section view a Dual Damascene process flow
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`utilizing a first preferred embodiment of the disclosed dual pattern hard mask;
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`
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`FIGS. 6A-6J illustrate in cross section view a Dual Damascene process flow
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`utilizing a trilayer variation of a first preferred embodiment of the disclosed dual
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`pattern hard mask;
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`
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`FIGS. 7A-7I illustrate in cross section view a Dual Damascene process flow
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`utilizing a second preferred embodiment of the disclosed dual pattern hard mask;
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`and
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`
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`FIGS. 8A-8D illustrate in cross section view a three pattern hard mask, and some
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`associated materials issues.
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`
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`DESCRIPTION OF THE PREFERRED EMBODIMENTS
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`
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`FIGS. 1A-1L show in cross section view a prior art "twice patterned single mask
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`layer" Dual Damascene process flow for forming a wiring layer and its underlying
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`IPR2016-01379 Page 0006
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`via layer. The process flow may be exercised on a variety of substrates but is
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`illustrated for
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`the simplified substrate of FIG. 1A which comprises a
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`semiconductor base 2 containing arrays of electrical devices (not shown),
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`conductive via 4, and dielectric passivation layer 6.
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`layered
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`dielectric
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`stack
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`13
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`comprising
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`an
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`optional
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`dielectric
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` A
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`
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`passivation/adhesion layer 7, a via level dielectric 8, an optional dielectric etch
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`stop layer 10, and a wiring level dielectric 12 are then applied to produce the
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`structure of FIG. 1B. Via and wiring dielectrics 8 and 12 might be carbon-based
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`materials such as DLC or fluorinated DLC (FDLC), SiCO or SiCOH compounds,
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`or organic or inorganic polymer dielectrics, and optional dielectric etch stop 10
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`might be a silicon-containing material such as SiO2, Si3N4, SiOxNy, SiCOH
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`compounds, silicon-containing DLC (SiDLC), etc. The total thickness of layered
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`dielectric stack 13 closely approximates the sum of the via and wiring level
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`thicknesses.
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`
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`For a description of DLC and SiDLC, reference is made to US PatentU.S. Pat. No.
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`5,xxx,xxx;559,367 which is incorporated here by reference, for a description of
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`FDLC reference is made to US Patents NoU.S. Pat. Nos. 5,xxx,xxx462,784 and
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`5,xxx,xxx;674,638 which is incorporated herein by reference. For a description of
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`SiDLC, reference is made to US Patent No. 5,xxx,xxx.hydrogenated oxidized
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`silicon carbon material (SiCOH) and a method for making layers thereof reference
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`is made to U.S. Pat. Ser. No. 09/107,567 filed Jun. 29, 1998 by A. Grill et al
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`entitled "Hydrogenated Oxidized Silicon Carbon Material" which is incorporated
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`herein by reference.
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`IPR2016-01379 Page 0007
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`A hard mask layer 14, formed from a material such as SiO2 or Si3N4 having
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`different etch characteristics from the underlying dielectric 12, is then applied to
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`produce the structure of FIG. 1C. Hard mask layer 14 is more resistant than
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`photoresist to the etching condidtions used for transfering the photoresist pattern
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`into underlying dielectric 12. A photoresist forms a soft mask and is mainly
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`composed of organic material. The hard mask may be composed of inorganic
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`materials. A resist layer 16 patterned with a first pattern is then formed on hard
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`mask 14, as shown in FIG. 1D. The first pattern in patterned resist layer 16 would
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`typically be a via level pattern. If resist layer 16 is for some reason misaligned with
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`respect to underlying structures such as via 4, resist layer 16 may be removed by a
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`process such as ashing or wet chemical etching without damaging underlying
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`dielectric 12, since dielectric 12 is still protected by hard mask 14. Resist 16 is then
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`reapplied and patterned until the desired alignment is achieved. Hard mask layer 14
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`is then patterned with said first pattern by etching through the openings in
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`patterned resist layer 16, as shown in FIG. 1E. Said first pattern is then transferred
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`into the entire thickness of dielectric 12 by an etching process such as reactive ion
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`etching (RIE), as shown in FIG. 1F. This etching process typically also removes all
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`residuals of patterned resist layer 16.
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` A
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` resist layer 18 patterned with a second pattern is then formed on the structure of
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`FIG. 1F to produce the structure of FIG. 1G. Said second pattern in patterned resist
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`layer 18 would typically be a wiring level pattern. Hard mask layer 14 is then
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`patterned with said second pattern by etching through the openings in patterned
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`resist layer 18, as shown in FIG. 1H. Exposed regions of optional dielectric etch
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`stop 10 would typically also be removed during this etching step, as well.
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`Dielectrics 8 and 12 are then etched to transfer the second pattern into the entire
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`thickness of dielectric 12, and the first pattern into the entire thickness of dielectric
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`IPR2016-01379 Page 0008
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`8, as shown in FIG. 1I. This etching process typically also removes all residuals of
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`patterned resist layer 18. Exposed regions of optional dielectrics 10 and 7 are then
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`removed to produce the structure of FIG. 1J containing dual relief cavity 20.
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`Cavity 20 is optionally lined with one or more adhesion or diffusion barrier layers
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`(not shown) and then overfilled with conductive wiring material 22, by a process
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`such as physical vapor deposition, chemical vapor deposition, solution deposition,
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`or plating to produce the structure of FIG. 1K. Conductive wiring material 22 is
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`then planarized by a process such as chemical mechanical polishing (CMP) to be
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`approximately even with the top surface of dielectric 12 and/or remaining hard
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`mask 14. Remaining hard mask 14 is then optionally removed to produce the
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`structure of FIG. 1L. Additional wiring/via levels may be fabricated by repeating
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`the steps shown in FIGS. 1B-1L.
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`
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`FIGS. 2A-2D show in cross section view an exaggeration of the rework problem
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`that may be encountered with the process flow of FIGS. 1B-1L if resist 18 of FIG.
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`1G is misaligned. FIG. 2A shows the structure of FIG. 1F after application of resist
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`26. FIG. 2B shows the structure of FIG. 2A after resist layer 26 has been patterned
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`with said second pattern to produce misaligned patterned resist layer 28. FIG. 2C
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`shows the structure of FIG. 2B after an ashing process to remove removal of
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`misaligned patterned resist layer 28 by a process such as ashing or wet chemical
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`etching. Sidewalls 30 of dielectric 12 are clearly undercut. Such a result may not
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`be a problem when the dimensions of said second pattern substantially exceed the
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`dimensions of the first pattern, since the undercut regions would be etched anyway.
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`However, it will be a problem for cases in which the dimensions of the first and
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`second patterns are similar, as shown in FIG. 2D, since the undercut sidewall
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`profile will persist in the final structure. Such undercutting makes critical
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`dimension (CD) control more difficult and produces cavities that are more difficult
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`IPR2016-01379 Page 0009
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`to line with a conductive liner and fill with a conductive wiring material 22. An
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`additional problem encountered with this technique is that resist layer 26 is
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`necessarily thicker over the via areas. For positive-tone resist systems, this thicker
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`resist will require higher dose exposures, with consequent loss in CD control.
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`
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`FIGS. 3A-3G show a first preferred modification of the FIGS. 1A-1L, "twice
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`patterned single mask layer" process described above, in cross section view. The
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`process of FIGS. 3A-3G differs from that of FIGS. 1A-1L by the addition of a
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`sidewall liner which may remain in the final structure. In addition, the first and
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`second patterns to be transferred are the wiring and via patterns in the process of
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`FIGS. 3A-3G, as opposed to the via and wiring patterns in the process of FIGS.
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`1A-1L.
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`
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`FIG. 3A shows the structure of FIG. 1C after application of an overlayer of resist
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`34 analogous to resist layer 16, but patterned with a wiring level pattern. Hard
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`mask layer 14 is then patterned with the wiring pattern of resist layer 34, to
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`produce the structure of FIG. 3B. The wiring pattern of resist layer 34 is then
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`transferred to dielectric layer 12, and preferably to dielectric etch stop layer 10 as
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`well, to form cavity 36 in FIG. 3C. A thin layer of conductive or insulating liner
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`material 38 that may also be used as a hard mask is then conformally deposited
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`over the topography of FIG. 3C to form the lined cavity 40 shown in FIG. 3D.
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`Possible hard mask/liner materials for hard mask/liner material 38 include
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`conductive barrier materials such as the metals W, Ta, Ti, Zr, Cr, or TaNHf, the
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`metal nitrides WN, TaN, TiN, ZrN, HfN, and metal silicon nitrides such as TaSiN,
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`TiSiN, ZrSiN, and HfSiN, semiconductors such as amorphous hydrogenated
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`silicon (a-Si:H), and insulators such as SiO2, and Si3N4, and SiCOH compounds.
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`IPR2016-01379 Page 0010
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`Hard mask/liner material 38 is preferably conducting if any of it is to be left in the
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`final structure.
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`
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`FIG. 3E shows the structure of FIG. 3D after application of an overlayer of resist
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`42 patterned with a via level pattern. In the event patterned resist 42 is misaligned,
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`patterned resist 42 may be removed by a process such as ashing or wet chemical
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`etching without damaging the sidewalls of dielectric layer 12 or the top surface of
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`dielectric layer 8. The steps of applying an overlayer of resist 42 and patterning
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`resist 42 may be repeated until patterned resist 42 is properly aligned. The pattern
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`of resist layer 42 is then transferred to hard mask/liner layer 38, to produce the
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`structure of FIG. 3F, and then transferred further to dielectric layers 8 and 7 to
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`produce the dual relief cavity 44 in FIG. 3G. After optional removal (not shown) of
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`some or all of patterned hard mask/liner 38 by a process such as selective etching
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`process such as CMP, RIE, or wet etching, the structure is overfilled with a
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`conductive material and planarized, as shown in FIGS. 1K and 1L. Any portions of
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`hard mask/liner 38 remaining above dielectric 12 after the final polishing step are
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`preferably removed before fabrication of any overlying wiring or via levels.
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`
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`FIGS. 4A-4F show a second preferred modification of the FIGS. 1A-1L. "twice
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`patterned single mask layer" process, in cross section view. The process of FIGS.
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`4A-4F differs from that of FIGS. 1A-1L by the addition of a disposable sidewall
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`coating which is removed from the structure at an intermediate stage in processing.
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`However, it is similar to the prior art FIGS. 1A-1L process in that a single hard
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`mask layer is patterned twice, first with a via pattern and then with a wiring
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`pattern.
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`IPR2016-01379 Page 0011
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`FIG. 4A shows the structure of FIG. 1F after application of thin disposable liner 46
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`conformally deposited over the topography of FIG. 1F to form lined cavity 50.
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`Liner 46 may be conductive or insulating, and is preferably selected from the
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`group of materials resistant to the oxygen ashing or wet chemical etching of the
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`resist stripping process, and preferably has a thickness between 1 and 50 nm.
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`Possible liner materials include conductive materials such as the metals W, Ta, and
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`Cr, ormetal nitrides such as WN, TaN, TiN, ZrN, and Hfn, metal silicon nitrides
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`such as TaSiN, TiSiN, ZrSiN, and HfSiN, and insulating materials such as
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`amorphous hydrogenated silicon (a-Si:H), SiO2, and Si3N4, SiOxNy, SiCOH
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`compounds, SiDLC, and other silicon-containing materials. Resist layer 18
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`patterned with a wiring level pattern is then formed on the structure of FIG. 4A. If
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`resist layer 18 must be reworked, liner 46 will protect dielectric 12 from damage
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`during processing.
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`
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`If alignment of resist layer 18 with the via level pattern is satisfactory, the wiring
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`level pattern is then transferred into disposable liner 46 and, hard mask 14, and
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`etch stop 10 to form the structure of FIG. 4C which is shown with the disposable
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`liner sidewalls 52 which may sometimes be left after disposable liner 46
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`patterning. The wiring pattern of hard mask 14 is then transferred into dielectric
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`layers 12 and 10 while the via pattern in dielectrics 12 and 10 is transferred into
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`dielectrics 8 and 7. If sidewall liner 52 is still present after these etching steps, it is
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`removed by a selective etching process such as RIE or wet etching to produce the
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`structure of FIG. 4D containing cavity 54 which iswould then be overfilled with
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`conductive material 22 and planarized as shown in FIGS. 1K -and 1L.
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` A
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` satisfactory approximation to the structure of FIG. 4C may be formed from the
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`structure of FIG. 1F by etching exposed etch stop 10 in such a manner as to
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`IPR2016-01379 Page 0012
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`redeposit etch stop material to form sidewall liners 52, as illustrated in FIG. 4E. A
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`preferred resputtering process to form sidewall liners 52 would be ion beam
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`sputtering or low pressure, high bias voltage RIE.
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`
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`Alternatively, the structures of FIGS. 4E and 4F might be formed by the selective
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`deposition of a liner material 55 on the sidewalls of dielectric 12 or on both the
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`sidewalls of dielectric 12 and the exposed top surface of dielectric etch stop 10.8.
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`Selectively deposited liner material 55 might be deposited by selective chemical
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`vapor deposition, or by a surface modification treatment which could, for example,
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`selectively add Si or SiOx functionality to exposed surfaces of an organic dielectric
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`not containing Si.
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`
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`Dual pattern hard masks may comprise a first layer of a first material with a first
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`pattern and a second layer of a second material with a second pattern. While
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`materials of said first and second mask layers may be the same (and deposited as a
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`single layer), they are preferably different. More generally, a dual pattern hard
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`mask may comprise a first set of one or more layers with a first pattern, and a
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`second set of one or more layers with a second pattern, materials of said first and
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`second sets of layers selected respectively from a first group of materials and a
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`second group of materials.
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`
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`FIGS. 5A-5E show a first preferred embodiment of a method for forming a dual
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`pattern hard mask comprising a first layer of a first material with a first pattern,
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`and a second layer of a second material with a second pattern; FIGS. 5F-5H show
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`how this dual pattern hard mask may be used to fabricate a dual relief cavity for
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`use in a Dual Damascene process. For purposes of illustration, one of said first and
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`second patterns will be a via level pattern, and the other of said first and second
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`IPR2016-01379 Page 0013
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`patterns will be a wiring level pattern. However, thethis combination of via and
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`wiring level patterns should be viewed as a special casescase of the general
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`category of dual relief patterns in which all features of a smaller area (via) pattern
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`completely fit withinsubstantially overlap with the features of a larger area
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`(wiring) pattern.
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`
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`FIG. 5A shows the structure of FIG. 1B after application of lower hard mask layer
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`56 and upper hard mask layer 58. Hard mask layers 56 and 58 are preferably
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`formed from different materials which have different etch properties from each
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`other and from the dielectric underlayers 12 and 8. For example, lower hard mask
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`layer 56 might be formed from Si3N4 and upper hard mask layer 58 might be
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`formed from SiO2. Other suitable hard mask materials may include SiO2-based
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`materials, other oxides, nitrides other than Si3N4, carbon-based dielectrics,
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`andSiC-based dielectrics, polycrystalline silicon, and amorphous hydrogenated
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`silicon, and metals. A first resist layer 60, patterned with a first (wiring level)
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`pattern, is formed on layer 58 to form the structure of FIG. 5B. If resist layer 60 is
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`misaligned, rework at this stage presents no problem. The pattern of resist layer 60
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`is transferred into upper hard mask layer 58 by an etching process to form the
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`structure of FIG. 5C. The etching process is preferably selective, for example a
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`selective SiO2 to Si3N4 etch, so that lower hard mask layer 56 will remain intact
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`during any overetching of hard mask layer 58.
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`
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`Patterned resist layer 60 is then removed by a process such as ashing or wet
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`chemical etching, and a second resist layer 62, patterned with a second (via level)
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`pattern, is then formed on the structure of FIG. 5C to produce the structure of FIG.
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`5D. Again, resist rework at this stage presents no problem because lower hard
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`IPR2016-01379 Page 0014
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`mask layer 56 is still in place to protect dielectric 12. The pattern of resist layer 62
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`is then transferred
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`into lower hard mask layer 56. FIG. 5E shows the completed dual pattern hard
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`mask, comprising patterned hard mask layers 56 and 58, with patterned resist layer
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`62 still in place.
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`
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`The via level pattern is then transferred into dielectric 12 by an etching process
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`such as reactive ion etching, to produce the structure of FIG. 5F. Patterned second
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`resist layer 62 is absent from FIG. 5F because it is typically removed by the
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`etching process used to pattern dielectric 12. The etching conditions are then
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`changed to removed exposed portions of lower hard mask layer 56 and optional
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`etch stop 10, to form the structure of FIG. 5G. Dielectrics 8 and 12 are then etched
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`to transfer said second pattern into the entire thickness of dielectric 12, and said
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`first pattern into the entire thickness of dielectric 8, as shown in FIG. 5H. The
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`cavity structure may then be completed as shown in FIG. 1J, and, for interconnect
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`applications, filled with wiring material 22 as shown in FIGS. 1K toand 1L.
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`
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`FIGS. 6A-6F show a trilayer variation of the FIG. 5 method for forming a dual
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`pattern hard mask; FIGS. 6G-6J show how this dual pattern hard mask may be
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`used to fabricate a dual relief cavity for use in a Dual Damascene process. This
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`trilayer variation may be preferable to the FIG. 5 dual layer dual pattern hard mask
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`because it provides a resist-free dual pattern hard mask prior to any pattern transfer
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`into the substrate. This can be desirable when resist loading is a concern, or if the
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`resist thickness has to be thinned to allow its removal to coincide with the endpoint
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`of the cavity patterning process.
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`FIG. 6A shows the structure of FIG. 1B after application of lower hard mask layer
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`66, middle hard mask layer 68, and upper hard mask layer 70. hard mask layers 66,
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`68, and 70 are preferably formed from materials having different etch properties
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`than dielectric underlayers 12 and 8. Hard mask layers 66 and 70 may be formed
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`from the same material, but preferably one different from that of hard mask layer
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`68. For example, lower hard mask layer 66 might be formed from a 20 nm
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`thickness of Si3N4, middle hard mask layer 68 might be formed from a 50 nm
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`thickness of SiO2, and upper hard mask layer 70 might be formed from a 40 nm
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`thickness of Si02.Si3N4. Other suitable hard mask materials may include SiO2-
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`based materials, other oxides, nitrides other than Si3N4, carbon-based dielectrics,
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`and SiC-based dielectrics, polycrystalline silicon, and amorphous hydrogenated
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`silicon, and metals.
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` A
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` first resist layer 72, patterned with a first (wiring level) pattern, is formed on
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`layer 70 to form the structure of FIG. 6B. If resist layer 72 is misaligned, rework at
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`this stage presents no problem. The pattern of resist layer 72 is transferred into
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`upper hard mask layer 70 by an etching process. Said etching process might
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`preferably be selective with respect to hard mask layer 68, but it may be
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`nonselective as well. Patterned resist layer 72 is then removed by a process such as
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`ashing or wet chemical etching to form the structure of FIG. 6C.
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` A
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` second resist layer 74, patterned with a second (via level) pattern, is then formed
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`on the structure of FIG. 6C to produce the structure of FIG. 6D. Again, resist
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`rework at this stage presents no problem. The pattern of resist layer 74 is then
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`transferred into middle hard mask layer 68 by an etching process. Said etching
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`process is preferably selective with respect to hard mask layer 66, for example, a
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`selective oxide to nitride etch for the preferred hard mask layer materials cited
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`above. Patterned resist layer 74 is then preferably removed by a process such as
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`ashing or wet chemical etching to form the structure of FIG. 6E. The via pattern of
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`patterned hard mask layer 68 is then transferred to bottom hard mask layer 66 by
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`an etching process that may be selective or nonselective to produce the completed,
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`resist-free trilayer dual pattern hard mask of FIG. 6F, comprising patterned hard
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`mask layers 66, 68, and 70.
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`
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`The via level pattern is then transferred into dielectric 12 by an etching process
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`such as reactive ion etching, to produce the structure of FIG. 6G. The etching
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`conditions are then changed to removed exposed portions of middle hard mask
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`layer 68 and optional etch stop 10, to form the structure of FIG. 6H with wiring
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`level pattern contained in middle and top hard mask layers 68 and 70. The wiring
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`level pattern is then transferred into bottom hard mask layer 66 by an etching
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`process that would typically also remove the exposed portions of hard mask 70, to
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`produce the structure of FIG. 6I. Dielectrics 8 and 12 are then etched to transfer
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`said second (wiring level) pattern into the entire thickness of dielectric 12, and said
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`first (via level) pattern into the entire thickness of dielectric 8, as shown in FIG. 6J.
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`The cavity structure may then be completed as shown in FIG. 1J, and, for
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`interconnect applications, filled with wiring material as shown in FIGS. 1K to 1L.
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`
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`FIGS. 7A-7E show a second preferred embodiment of a method for forming a dual
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`pattern hard mask comprising a first layer of a first material with a first pattern,
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`and a second layer of a second material with a second pattern; and FIGS. 7F-7I
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`show how this dual pattern hard mask may be used to fabricate a dual relief cavity
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`for use in a Dual Damascene process. The main difference between the second
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`embodiment of FIGS. 7A-7I and the first embodiment of FIGS. 5A-5H is the order
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`in which the via and wiring level patterns are transferred into the two layers of the
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`dual pattern hard mask.
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`
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`FIG. 7A shows the structure of FIG. 1B after application of lower hard mask layer
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`76 and upper hard mask layer 78. Hard mask layers 76 and 78 are preferably
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`formed from different materials which have different etch properties from each
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`other and from the dielectric underlayers 12 and 8. For example, lower hard mask
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`layer 76 might be formed from Si3N4 and upper hard mask layer 78 might be
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`formed from SiO2. A first resist layer 80, patterned with a via level pattern, is
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`formed on layer 78 to form the structure of FIG. 7B. If resist layer 80 is
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`misaligned, rework at this stage presents no problem. The pattern of resist layer 80
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`is transferred into upper hard mask layer 78 by an etching process to form the
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`structure of FIG. 7C. Said etching process is preferably selective, for example a
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`selective SiO2 to Si3N4 etch, to ensureinsure that lower hard mask layer 76 will
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`remain intact during any overetching of hard mask layer 78.
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`
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`Patterned resist layer 80 is then removed by a process such as ashing or wet
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`chemical etching and a second resist layer 82, patterned with a wiring level pattern,
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`is then formed on the structure of FIG. 7C to pro